1 /* 2 * arch/arm/include/asm/tlbflush.h 3 * 4 * Copyright (C) 1999-2003 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _ASMARM_TLBFLUSH_H 11 #define _ASMARM_TLBFLUSH_H 12 13 #ifdef CONFIG_MMU 14 15 #include <asm/glue.h> 16 17 #define TLB_V3_PAGE (1 << 0) 18 #define TLB_V4_U_PAGE (1 << 1) 19 #define TLB_V4_D_PAGE (1 << 2) 20 #define TLB_V4_I_PAGE (1 << 3) 21 #define TLB_V6_U_PAGE (1 << 4) 22 #define TLB_V6_D_PAGE (1 << 5) 23 #define TLB_V6_I_PAGE (1 << 6) 24 25 #define TLB_V3_FULL (1 << 8) 26 #define TLB_V4_U_FULL (1 << 9) 27 #define TLB_V4_D_FULL (1 << 10) 28 #define TLB_V4_I_FULL (1 << 11) 29 #define TLB_V6_U_FULL (1 << 12) 30 #define TLB_V6_D_FULL (1 << 13) 31 #define TLB_V6_I_FULL (1 << 14) 32 33 #define TLB_V6_U_ASID (1 << 16) 34 #define TLB_V6_D_ASID (1 << 17) 35 #define TLB_V6_I_ASID (1 << 18) 36 37 #define TLB_V6_BP (1 << 19) 38 39 /* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */ 40 #define TLB_V7_UIS_PAGE (1 << 20) 41 #define TLB_V7_UIS_FULL (1 << 21) 42 #define TLB_V7_UIS_ASID (1 << 22) 43 #define TLB_V7_UIS_BP (1 << 23) 44 45 #define TLB_BARRIER (1 << 28) 46 #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ 47 #define TLB_DCLEAN (1 << 30) 48 #define TLB_WB (1 << 31) 49 50 /* 51 * MMU TLB Model 52 * ============= 53 * 54 * We have the following to choose from: 55 * v3 - ARMv3 56 * v4 - ARMv4 without write buffer 57 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction 58 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction 59 * fr - Feroceon (v4wbi with non-outer-cacheable page table walks) 60 * fa - Faraday (v4 with write buffer with UTLB) 61 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction 62 * v7wbi - identical to v6wbi 63 */ 64 #undef _TLB 65 #undef MULTI_TLB 66 67 #ifdef CONFIG_SMP_ON_UP 68 #define MULTI_TLB 1 69 #endif 70 71 #define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE) 72 73 #ifdef CONFIG_CPU_TLB_V4WT 74 # define v4_possible_flags v4_tlb_flags 75 # define v4_always_flags v4_tlb_flags 76 # ifdef _TLB 77 # define MULTI_TLB 1 78 # else 79 # define _TLB v4 80 # endif 81 #else 82 # define v4_possible_flags 0 83 # define v4_always_flags (-1UL) 84 #endif 85 86 #define fa_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 87 TLB_V4_U_FULL | TLB_V4_U_PAGE) 88 89 #ifdef CONFIG_CPU_TLB_FA 90 # define fa_possible_flags fa_tlb_flags 91 # define fa_always_flags fa_tlb_flags 92 # ifdef _TLB 93 # define MULTI_TLB 1 94 # else 95 # define _TLB fa 96 # endif 97 #else 98 # define fa_possible_flags 0 99 # define fa_always_flags (-1UL) 100 #endif 101 102 #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ 103 TLB_V4_I_FULL | TLB_V4_D_FULL | \ 104 TLB_V4_I_PAGE | TLB_V4_D_PAGE) 105 106 #ifdef CONFIG_CPU_TLB_V4WBI 107 # define v4wbi_possible_flags v4wbi_tlb_flags 108 # define v4wbi_always_flags v4wbi_tlb_flags 109 # ifdef _TLB 110 # define MULTI_TLB 1 111 # else 112 # define _TLB v4wbi 113 # endif 114 #else 115 # define v4wbi_possible_flags 0 116 # define v4wbi_always_flags (-1UL) 117 #endif 118 119 #define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \ 120 TLB_V4_I_FULL | TLB_V4_D_FULL | \ 121 TLB_V4_I_PAGE | TLB_V4_D_PAGE) 122 123 #ifdef CONFIG_CPU_TLB_FEROCEON 124 # define fr_possible_flags fr_tlb_flags 125 # define fr_always_flags fr_tlb_flags 126 # ifdef _TLB 127 # define MULTI_TLB 1 128 # else 129 # define _TLB v4wbi 130 # endif 131 #else 132 # define fr_possible_flags 0 133 # define fr_always_flags (-1UL) 134 #endif 135 136 #define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \ 137 TLB_V4_I_FULL | TLB_V4_D_FULL | \ 138 TLB_V4_D_PAGE) 139 140 #ifdef CONFIG_CPU_TLB_V4WB 141 # define v4wb_possible_flags v4wb_tlb_flags 142 # define v4wb_always_flags v4wb_tlb_flags 143 # ifdef _TLB 144 # define MULTI_TLB 1 145 # else 146 # define _TLB v4wb 147 # endif 148 #else 149 # define v4wb_possible_flags 0 150 # define v4wb_always_flags (-1UL) 151 #endif 152 153 #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 154 TLB_V6_I_FULL | TLB_V6_D_FULL | \ 155 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ 156 TLB_V6_I_ASID | TLB_V6_D_ASID | \ 157 TLB_V6_BP) 158 159 #ifdef CONFIG_CPU_TLB_V6 160 # define v6wbi_possible_flags v6wbi_tlb_flags 161 # define v6wbi_always_flags v6wbi_tlb_flags 162 # ifdef _TLB 163 # define MULTI_TLB 1 164 # else 165 # define _TLB v6wbi 166 # endif 167 #else 168 # define v6wbi_possible_flags 0 169 # define v6wbi_always_flags (-1UL) 170 #endif 171 172 #define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 173 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \ 174 TLB_V7_UIS_ASID | TLB_V7_UIS_BP) 175 #define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \ 176 TLB_V6_U_FULL | TLB_V6_U_PAGE | \ 177 TLB_V6_U_ASID | TLB_V6_BP) 178 179 #ifdef CONFIG_CPU_TLB_V7 180 181 # ifdef CONFIG_SMP_ON_UP 182 # define v7wbi_possible_flags (v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up) 183 # define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up) 184 # elif defined(CONFIG_SMP) 185 # define v7wbi_possible_flags v7wbi_tlb_flags_smp 186 # define v7wbi_always_flags v7wbi_tlb_flags_smp 187 # else 188 # define v7wbi_possible_flags v7wbi_tlb_flags_up 189 # define v7wbi_always_flags v7wbi_tlb_flags_up 190 # endif 191 # ifdef _TLB 192 # define MULTI_TLB 1 193 # else 194 # define _TLB v7wbi 195 # endif 196 #else 197 # define v7wbi_possible_flags 0 198 # define v7wbi_always_flags (-1UL) 199 #endif 200 201 #ifndef _TLB 202 #error Unknown TLB model 203 #endif 204 205 #ifndef __ASSEMBLY__ 206 207 #include <linux/sched.h> 208 209 struct cpu_tlb_fns { 210 void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *); 211 void (*flush_kern_range)(unsigned long, unsigned long); 212 unsigned long tlb_flags; 213 }; 214 215 /* 216 * Select the calling method 217 */ 218 #ifdef MULTI_TLB 219 220 #define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range 221 #define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range 222 223 #else 224 225 #define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range) 226 #define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range) 227 228 extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *); 229 extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long); 230 231 #endif 232 233 extern struct cpu_tlb_fns cpu_tlb; 234 235 #define __cpu_tlb_flags cpu_tlb.tlb_flags 236 237 /* 238 * TLB Management 239 * ============== 240 * 241 * The arch/arm/mm/tlb-*.S files implement these methods. 242 * 243 * The TLB specific code is expected to perform whatever tests it 244 * needs to determine if it should invalidate the TLB for each 245 * call. Start addresses are inclusive and end addresses are 246 * exclusive; it is safe to round these addresses down. 247 * 248 * flush_tlb_all() 249 * 250 * Invalidate the entire TLB. 251 * 252 * flush_tlb_mm(mm) 253 * 254 * Invalidate all TLB entries in a particular address 255 * space. 256 * - mm - mm_struct describing address space 257 * 258 * flush_tlb_range(mm,start,end) 259 * 260 * Invalidate a range of TLB entries in the specified 261 * address space. 262 * - mm - mm_struct describing address space 263 * - start - start address (may not be aligned) 264 * - end - end address (exclusive, may not be aligned) 265 * 266 * flush_tlb_page(vaddr,vma) 267 * 268 * Invalidate the specified page in the specified address range. 269 * - vaddr - virtual address (may not be aligned) 270 * - vma - vma_struct describing address range 271 * 272 * flush_kern_tlb_page(kaddr) 273 * 274 * Invalidate the TLB entry for the specified page. The address 275 * will be in the kernels virtual memory space. Current uses 276 * only require the D-TLB to be invalidated. 277 * - kaddr - Kernel virtual memory address 278 */ 279 280 /* 281 * We optimise the code below by: 282 * - building a set of TLB flags that might be set in __cpu_tlb_flags 283 * - building a set of TLB flags that will always be set in __cpu_tlb_flags 284 * - if we're going to need __cpu_tlb_flags, access it once and only once 285 * 286 * This allows us to build optimal assembly for the single-CPU type case, 287 * and as close to optimal given the compiler constrants for multi-CPU 288 * case. We could do better for the multi-CPU case if the compiler 289 * implemented the "%?" method, but this has been discontinued due to too 290 * many people getting it wrong. 291 */ 292 #define possible_tlb_flags (v4_possible_flags | \ 293 v4wbi_possible_flags | \ 294 fr_possible_flags | \ 295 v4wb_possible_flags | \ 296 fa_possible_flags | \ 297 v6wbi_possible_flags | \ 298 v7wbi_possible_flags) 299 300 #define always_tlb_flags (v4_always_flags & \ 301 v4wbi_always_flags & \ 302 fr_always_flags & \ 303 v4wb_always_flags & \ 304 fa_always_flags & \ 305 v6wbi_always_flags & \ 306 v7wbi_always_flags) 307 308 #define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) 309 310 #define __tlb_op(f, insnarg, arg) \ 311 do { \ 312 if (always_tlb_flags & (f)) \ 313 asm("mcr " insnarg \ 314 : : "r" (arg) : "cc"); \ 315 else if (possible_tlb_flags & (f)) \ 316 asm("tst %1, %2\n\t" \ 317 "mcrne " insnarg \ 318 : : "r" (arg), "r" (__tlb_flag), "Ir" (f) \ 319 : "cc"); \ 320 } while (0) 321 322 #define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg) 323 #define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg) 324 325 static inline void local_flush_tlb_all(void) 326 { 327 const int zero = 0; 328 const unsigned int __tlb_flag = __cpu_tlb_flags; 329 330 if (tlb_flag(TLB_WB)) 331 dsb(); 332 333 tlb_op(TLB_V3_FULL, "c6, c0, 0", zero); 334 tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero); 335 tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero); 336 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); 337 tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero); 338 339 if (tlb_flag(TLB_BARRIER)) { 340 dsb(); 341 isb(); 342 } 343 } 344 345 static inline void local_flush_tlb_mm(struct mm_struct *mm) 346 { 347 const int zero = 0; 348 const int asid = ASID(mm); 349 const unsigned int __tlb_flag = __cpu_tlb_flags; 350 351 if (tlb_flag(TLB_WB)) 352 dsb(); 353 354 if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) { 355 if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { 356 tlb_op(TLB_V3_FULL, "c6, c0, 0", zero); 357 tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero); 358 tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero); 359 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); 360 } 361 put_cpu(); 362 } 363 364 tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid); 365 tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid); 366 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid); 367 #ifdef CONFIG_ARM_ERRATA_720789 368 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero); 369 #else 370 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid); 371 #endif 372 373 if (tlb_flag(TLB_BARRIER)) 374 dsb(); 375 } 376 377 static inline void 378 local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 379 { 380 const int zero = 0; 381 const unsigned int __tlb_flag = __cpu_tlb_flags; 382 383 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); 384 385 if (tlb_flag(TLB_WB)) 386 dsb(); 387 388 if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) && 389 cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { 390 tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr); 391 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr); 392 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr); 393 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr); 394 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) 395 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); 396 } 397 398 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr); 399 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr); 400 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr); 401 #ifdef CONFIG_ARM_ERRATA_720789 402 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK); 403 #else 404 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr); 405 #endif 406 407 if (tlb_flag(TLB_BARRIER)) 408 dsb(); 409 } 410 411 static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 412 { 413 const int zero = 0; 414 const unsigned int __tlb_flag = __cpu_tlb_flags; 415 416 kaddr &= PAGE_MASK; 417 418 if (tlb_flag(TLB_WB)) 419 dsb(); 420 421 tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr); 422 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr); 423 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr); 424 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); 425 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL)) 426 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); 427 428 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr); 429 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr); 430 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr); 431 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr); 432 433 if (tlb_flag(TLB_BARRIER)) { 434 dsb(); 435 isb(); 436 } 437 } 438 439 static inline void local_flush_bp_all(void) 440 { 441 const int zero = 0; 442 const unsigned int __tlb_flag = __cpu_tlb_flags; 443 444 if (tlb_flag(TLB_V7_UIS_BP)) 445 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); 446 else if (tlb_flag(TLB_V6_BP)) 447 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); 448 449 if (tlb_flag(TLB_BARRIER)) 450 isb(); 451 } 452 453 /* 454 * flush_pmd_entry 455 * 456 * Flush a PMD entry (word aligned, or double-word aligned) to 457 * RAM if the TLB for the CPU we are running on requires this. 458 * This is typically used when we are creating PMD entries. 459 * 460 * clean_pmd_entry 461 * 462 * Clean (but don't drain the write buffer) if the CPU requires 463 * these operations. This is typically used when we are removing 464 * PMD entries. 465 */ 466 static inline void flush_pmd_entry(void *pmd) 467 { 468 const unsigned int __tlb_flag = __cpu_tlb_flags; 469 470 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd); 471 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd); 472 473 if (tlb_flag(TLB_WB)) 474 dsb(); 475 } 476 477 static inline void clean_pmd_entry(void *pmd) 478 { 479 const unsigned int __tlb_flag = __cpu_tlb_flags; 480 481 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd); 482 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd); 483 } 484 485 #undef tlb_op 486 #undef tlb_flag 487 #undef always_tlb_flags 488 #undef possible_tlb_flags 489 490 /* 491 * Convert calls to our calling convention. 492 */ 493 #define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) 494 #define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) 495 496 #ifndef CONFIG_SMP 497 #define flush_tlb_all local_flush_tlb_all 498 #define flush_tlb_mm local_flush_tlb_mm 499 #define flush_tlb_page local_flush_tlb_page 500 #define flush_tlb_kernel_page local_flush_tlb_kernel_page 501 #define flush_tlb_range local_flush_tlb_range 502 #define flush_tlb_kernel_range local_flush_tlb_kernel_range 503 #define flush_bp_all local_flush_bp_all 504 #else 505 extern void flush_tlb_all(void); 506 extern void flush_tlb_mm(struct mm_struct *mm); 507 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr); 508 extern void flush_tlb_kernel_page(unsigned long kaddr); 509 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 510 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); 511 extern void flush_bp_all(void); 512 #endif 513 514 /* 515 * If PG_dcache_clean is not set for the page, we need to ensure that any 516 * cache entries for the kernels virtual memory range are written 517 * back to the page. On ARMv6 and later, the cache coherency is handled via 518 * the set_pte_at() function. 519 */ 520 #if __LINUX_ARM_ARCH__ < 6 521 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, 522 pte_t *ptep); 523 #else 524 static inline void update_mmu_cache(struct vm_area_struct *vma, 525 unsigned long addr, pte_t *ptep) 526 { 527 } 528 #endif 529 530 #endif 531 532 #endif /* CONFIG_MMU */ 533 534 #endif 535