xref: /linux/arch/arm/include/asm/pgtable.h (revision 5b0764a53235d3c77e1ed674e836e1b3fe1a4b1f)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  arch/arm/include/asm/pgtable.h
4  *
5  *  Copyright (C) 1995-2002 Russell King
6  */
7 #ifndef _ASMARM_PGTABLE_H
8 #define _ASMARM_PGTABLE_H
9 
10 #include <linux/const.h>
11 #include <asm/proc-fns.h>
12 
13 #include <asm-generic/pgtable-nopud.h>
14 
15 #ifndef CONFIG_MMU
16 #include <asm/pgtable-nommu.h>
17 
18 #else
19 
20 #include <asm/page.h>
21 #include <asm/pgtable-hwdef.h>
22 
23 
24 #include <asm/tlbflush.h>
25 
26 #ifdef CONFIG_ARM_LPAE
27 #include <asm/pgtable-3level.h>
28 #else
29 #include <asm/pgtable-2level.h>
30 #endif
31 
32 /*
33  * Just any arbitrary offset to the start of the vmalloc VM area: the
34  * current 8MB value just means that there will be a 8MB "hole" after the
35  * physical memory until the kernel virtual memory starts.  That means that
36  * any out-of-bounds memory accesses will hopefully be caught.
37  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
38  * area for the same reason. ;)
39  */
40 #define VMALLOC_OFFSET		(8*1024*1024)
41 #define VMALLOC_START		(((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
42 #define VMALLOC_END		0xff800000UL
43 
44 #define LIBRARY_TEXT_START	0x0c000000
45 
46 #ifndef __ASSEMBLY__
47 
48 /*
49  * This is the lowest virtual address we can permit any user space
50  * mapping to be mapped at.  This is particularly important for
51  * non-high vector CPUs.
52  */
53 #define FIRST_USER_ADDRESS	(PAGE_SIZE * 2)
54 
55 /*
56  * Use TASK_SIZE as the ceiling argument for free_pgtables() and
57  * free_pgd_range() to avoid freeing the modules pmd when LPAE is enabled (pmd
58  * page shared between user and kernel).
59  */
60 #ifdef CONFIG_ARM_LPAE
61 #define USER_PGTABLES_CEILING	TASK_SIZE
62 #endif
63 
64 /*
65  * The pgprot_* and protection_map entries will be fixed up in runtime
66  * to include the cachable and bufferable bits based on memory policy,
67  * as well as any architecture dependent bits like global/ASID and SMP
68  * shared mapping bits.
69  */
70 #define _L_PTE_DEFAULT	L_PTE_PRESENT | L_PTE_YOUNG
71 
72 extern pgprot_t		pgprot_user;
73 extern pgprot_t		pgprot_kernel;
74 
75 #define _MOD_PROT(p, b)	__pgprot(pgprot_val(p) | (b))
76 
77 #define PAGE_NONE		_MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY | L_PTE_NONE)
78 #define PAGE_SHARED		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN)
79 #define PAGE_SHARED_EXEC	_MOD_PROT(pgprot_user, L_PTE_USER)
80 #define PAGE_COPY		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
81 #define PAGE_COPY_EXEC		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
82 #define PAGE_READONLY		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
83 #define PAGE_READONLY_EXEC	_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
84 #define PAGE_KERNEL		_MOD_PROT(pgprot_kernel, L_PTE_XN)
85 #define PAGE_KERNEL_EXEC	pgprot_kernel
86 
87 #define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
88 #define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
89 #define __PAGE_SHARED_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER)
90 #define __PAGE_COPY		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
91 #define __PAGE_COPY_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
92 #define __PAGE_READONLY		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
93 #define __PAGE_READONLY_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
94 
95 #define __pgprot_modify(prot,mask,bits)		\
96 	__pgprot((pgprot_val(prot) & ~(mask)) | (bits))
97 
98 #define pgprot_noncached(prot) \
99 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
100 
101 #define pgprot_writecombine(prot) \
102 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
103 
104 #define pgprot_stronglyordered(prot) \
105 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
106 
107 #define pgprot_device(prot) \
108 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN)
109 
110 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
111 #define pgprot_dmacoherent(prot) \
112 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
113 #define __HAVE_PHYS_MEM_ACCESS_PROT
114 struct file;
115 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
116 				     unsigned long size, pgprot_t vma_prot);
117 #else
118 #define pgprot_dmacoherent(prot) \
119 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
120 #endif
121 
122 #endif /* __ASSEMBLY__ */
123 
124 /*
125  * The table below defines the page protection levels that we insert into our
126  * Linux page table version.  These get translated into the best that the
127  * architecture can perform.  Note that on most ARM hardware:
128  *  1) We cannot do execute protection
129  *  2) If we could do execute protection, then read is implied
130  *  3) write implies read permissions
131  */
132 
133 #ifndef __ASSEMBLY__
134 
135 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
136 
137 #define pgdp_get(pgpd)		READ_ONCE(*pgdp)
138 
139 #define pud_page(pud)		pmd_page(__pmd(pud_val(pud)))
140 #define pud_write(pud)		pmd_write(__pmd(pud_val(pud)))
141 
142 #define pmd_none(pmd)		(!pmd_val(pmd))
143 
144 static inline pte_t *pmd_page_vaddr(pmd_t pmd)
145 {
146 	return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
147 }
148 
149 #define pmd_page(pmd)		pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
150 
151 #define pte_pfn(pte)		((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
152 #define pfn_pte(pfn,prot)	__pte(__pfn_to_phys(pfn) | pgprot_val(prot))
153 
154 #define pte_page(pte)		pfn_to_page(pte_pfn(pte))
155 
156 #define pte_clear(mm,addr,ptep)	set_pte_ext(ptep, __pte(0), 0)
157 
158 #define pte_isset(pte, val)	((u32)(val) == (val) ? pte_val(pte) & (val) \
159 						: !!(pte_val(pte) & (val)))
160 #define pte_isclear(pte, val)	(!(pte_val(pte) & (val)))
161 
162 #define pte_none(pte)		(!pte_val(pte))
163 #define pte_present(pte)	(pte_isset((pte), L_PTE_PRESENT))
164 #define pte_valid(pte)		(pte_isset((pte), L_PTE_VALID))
165 #define pte_accessible(mm, pte)	(mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
166 #define pte_write(pte)		(pte_isclear((pte), L_PTE_RDONLY))
167 #define pte_dirty(pte)		(pte_isset((pte), L_PTE_DIRTY))
168 #define pte_young(pte)		(pte_isset((pte), L_PTE_YOUNG))
169 #define pte_exec(pte)		(pte_isclear((pte), L_PTE_XN))
170 
171 #define pte_valid_user(pte)	\
172 	(pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
173 
174 static inline bool pte_access_permitted(pte_t pte, bool write)
175 {
176 	pteval_t mask = L_PTE_PRESENT | L_PTE_USER;
177 	pteval_t needed = mask;
178 
179 	if (write)
180 		mask |= L_PTE_RDONLY;
181 
182 	return (pte_val(pte) & mask) == needed;
183 }
184 #define pte_access_permitted pte_access_permitted
185 
186 #if __LINUX_ARM_ARCH__ < 6
187 static inline void __sync_icache_dcache(pte_t pteval)
188 {
189 }
190 #else
191 extern void __sync_icache_dcache(pte_t pteval);
192 #endif
193 
194 #define PFN_PTE_SHIFT		PAGE_SHIFT
195 
196 void set_ptes(struct mm_struct *mm, unsigned long addr,
197 		      pte_t *ptep, pte_t pteval, unsigned int nr);
198 #define set_ptes set_ptes
199 
200 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
201 {
202 	pte_val(pte) &= ~pgprot_val(prot);
203 	return pte;
204 }
205 
206 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
207 {
208 	pte_val(pte) |= pgprot_val(prot);
209 	return pte;
210 }
211 
212 static inline pte_t pte_wrprotect(pte_t pte)
213 {
214 	return set_pte_bit(pte, __pgprot(L_PTE_RDONLY));
215 }
216 
217 static inline pte_t pte_mkwrite_novma(pte_t pte)
218 {
219 	return clear_pte_bit(pte, __pgprot(L_PTE_RDONLY));
220 }
221 
222 static inline pte_t pte_mkclean(pte_t pte)
223 {
224 	return clear_pte_bit(pte, __pgprot(L_PTE_DIRTY));
225 }
226 
227 static inline pte_t pte_mkdirty(pte_t pte)
228 {
229 	return set_pte_bit(pte, __pgprot(L_PTE_DIRTY));
230 }
231 
232 static inline pte_t pte_mkold(pte_t pte)
233 {
234 	return clear_pte_bit(pte, __pgprot(L_PTE_YOUNG));
235 }
236 
237 static inline pte_t pte_mkyoung(pte_t pte)
238 {
239 	return set_pte_bit(pte, __pgprot(L_PTE_YOUNG));
240 }
241 
242 static inline pte_t pte_mkexec(pte_t pte)
243 {
244 	return clear_pte_bit(pte, __pgprot(L_PTE_XN));
245 }
246 
247 static inline pte_t pte_mknexec(pte_t pte)
248 {
249 	return set_pte_bit(pte, __pgprot(L_PTE_XN));
250 }
251 
252 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
253 {
254 	const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
255 		L_PTE_NONE | L_PTE_VALID;
256 	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
257 	return pte;
258 }
259 
260 /*
261  * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
262  * are !pte_none() && !pte_present().
263  *
264  * Format of swap PTEs:
265  *
266  *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
267  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
268  *   <------------------- offset ------------------> E < type -> 0 0
269  *
270  *   E is the exclusive marker that is not stored in swap entries.
271  *
272  * This gives us up to 31 swap files and 64GB per swap file.  Note that
273  * the offset field is always non-zero.
274  */
275 #define __SWP_TYPE_SHIFT	2
276 #define __SWP_TYPE_BITS		5
277 #define __SWP_TYPE_MASK		((1 << __SWP_TYPE_BITS) - 1)
278 #define __SWP_OFFSET_SHIFT	(__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1)
279 
280 #define __swp_type(x)		(((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
281 #define __swp_offset(x)		((x).val >> __SWP_OFFSET_SHIFT)
282 #define __swp_entry(type, offset) ((swp_entry_t) { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \
283 						   ((offset) << __SWP_OFFSET_SHIFT) })
284 
285 #define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
286 #define __swp_entry_to_pte(swp)	__pte((swp).val)
287 
288 static inline bool pte_swp_exclusive(pte_t pte)
289 {
290 	return pte_isset(pte, L_PTE_SWP_EXCLUSIVE);
291 }
292 
293 static inline pte_t pte_swp_mkexclusive(pte_t pte)
294 {
295 	return set_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
296 }
297 
298 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
299 {
300 	return clear_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
301 }
302 
303 /*
304  * It is an error for the kernel to have more swap files than we can
305  * encode in the PTEs.  This ensures that we know when MAX_SWAPFILES
306  * is increased beyond what we presently support.
307  */
308 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
309 
310 /*
311  * We provide our own arch_get_unmapped_area to cope with VIPT caches.
312  */
313 #define HAVE_ARCH_UNMAPPED_AREA
314 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
315 
316 #endif /* !__ASSEMBLY__ */
317 
318 #endif /* CONFIG_MMU */
319 
320 #endif /* _ASMARM_PGTABLE_H */
321