1 /* 2 * arch/arm/include/asm/mmu_context.h 3 * 4 * Copyright (C) 1996 Russell King. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Changelog: 11 * 27-06-1996 RMK Created 12 */ 13 #ifndef __ASM_ARM_MMU_CONTEXT_H 14 #define __ASM_ARM_MMU_CONTEXT_H 15 16 #include <linux/compiler.h> 17 #include <linux/sched.h> 18 #include <asm/cacheflush.h> 19 #include <asm/cachetype.h> 20 #include <asm/proc-fns.h> 21 #include <asm-generic/mm_hooks.h> 22 23 void __check_kvm_seq(struct mm_struct *mm); 24 25 #ifdef CONFIG_CPU_HAS_ASID 26 27 /* 28 * On ARMv6, we have the following structure in the Context ID: 29 * 30 * 31 7 0 31 * +-------------------------+-----------+ 32 * | process ID | ASID | 33 * +-------------------------+-----------+ 34 * | context ID | 35 * +-------------------------------------+ 36 * 37 * The ASID is used to tag entries in the CPU caches and TLBs. 38 * The context ID is used by debuggers and trace logic, and 39 * should be unique within all running processes. 40 */ 41 #define ASID_BITS 8 42 #define ASID_MASK ((~0) << ASID_BITS) 43 #define ASID_FIRST_VERSION (1 << ASID_BITS) 44 45 extern unsigned int cpu_last_asid; 46 47 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm); 48 void __new_context(struct mm_struct *mm); 49 void cpu_set_reserved_ttbr0(void); 50 51 static inline void switch_new_context(struct mm_struct *mm) 52 { 53 unsigned long flags; 54 55 __new_context(mm); 56 57 local_irq_save(flags); 58 cpu_switch_mm(mm->pgd, mm); 59 local_irq_restore(flags); 60 } 61 62 static inline void check_and_switch_context(struct mm_struct *mm, 63 struct task_struct *tsk) 64 { 65 if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq)) 66 __check_kvm_seq(mm); 67 68 /* 69 * Required during context switch to avoid speculative page table 70 * walking with the wrong TTBR. 71 */ 72 cpu_set_reserved_ttbr0(); 73 74 if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) 75 /* 76 * The ASID is from the current generation, just switch to the 77 * new pgd. This condition is only true for calls from 78 * context_switch() and interrupts are already disabled. 79 */ 80 cpu_switch_mm(mm->pgd, mm); 81 else if (irqs_disabled()) 82 /* 83 * Defer the new ASID allocation until after the context 84 * switch critical region since __new_context() cannot be 85 * called with interrupts disabled (it sends IPIs). 86 */ 87 set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM); 88 else 89 /* 90 * That is a direct call to switch_mm() or activate_mm() with 91 * interrupts enabled and a new context. 92 */ 93 switch_new_context(mm); 94 } 95 96 #define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0) 97 98 #define finish_arch_post_lock_switch \ 99 finish_arch_post_lock_switch 100 static inline void finish_arch_post_lock_switch(void) 101 { 102 if (test_and_clear_thread_flag(TIF_SWITCH_MM)) 103 switch_new_context(current->mm); 104 } 105 106 #else /* !CONFIG_CPU_HAS_ASID */ 107 108 #ifdef CONFIG_MMU 109 110 static inline void check_and_switch_context(struct mm_struct *mm, 111 struct task_struct *tsk) 112 { 113 if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq)) 114 __check_kvm_seq(mm); 115 116 if (irqs_disabled()) 117 /* 118 * cpu_switch_mm() needs to flush the VIVT caches. To avoid 119 * high interrupt latencies, defer the call and continue 120 * running with the old mm. Since we only support UP systems 121 * on non-ASID CPUs, the old mm will remain valid until the 122 * finish_arch_post_lock_switch() call. 123 */ 124 set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM); 125 else 126 cpu_switch_mm(mm->pgd, mm); 127 } 128 129 #define finish_arch_post_lock_switch \ 130 finish_arch_post_lock_switch 131 static inline void finish_arch_post_lock_switch(void) 132 { 133 if (test_and_clear_thread_flag(TIF_SWITCH_MM)) { 134 struct mm_struct *mm = current->mm; 135 cpu_switch_mm(mm->pgd, mm); 136 } 137 } 138 139 #endif /* CONFIG_MMU */ 140 141 #define init_new_context(tsk,mm) 0 142 143 #endif /* CONFIG_CPU_HAS_ASID */ 144 145 #define destroy_context(mm) do { } while(0) 146 147 /* 148 * This is called when "tsk" is about to enter lazy TLB mode. 149 * 150 * mm: describes the currently active mm context 151 * tsk: task which is entering lazy tlb 152 * cpu: cpu number which is entering lazy tlb 153 * 154 * tsk->mm will be NULL 155 */ 156 static inline void 157 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 158 { 159 } 160 161 /* 162 * This is the actual mm switch as far as the scheduler 163 * is concerned. No registers are touched. We avoid 164 * calling the CPU specific function when the mm hasn't 165 * actually changed. 166 */ 167 static inline void 168 switch_mm(struct mm_struct *prev, struct mm_struct *next, 169 struct task_struct *tsk) 170 { 171 #ifdef CONFIG_MMU 172 unsigned int cpu = smp_processor_id(); 173 174 #ifdef CONFIG_SMP 175 /* check for possible thread migration */ 176 if (!cpumask_empty(mm_cpumask(next)) && 177 !cpumask_test_cpu(cpu, mm_cpumask(next))) 178 __flush_icache_all(); 179 #endif 180 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) { 181 check_and_switch_context(next, tsk); 182 if (cache_is_vivt()) 183 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 184 } 185 #endif 186 } 187 188 #define deactivate_mm(tsk,mm) do { } while (0) 189 #define activate_mm(prev,next) switch_mm(prev, next, NULL) 190 191 #endif 192