1 /* 2 * arch/arm/include/asm/io.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Modifications: 11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both 12 * constant addresses and variable addresses. 13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture 14 * specific IO header files. 15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. 16 * 04-Apr-1999 PJB Added check_signature. 17 * 12-Dec-1999 RMK More cleanups 18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions 19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem 20 */ 21 #ifndef __ASM_ARM_IO_H 22 #define __ASM_ARM_IO_H 23 24 #ifdef __KERNEL__ 25 26 #include <linux/types.h> 27 #include <asm/byteorder.h> 28 #include <asm/memory.h> 29 30 /* 31 * ISA I/O bus memory addresses are 1:1 with the physical address. 32 */ 33 #define isa_virt_to_bus virt_to_phys 34 #define isa_page_to_bus page_to_phys 35 #define isa_bus_to_virt phys_to_virt 36 37 /* 38 * Generic IO read/write. These perform native-endian accesses. Note 39 * that some architectures will want to re-define __raw_{read,write}w. 40 */ 41 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen); 42 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen); 43 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen); 44 45 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen); 46 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); 47 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); 48 49 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v)) 50 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)) 51 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v)) 52 53 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a)) 54 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) 55 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a)) 56 57 /* 58 * Architecture ioremap implementation. 59 */ 60 #define MT_DEVICE 0 61 #define MT_DEVICE_NONSHARED 1 62 #define MT_DEVICE_CACHED 2 63 #define MT_DEVICE_IXP2000 3 64 #define MT_DEVICE_WC 4 65 /* 66 * types 5 onwards can be found in asm/mach/map.h and are undefined 67 * for ioremap 68 */ 69 70 /* 71 * __arm_ioremap takes CPU physical address. 72 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page 73 */ 74 extern void __iomem * __arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); 75 extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int); 76 extern void __iounmap(volatile void __iomem *addr); 77 78 /* 79 * Bad read/write accesses... 80 */ 81 extern void __readwrite_bug(const char *fn); 82 83 /* 84 * Now, pick up the machine-defined IO definitions 85 */ 86 #include <mach/io.h> 87 88 /* 89 * IO port access primitives 90 * ------------------------- 91 * 92 * The ARM doesn't have special IO access instructions; all IO is memory 93 * mapped. Note that these are defined to perform little endian accesses 94 * only. Their primary purpose is to access PCI and ISA peripherals. 95 * 96 * Note that for a big endian machine, this implies that the following 97 * big endian mode connectivity is in place, as described by numerous 98 * ARM documents: 99 * 100 * PCI: D0-D7 D8-D15 D16-D23 D24-D31 101 * ARM: D24-D31 D16-D23 D8-D15 D0-D7 102 * 103 * The machine specific io.h include defines __io to translate an "IO" 104 * address to a memory address. 105 * 106 * Note that we prevent GCC re-ordering or caching values in expressions 107 * by introducing sequence points into the in*() definitions. Note that 108 * __raw_* do not guarantee this behaviour. 109 * 110 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. 111 */ 112 #ifdef __io 113 #define outb(v,p) __raw_writeb(v,__io(p)) 114 #define outw(v,p) __raw_writew((__force __u16) \ 115 cpu_to_le16(v),__io(p)) 116 #define outl(v,p) __raw_writel((__force __u32) \ 117 cpu_to_le32(v),__io(p)) 118 119 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; }) 120 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ 121 __raw_readw(__io(p))); __v; }) 122 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ 123 __raw_readl(__io(p))); __v; }) 124 125 #define outsb(p,d,l) __raw_writesb(__io(p),d,l) 126 #define outsw(p,d,l) __raw_writesw(__io(p),d,l) 127 #define outsl(p,d,l) __raw_writesl(__io(p),d,l) 128 129 #define insb(p,d,l) __raw_readsb(__io(p),d,l) 130 #define insw(p,d,l) __raw_readsw(__io(p),d,l) 131 #define insl(p,d,l) __raw_readsl(__io(p),d,l) 132 #endif 133 134 #define outb_p(val,port) outb((val),(port)) 135 #define outw_p(val,port) outw((val),(port)) 136 #define outl_p(val,port) outl((val),(port)) 137 #define inb_p(port) inb((port)) 138 #define inw_p(port) inw((port)) 139 #define inl_p(port) inl((port)) 140 141 #define outsb_p(port,from,len) outsb(port,from,len) 142 #define outsw_p(port,from,len) outsw(port,from,len) 143 #define outsl_p(port,from,len) outsl(port,from,len) 144 #define insb_p(port,to,len) insb(port,to,len) 145 #define insw_p(port,to,len) insw(port,to,len) 146 #define insl_p(port,to,len) insl(port,to,len) 147 148 /* 149 * String version of IO memory access ops: 150 */ 151 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t); 152 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t); 153 extern void _memset_io(volatile void __iomem *, int, size_t); 154 155 #define mmiowb() 156 157 /* 158 * Memory access primitives 159 * ------------------------ 160 * 161 * These perform PCI memory accesses via an ioremap region. They don't 162 * take an address as such, but a cookie. 163 * 164 * Again, this are defined to perform little endian accesses. See the 165 * IO port primitives for more information. 166 */ 167 #ifdef __mem_pci 168 #define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; }) 169 #define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \ 170 __raw_readw(__mem_pci(c))); __v; }) 171 #define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \ 172 __raw_readl(__mem_pci(c))); __v; }) 173 #define readb_relaxed(addr) readb(addr) 174 #define readw_relaxed(addr) readw(addr) 175 #define readl_relaxed(addr) readl(addr) 176 177 #define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l) 178 #define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l) 179 #define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l) 180 181 #define writeb(v,c) __raw_writeb(v,__mem_pci(c)) 182 #define writew(v,c) __raw_writew((__force __u16) \ 183 cpu_to_le16(v),__mem_pci(c)) 184 #define writel(v,c) __raw_writel((__force __u32) \ 185 cpu_to_le32(v),__mem_pci(c)) 186 187 #define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l) 188 #define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l) 189 #define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l) 190 191 #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) 192 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) 193 #define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) 194 195 #elif !defined(readb) 196 197 #define readb(c) (__readwrite_bug("readb"),0) 198 #define readw(c) (__readwrite_bug("readw"),0) 199 #define readl(c) (__readwrite_bug("readl"),0) 200 #define writeb(v,c) __readwrite_bug("writeb") 201 #define writew(v,c) __readwrite_bug("writew") 202 #define writel(v,c) __readwrite_bug("writel") 203 204 #define check_signature(io,sig,len) (0) 205 206 #endif /* __mem_pci */ 207 208 /* 209 * ioremap and friends. 210 * 211 * ioremap takes a PCI memory address, as specified in 212 * Documentation/IO-mapping.txt. 213 * 214 */ 215 #ifndef __arch_ioremap 216 #define ioremap(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE) 217 #define ioremap_nocache(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE) 218 #define ioremap_cached(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_CACHED) 219 #define ioremap_wc(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_WC) 220 #define iounmap(cookie) __iounmap(cookie) 221 #else 222 #define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) 223 #define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) 224 #define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED) 225 #define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC) 226 #define iounmap(cookie) __arch_iounmap(cookie) 227 #endif 228 229 /* 230 * io{read,write}{8,16,32} macros 231 */ 232 #ifndef ioread8 233 #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) 234 #define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __v; }) 235 #define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __v; }) 236 237 #define iowrite8(v,p) __raw_writeb(v, p) 238 #define iowrite16(v,p) __raw_writew((__force __u16)cpu_to_le16(v), p) 239 #define iowrite32(v,p) __raw_writel((__force __u32)cpu_to_le32(v), p) 240 241 #define ioread8_rep(p,d,c) __raw_readsb(p,d,c) 242 #define ioread16_rep(p,d,c) __raw_readsw(p,d,c) 243 #define ioread32_rep(p,d,c) __raw_readsl(p,d,c) 244 245 #define iowrite8_rep(p,s,c) __raw_writesb(p,s,c) 246 #define iowrite16_rep(p,s,c) __raw_writesw(p,s,c) 247 #define iowrite32_rep(p,s,c) __raw_writesl(p,s,c) 248 249 extern void __iomem *ioport_map(unsigned long port, unsigned int nr); 250 extern void ioport_unmap(void __iomem *addr); 251 #endif 252 253 struct pci_dev; 254 255 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen); 256 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); 257 258 /* 259 * can the hardware map this into one segment or not, given no other 260 * constraints. 261 */ 262 #define BIOVEC_MERGEABLE(vec1, vec2) \ 263 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) 264 265 #ifdef CONFIG_MMU 266 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 267 extern int valid_phys_addr_range(unsigned long addr, size_t size); 268 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 269 #endif 270 271 /* 272 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 273 * access 274 */ 275 #define xlate_dev_mem_ptr(p) __va(p) 276 277 /* 278 * Convert a virtual cached pointer to an uncached pointer 279 */ 280 #define xlate_dev_kmem_ptr(p) p 281 282 /* 283 * Register ISA memory and port locations for glibc iopl/inb/outb 284 * emulation. 285 */ 286 extern void register_isa_ports(unsigned int mmio, unsigned int io, 287 unsigned int io_shift); 288 289 #endif /* __KERNEL__ */ 290 #endif /* __ASM_ARM_IO_H */ 291