1 /* 2 * arch/arm/include/asm/io.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Modifications: 11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both 12 * constant addresses and variable addresses. 13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture 14 * specific IO header files. 15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. 16 * 04-Apr-1999 PJB Added check_signature. 17 * 12-Dec-1999 RMK More cleanups 18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions 19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem 20 */ 21 #ifndef __ASM_ARM_IO_H 22 #define __ASM_ARM_IO_H 23 24 #ifdef __KERNEL__ 25 26 #include <linux/string.h> 27 #include <linux/types.h> 28 #include <linux/blk_types.h> 29 #include <asm/byteorder.h> 30 #include <asm/memory.h> 31 #include <asm-generic/pci_iomap.h> 32 #include <xen/xen.h> 33 34 /* 35 * ISA I/O bus memory addresses are 1:1 with the physical address. 36 */ 37 #define isa_virt_to_bus virt_to_phys 38 #define isa_page_to_bus page_to_phys 39 #define isa_bus_to_virt phys_to_virt 40 41 /* 42 * Atomic MMIO-wide IO modify 43 */ 44 extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set); 45 extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set); 46 47 /* 48 * Generic IO read/write. These perform native-endian accesses. Note 49 * that some architectures will want to re-define __raw_{read,write}w. 50 */ 51 void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen); 52 void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen); 53 void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen); 54 55 void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen); 56 void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen); 57 void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen); 58 59 #if __LINUX_ARM_ARCH__ < 6 60 /* 61 * Half-word accesses are problematic with RiscPC due to limitations of 62 * the bus. Rather than special-case the machine, just let the compiler 63 * generate the access for CPUs prior to ARMv6. 64 */ 65 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) 66 #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) 67 #else 68 /* 69 * When running under a hypervisor, we want to avoid I/O accesses with 70 * writeback addressing modes as these incur a significant performance 71 * overhead (the address generation must be emulated in software). 72 */ 73 #define __raw_writew __raw_writew 74 static inline void __raw_writew(u16 val, volatile void __iomem *addr) 75 { 76 asm volatile("strh %1, %0" 77 : : "Q" (*(volatile u16 __force *)addr), "r" (val)); 78 } 79 80 #define __raw_readw __raw_readw 81 static inline u16 __raw_readw(const volatile void __iomem *addr) 82 { 83 u16 val; 84 asm volatile("ldrh %0, %1" 85 : "=r" (val) 86 : "Q" (*(volatile u16 __force *)addr)); 87 return val; 88 } 89 #endif 90 91 #define __raw_writeb __raw_writeb 92 static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 93 { 94 asm volatile("strb %1, %0" 95 : : "Qo" (*(volatile u8 __force *)addr), "r" (val)); 96 } 97 98 #define __raw_writel __raw_writel 99 static inline void __raw_writel(u32 val, volatile void __iomem *addr) 100 { 101 asm volatile("str %1, %0" 102 : : "Qo" (*(volatile u32 __force *)addr), "r" (val)); 103 } 104 105 #define __raw_readb __raw_readb 106 static inline u8 __raw_readb(const volatile void __iomem *addr) 107 { 108 u8 val; 109 asm volatile("ldrb %0, %1" 110 : "=r" (val) 111 : "Qo" (*(volatile u8 __force *)addr)); 112 return val; 113 } 114 115 #define __raw_readl __raw_readl 116 static inline u32 __raw_readl(const volatile void __iomem *addr) 117 { 118 u32 val; 119 asm volatile("ldr %0, %1" 120 : "=r" (val) 121 : "Qo" (*(volatile u32 __force *)addr)); 122 return val; 123 } 124 125 /* 126 * Architecture ioremap implementation. 127 */ 128 #define MT_DEVICE 0 129 #define MT_DEVICE_NONSHARED 1 130 #define MT_DEVICE_CACHED 2 131 #define MT_DEVICE_WC 3 132 /* 133 * types 4 onwards can be found in asm/mach/map.h and are undefined 134 * for ioremap 135 */ 136 137 /* 138 * __arm_ioremap takes CPU physical address. 139 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page 140 * The _caller variety takes a __builtin_return_address(0) value for 141 * /proc/vmalloc to use - and should only be used in non-inline functions. 142 */ 143 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long, 144 size_t, unsigned int, void *); 145 extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int, 146 void *); 147 148 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); 149 extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int); 150 extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached); 151 extern void __iounmap(volatile void __iomem *addr); 152 extern void __arm_iounmap(volatile void __iomem *addr); 153 154 extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, 155 unsigned int, void *); 156 extern void (*arch_iounmap)(volatile void __iomem *); 157 158 /* 159 * Bad read/write accesses... 160 */ 161 extern void __readwrite_bug(const char *fn); 162 163 /* 164 * A typesafe __io() helper 165 */ 166 static inline void __iomem *__typesafe_io(unsigned long addr) 167 { 168 return (void __iomem *)addr; 169 } 170 171 #define IOMEM(x) ((void __force __iomem *)(x)) 172 173 /* IO barriers */ 174 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 175 #include <asm/barrier.h> 176 #define __iormb() rmb() 177 #define __iowmb() wmb() 178 #else 179 #define __iormb() do { } while (0) 180 #define __iowmb() do { } while (0) 181 #endif 182 183 /* PCI fixed i/o mapping */ 184 #define PCI_IO_VIRT_BASE 0xfee00000 185 #define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE) 186 187 #if defined(CONFIG_PCI) 188 void pci_ioremap_set_mem_type(int mem_type); 189 #else 190 static inline void pci_ioremap_set_mem_type(int mem_type) {} 191 #endif 192 193 extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); 194 195 /* 196 * Now, pick up the machine-defined IO definitions 197 */ 198 #ifdef CONFIG_NEED_MACH_IO_H 199 #include <mach/io.h> 200 #elif defined(CONFIG_PCI) 201 #define IO_SPACE_LIMIT ((resource_size_t)0xfffff) 202 #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) 203 #else 204 #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) 205 #endif 206 207 /* 208 * This is the limit of PC card/PCI/ISA IO space, which is by default 209 * 64K if we have PC card, PCI or ISA support. Otherwise, default to 210 * zero to prevent ISA/PCI drivers claiming IO space (and potentially 211 * oopsing.) 212 * 213 * Only set this larger if you really need inb() et.al. to operate over 214 * a larger address space. Note that SOC_COMMON ioremaps each sockets 215 * IO space area, and so inb() et.al. must be defined to operate as per 216 * readb() et.al. on such platforms. 217 */ 218 #ifndef IO_SPACE_LIMIT 219 #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE) 220 #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff) 221 #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD) 222 #define IO_SPACE_LIMIT ((resource_size_t)0xffff) 223 #else 224 #define IO_SPACE_LIMIT ((resource_size_t)0) 225 #endif 226 #endif 227 228 /* 229 * IO port access primitives 230 * ------------------------- 231 * 232 * The ARM doesn't have special IO access instructions; all IO is memory 233 * mapped. Note that these are defined to perform little endian accesses 234 * only. Their primary purpose is to access PCI and ISA peripherals. 235 * 236 * Note that for a big endian machine, this implies that the following 237 * big endian mode connectivity is in place, as described by numerous 238 * ARM documents: 239 * 240 * PCI: D0-D7 D8-D15 D16-D23 D24-D31 241 * ARM: D24-D31 D16-D23 D8-D15 D0-D7 242 * 243 * The machine specific io.h include defines __io to translate an "IO" 244 * address to a memory address. 245 * 246 * Note that we prevent GCC re-ordering or caching values in expressions 247 * by introducing sequence points into the in*() definitions. Note that 248 * __raw_* do not guarantee this behaviour. 249 * 250 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. 251 */ 252 #ifdef __io 253 #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); }) 254 #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \ 255 cpu_to_le16(v),__io(p)); }) 256 #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \ 257 cpu_to_le32(v),__io(p)); }) 258 259 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; }) 260 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ 261 __raw_readw(__io(p))); __iormb(); __v; }) 262 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ 263 __raw_readl(__io(p))); __iormb(); __v; }) 264 265 #define outsb(p,d,l) __raw_writesb(__io(p),d,l) 266 #define outsw(p,d,l) __raw_writesw(__io(p),d,l) 267 #define outsl(p,d,l) __raw_writesl(__io(p),d,l) 268 269 #define insb(p,d,l) __raw_readsb(__io(p),d,l) 270 #define insw(p,d,l) __raw_readsw(__io(p),d,l) 271 #define insl(p,d,l) __raw_readsl(__io(p),d,l) 272 #endif 273 274 /* 275 * String version of IO memory access ops: 276 */ 277 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t); 278 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t); 279 extern void _memset_io(volatile void __iomem *, int, size_t); 280 281 #define mmiowb() 282 283 /* 284 * Memory access primitives 285 * ------------------------ 286 * 287 * These perform PCI memory accesses via an ioremap region. They don't 288 * take an address as such, but a cookie. 289 * 290 * Again, this are defined to perform little endian accesses. See the 291 * IO port primitives for more information. 292 */ 293 #ifndef readl 294 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) 295 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ 296 __raw_readw(c)); __r; }) 297 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ 298 __raw_readl(c)); __r; }) 299 300 #define writeb_relaxed(v,c) __raw_writeb(v,c) 301 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) 302 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) 303 304 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) 305 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) 306 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) 307 308 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) 309 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) 310 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) 311 312 #define readsb(p,d,l) __raw_readsb(p,d,l) 313 #define readsw(p,d,l) __raw_readsw(p,d,l) 314 #define readsl(p,d,l) __raw_readsl(p,d,l) 315 316 #define writesb(p,d,l) __raw_writesb(p,d,l) 317 #define writesw(p,d,l) __raw_writesw(p,d,l) 318 #define writesl(p,d,l) __raw_writesl(p,d,l) 319 320 #ifndef __ARMBE__ 321 static inline void memset_io(volatile void __iomem *dst, unsigned c, 322 size_t count) 323 { 324 memset((void __force *)dst, c, count); 325 } 326 #define memset_io(dst,c,count) memset_io(dst,c,count) 327 328 static inline void memcpy_fromio(void *to, const volatile void __iomem *from, 329 size_t count) 330 { 331 memcpy(to, (const void __force *)from, count); 332 } 333 #define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count) 334 335 static inline void memcpy_toio(volatile void __iomem *to, const void *from, 336 size_t count) 337 { 338 memcpy((void __force *)to, from, count); 339 } 340 #define memcpy_toio(to,from,count) memcpy_toio(to,from,count) 341 342 #else 343 #define memset_io(c,v,l) _memset_io(c,(v),(l)) 344 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l)) 345 #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l)) 346 #endif 347 348 #endif /* readl */ 349 350 /* 351 * ioremap and friends. 352 * 353 * ioremap takes a PCI memory address, as specified in 354 * Documentation/io-mapping.txt. 355 * 356 */ 357 #define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE) 358 #define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE) 359 #define ioremap_cache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED) 360 #define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC) 361 #define ioremap_wt(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE) 362 #define iounmap __arm_iounmap 363 364 /* 365 * io{read,write}{16,32}be() macros 366 */ 367 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) 368 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) 369 370 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) 371 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) 372 373 #ifndef ioport_map 374 #define ioport_map ioport_map 375 extern void __iomem *ioport_map(unsigned long port, unsigned int nr); 376 #endif 377 #ifndef ioport_unmap 378 #define ioport_unmap ioport_unmap 379 extern void ioport_unmap(void __iomem *addr); 380 #endif 381 382 struct pci_dev; 383 384 #define pci_iounmap pci_iounmap 385 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); 386 387 /* 388 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 389 * access 390 */ 391 #define xlate_dev_mem_ptr(p) __va(p) 392 393 /* 394 * Convert a virtual cached pointer to an uncached pointer 395 */ 396 #define xlate_dev_kmem_ptr(p) p 397 398 #include <asm-generic/io.h> 399 400 /* 401 * can the hardware map this into one segment or not, given no other 402 * constraints. 403 */ 404 #define BIOVEC_MERGEABLE(vec1, vec2) \ 405 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) 406 407 struct bio_vec; 408 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, 409 const struct bio_vec *vec2); 410 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ 411 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ 412 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) 413 414 #ifdef CONFIG_MMU 415 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 416 extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 417 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 418 extern int devmem_is_allowed(unsigned long pfn); 419 #endif 420 421 /* 422 * Register ISA memory and port locations for glibc iopl/inb/outb 423 * emulation. 424 */ 425 extern void register_isa_ports(unsigned int mmio, unsigned int io, 426 unsigned int io_shift); 427 428 #endif /* __KERNEL__ */ 429 #endif /* __ASM_ARM_IO_H */ 430