1 #ifndef __ASMARM_CTI_H 2 #define __ASMARM_CTI_H 3 4 #include <asm/io.h> 5 #include <asm/hardware/coresight.h> 6 7 /* The registers' definition is from section 3.2 of 8 * Embedded Cross Trigger Revision: r0p0 9 */ 10 #define CTICONTROL 0x000 11 #define CTISTATUS 0x004 12 #define CTILOCK 0x008 13 #define CTIPROTECTION 0x00C 14 #define CTIINTACK 0x010 15 #define CTIAPPSET 0x014 16 #define CTIAPPCLEAR 0x018 17 #define CTIAPPPULSE 0x01c 18 #define CTIINEN 0x020 19 #define CTIOUTEN 0x0A0 20 #define CTITRIGINSTATUS 0x130 21 #define CTITRIGOUTSTATUS 0x134 22 #define CTICHINSTATUS 0x138 23 #define CTICHOUTSTATUS 0x13c 24 #define CTIPERIPHID0 0xFE0 25 #define CTIPERIPHID1 0xFE4 26 #define CTIPERIPHID2 0xFE8 27 #define CTIPERIPHID3 0xFEC 28 #define CTIPCELLID0 0xFF0 29 #define CTIPCELLID1 0xFF4 30 #define CTIPCELLID2 0xFF8 31 #define CTIPCELLID3 0xFFC 32 33 /* The below are from section 3.6.4 of 34 * CoreSight v1.0 Architecture Specification 35 */ 36 #define LOCKACCESS 0xFB0 37 #define LOCKSTATUS 0xFB4 38 39 /** 40 * struct cti - cross trigger interface struct 41 * @base: mapped virtual address for the cti base 42 * @irq: irq number for the cti 43 * @trig_out_for_irq: triger out number which will cause 44 * the @irq happen 45 * 46 * cti struct used to operate cti registers. 47 */ 48 struct cti { 49 void __iomem *base; 50 int irq; 51 int trig_out_for_irq; 52 }; 53 54 /** 55 * cti_init - initialize the cti instance 56 * @cti: cti instance 57 * @base: mapped virtual address for the cti base 58 * @irq: irq number for the cti 59 * @trig_out: triger out number which will cause 60 * the @irq happen 61 * 62 * called by machine code to pass the board dependent 63 * @base, @irq and @trig_out to cti. 64 */ 65 static inline void cti_init(struct cti *cti, 66 void __iomem *base, int irq, int trig_out) 67 { 68 cti->base = base; 69 cti->irq = irq; 70 cti->trig_out_for_irq = trig_out; 71 } 72 73 /** 74 * cti_map_trigger - use the @chan to map @trig_in to @trig_out 75 * @cti: cti instance 76 * @trig_in: trigger in number 77 * @trig_out: trigger out number 78 * @channel: channel number 79 * 80 * This function maps one trigger in of @trig_in to one trigger 81 * out of @trig_out using the channel @chan. 82 */ 83 static inline void cti_map_trigger(struct cti *cti, 84 int trig_in, int trig_out, int chan) 85 { 86 void __iomem *base = cti->base; 87 unsigned long val; 88 89 val = __raw_readl(base + CTIINEN + trig_in * 4); 90 val |= BIT(chan); 91 __raw_writel(val, base + CTIINEN + trig_in * 4); 92 93 val = __raw_readl(base + CTIOUTEN + trig_out * 4); 94 val |= BIT(chan); 95 __raw_writel(val, base + CTIOUTEN + trig_out * 4); 96 } 97 98 /** 99 * cti_enable - enable the cti module 100 * @cti: cti instance 101 * 102 * enable the cti module 103 */ 104 static inline void cti_enable(struct cti *cti) 105 { 106 __raw_writel(0x1, cti->base + CTICONTROL); 107 } 108 109 /** 110 * cti_disable - disable the cti module 111 * @cti: cti instance 112 * 113 * enable the cti module 114 */ 115 static inline void cti_disable(struct cti *cti) 116 { 117 __raw_writel(0, cti->base + CTICONTROL); 118 } 119 120 /** 121 * cti_irq_ack - clear the cti irq 122 * @cti: cti instance 123 * 124 * clear the cti irq 125 */ 126 static inline void cti_irq_ack(struct cti *cti) 127 { 128 void __iomem *base = cti->base; 129 unsigned long val; 130 131 val = __raw_readl(base + CTIINTACK); 132 val |= BIT(cti->trig_out_for_irq); 133 __raw_writel(val, base + CTIINTACK); 134 } 135 136 /** 137 * cti_unlock - unlock cti module 138 * @cti: cti instance 139 * 140 * unlock the cti module, or else any writes to the cti 141 * module is not allowed. 142 */ 143 static inline void cti_unlock(struct cti *cti) 144 { 145 __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); 146 } 147 148 /** 149 * cti_lock - lock cti module 150 * @cti: cti instance 151 * 152 * lock the cti module, so any writes to the cti 153 * module will be not allowed. 154 */ 155 static inline void cti_lock(struct cti *cti) 156 { 157 __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); 158 } 159 #endif 160