1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASMARM_ARCH_TIMER_H 3 #define __ASMARM_ARCH_TIMER_H 4 5 #include <asm/barrier.h> 6 #include <asm/errno.h> 7 #include <asm/hwcap.h> 8 #include <linux/clocksource.h> 9 #include <linux/init.h> 10 #include <linux/types.h> 11 12 #include <clocksource/arm_arch_timer.h> 13 14 #ifdef CONFIG_ARM_ARCH_TIMER 15 /* 32bit ARM doesn't know anything about timer errata... */ 16 #define has_erratum_handler(h) (false) 17 #define erratum_handler(h) (arch_timer_##h) 18 19 int arch_timer_arch_init(void); 20 21 /* 22 * These register accessors are marked inline so the compiler can 23 * nicely work out which register we want, and chuck away the rest of 24 * the code. At least it does so with a recent GCC (4.6.3). 25 */ 26 static __always_inline 27 void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val) 28 { 29 if (access == ARCH_TIMER_PHYS_ACCESS) { 30 switch (reg) { 31 case ARCH_TIMER_REG_CTRL: 32 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val)); 33 break; 34 case ARCH_TIMER_REG_TVAL: 35 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" ((u32)val)); 36 break; 37 default: 38 BUILD_BUG(); 39 } 40 } else if (access == ARCH_TIMER_VIRT_ACCESS) { 41 switch (reg) { 42 case ARCH_TIMER_REG_CTRL: 43 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val)); 44 break; 45 case ARCH_TIMER_REG_TVAL: 46 asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" ((u32)val)); 47 break; 48 default: 49 BUILD_BUG(); 50 } 51 } else { 52 BUILD_BUG(); 53 } 54 55 isb(); 56 } 57 58 static __always_inline 59 u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) 60 { 61 u32 val = 0; 62 63 if (access == ARCH_TIMER_PHYS_ACCESS) { 64 switch (reg) { 65 case ARCH_TIMER_REG_CTRL: 66 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); 67 break; 68 default: 69 BUILD_BUG(); 70 } 71 } else if (access == ARCH_TIMER_VIRT_ACCESS) { 72 switch (reg) { 73 case ARCH_TIMER_REG_CTRL: 74 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); 75 break; 76 default: 77 BUILD_BUG(); 78 } 79 } else { 80 BUILD_BUG(); 81 } 82 83 return val; 84 } 85 86 static inline u32 arch_timer_get_cntfrq(void) 87 { 88 u32 val; 89 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); 90 return val; 91 } 92 93 static inline u64 __arch_counter_get_cntpct(void) 94 { 95 u64 cval; 96 97 isb(); 98 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); 99 return cval; 100 } 101 102 static inline u64 __arch_counter_get_cntpct_stable(void) 103 { 104 return __arch_counter_get_cntpct(); 105 } 106 107 static inline u64 __arch_counter_get_cntvct(void) 108 { 109 u64 cval; 110 111 isb(); 112 asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval)); 113 return cval; 114 } 115 116 static inline u64 __arch_counter_get_cntvct_stable(void) 117 { 118 return __arch_counter_get_cntvct(); 119 } 120 121 static inline u32 arch_timer_get_cntkctl(void) 122 { 123 u32 cntkctl; 124 asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl)); 125 return cntkctl; 126 } 127 128 static inline void arch_timer_set_cntkctl(u32 cntkctl) 129 { 130 asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); 131 isb(); 132 } 133 134 static inline void arch_timer_set_evtstrm_feature(void) 135 { 136 elf_hwcap |= HWCAP_EVTSTRM; 137 } 138 139 static inline bool arch_timer_have_evtstrm_feature(void) 140 { 141 return elf_hwcap & HWCAP_EVTSTRM; 142 } 143 #endif 144 145 #endif 146