xref: /linux/arch/arm/include/asm/arch_gicv3.h (revision dd5b2498d845f925904cb2afabb6ba11bfc317c5)
1 /*
2  * arch/arm/include/asm/arch_gicv3.h
3  *
4  * Copyright (C) 2015 ARM Ltd.
5  *
6  * This program is free software: you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 #ifndef __ASM_ARCH_GICV3_H
19 #define __ASM_ARCH_GICV3_H
20 
21 #ifndef __ASSEMBLY__
22 
23 #include <linux/io.h>
24 #include <asm/barrier.h>
25 #include <asm/cacheflush.h>
26 #include <asm/cp15.h>
27 
28 #define ICC_EOIR1			__ACCESS_CP15(c12, 0, c12, 1)
29 #define ICC_DIR				__ACCESS_CP15(c12, 0, c11, 1)
30 #define ICC_IAR1			__ACCESS_CP15(c12, 0, c12, 0)
31 #define ICC_SGI1R			__ACCESS_CP15_64(0, c12)
32 #define ICC_PMR				__ACCESS_CP15(c4, 0, c6, 0)
33 #define ICC_CTLR			__ACCESS_CP15(c12, 0, c12, 4)
34 #define ICC_SRE				__ACCESS_CP15(c12, 0, c12, 5)
35 #define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)
36 #define ICC_BPR1			__ACCESS_CP15(c12, 0, c12, 3)
37 #define ICC_RPR				__ACCESS_CP15(c12, 0, c11, 3)
38 
39 #define __ICC_AP0Rx(x)			__ACCESS_CP15(c12, 0, c8, 4 | x)
40 #define ICC_AP0R0			__ICC_AP0Rx(0)
41 #define ICC_AP0R1			__ICC_AP0Rx(1)
42 #define ICC_AP0R2			__ICC_AP0Rx(2)
43 #define ICC_AP0R3			__ICC_AP0Rx(3)
44 
45 #define __ICC_AP1Rx(x)			__ACCESS_CP15(c12, 0, c9, x)
46 #define ICC_AP1R0			__ICC_AP1Rx(0)
47 #define ICC_AP1R1			__ICC_AP1Rx(1)
48 #define ICC_AP1R2			__ICC_AP1Rx(2)
49 #define ICC_AP1R3			__ICC_AP1Rx(3)
50 
51 #define ICC_HSRE			__ACCESS_CP15(c12, 4, c9, 5)
52 
53 #define ICH_VSEIR			__ACCESS_CP15(c12, 4, c9, 4)
54 #define ICH_HCR				__ACCESS_CP15(c12, 4, c11, 0)
55 #define ICH_VTR				__ACCESS_CP15(c12, 4, c11, 1)
56 #define ICH_MISR			__ACCESS_CP15(c12, 4, c11, 2)
57 #define ICH_EISR			__ACCESS_CP15(c12, 4, c11, 3)
58 #define ICH_ELRSR			__ACCESS_CP15(c12, 4, c11, 5)
59 #define ICH_VMCR			__ACCESS_CP15(c12, 4, c11, 7)
60 
61 #define __LR0(x)			__ACCESS_CP15(c12, 4, c12, x)
62 #define __LR8(x)			__ACCESS_CP15(c12, 4, c13, x)
63 
64 #define ICH_LR0				__LR0(0)
65 #define ICH_LR1				__LR0(1)
66 #define ICH_LR2				__LR0(2)
67 #define ICH_LR3				__LR0(3)
68 #define ICH_LR4				__LR0(4)
69 #define ICH_LR5				__LR0(5)
70 #define ICH_LR6				__LR0(6)
71 #define ICH_LR7				__LR0(7)
72 #define ICH_LR8				__LR8(0)
73 #define ICH_LR9				__LR8(1)
74 #define ICH_LR10			__LR8(2)
75 #define ICH_LR11			__LR8(3)
76 #define ICH_LR12			__LR8(4)
77 #define ICH_LR13			__LR8(5)
78 #define ICH_LR14			__LR8(6)
79 #define ICH_LR15			__LR8(7)
80 
81 /* LR top half */
82 #define __LRC0(x)			__ACCESS_CP15(c12, 4, c14, x)
83 #define __LRC8(x)			__ACCESS_CP15(c12, 4, c15, x)
84 
85 #define ICH_LRC0			__LRC0(0)
86 #define ICH_LRC1			__LRC0(1)
87 #define ICH_LRC2			__LRC0(2)
88 #define ICH_LRC3			__LRC0(3)
89 #define ICH_LRC4			__LRC0(4)
90 #define ICH_LRC5			__LRC0(5)
91 #define ICH_LRC6			__LRC0(6)
92 #define ICH_LRC7			__LRC0(7)
93 #define ICH_LRC8			__LRC8(0)
94 #define ICH_LRC9			__LRC8(1)
95 #define ICH_LRC10			__LRC8(2)
96 #define ICH_LRC11			__LRC8(3)
97 #define ICH_LRC12			__LRC8(4)
98 #define ICH_LRC13			__LRC8(5)
99 #define ICH_LRC14			__LRC8(6)
100 #define ICH_LRC15			__LRC8(7)
101 
102 #define __ICH_AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)
103 #define ICH_AP0R0			__ICH_AP0Rx(0)
104 #define ICH_AP0R1			__ICH_AP0Rx(1)
105 #define ICH_AP0R2			__ICH_AP0Rx(2)
106 #define ICH_AP0R3			__ICH_AP0Rx(3)
107 
108 #define __ICH_AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)
109 #define ICH_AP1R0			__ICH_AP1Rx(0)
110 #define ICH_AP1R1			__ICH_AP1Rx(1)
111 #define ICH_AP1R2			__ICH_AP1Rx(2)
112 #define ICH_AP1R3			__ICH_AP1Rx(3)
113 
114 /* A32-to-A64 mappings used by VGIC save/restore */
115 
116 #define CPUIF_MAP(a32, a64)			\
117 static inline void write_ ## a64(u32 val)	\
118 {						\
119 	write_sysreg(val, a32);			\
120 }						\
121 static inline u32 read_ ## a64(void)		\
122 {						\
123 	return read_sysreg(a32); 		\
124 }						\
125 
126 #define CPUIF_MAP_LO_HI(a32lo, a32hi, a64)	\
127 static inline void write_ ## a64(u64 val)	\
128 {						\
129 	write_sysreg(lower_32_bits(val), a32lo);\
130 	write_sysreg(upper_32_bits(val), a32hi);\
131 }						\
132 static inline u64 read_ ## a64(void)		\
133 {						\
134 	u64 val = read_sysreg(a32lo);		\
135 						\
136 	val |=	(u64)read_sysreg(a32hi) << 32;	\
137 						\
138 	return val; 				\
139 }
140 
141 CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
142 CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
143 CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
144 CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
145 CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
146 CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
147 CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)
148 CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
149 CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
150 
151 CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
152 CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
153 CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
154 CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
155 CPUIF_MAP(ICH_ELRSR, ICH_ELRSR_EL2)
156 CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
157 CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
158 CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
159 CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
160 CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
161 CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
162 CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
163 CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
164 CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
165 CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
166 CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
167 
168 CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
169 CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
170 CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
171 CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
172 CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
173 CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
174 CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
175 CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
176 CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
177 CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
178 CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
179 CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
180 CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
181 CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
182 CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
183 CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
184 
185 #define read_gicreg(r)                 read_##r()
186 #define write_gicreg(v, r)             write_##r(v)
187 
188 /* Low-level accessors */
189 
190 static inline void gic_write_eoir(u32 irq)
191 {
192 	write_sysreg(irq, ICC_EOIR1);
193 	isb();
194 }
195 
196 static inline void gic_write_dir(u32 val)
197 {
198 	write_sysreg(val, ICC_DIR);
199 	isb();
200 }
201 
202 static inline u32 gic_read_iar(void)
203 {
204 	u32 irqstat = read_sysreg(ICC_IAR1);
205 
206 	dsb(sy);
207 
208 	return irqstat;
209 }
210 
211 static inline void gic_write_ctlr(u32 val)
212 {
213 	write_sysreg(val, ICC_CTLR);
214 	isb();
215 }
216 
217 static inline u32 gic_read_ctlr(void)
218 {
219 	return read_sysreg(ICC_CTLR);
220 }
221 
222 static inline void gic_write_grpen1(u32 val)
223 {
224 	write_sysreg(val, ICC_IGRPEN1);
225 	isb();
226 }
227 
228 static inline void gic_write_sgi1r(u64 val)
229 {
230 	write_sysreg(val, ICC_SGI1R);
231 }
232 
233 static inline u32 gic_read_sre(void)
234 {
235 	return read_sysreg(ICC_SRE);
236 }
237 
238 static inline void gic_write_sre(u32 val)
239 {
240 	write_sysreg(val, ICC_SRE);
241 	isb();
242 }
243 
244 static inline void gic_write_bpr1(u32 val)
245 {
246 	write_sysreg(val, ICC_BPR1);
247 }
248 
249 static inline u32 gic_read_pmr(void)
250 {
251 	return read_sysreg(ICC_PMR);
252 }
253 
254 static inline void gic_write_pmr(u32 val)
255 {
256 	write_sysreg(val, ICC_PMR);
257 }
258 
259 static inline u32 gic_read_rpr(void)
260 {
261 	return read_sysreg(ICC_RPR);
262 }
263 
264 /*
265  * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
266  * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
267  * make much sense.
268  * Moreover, 64bit I/O emulation is extremely difficult to implement on
269  * AArch32, since the syndrome register doesn't provide any information for
270  * them.
271  * Consequently, the following IO helpers use 32bit accesses.
272  */
273 static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
274 {
275 	writel_relaxed((u32)val, addr);
276 	writel_relaxed((u32)(val >> 32), addr + 4);
277 }
278 
279 static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
280 {
281 	u64 val;
282 
283 	val = readl_relaxed(addr);
284 	val |= (u64)readl_relaxed(addr + 4) << 32;
285 	return val;
286 }
287 
288 #define gic_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))
289 
290 /*
291  *  GICD_IROUTERn, contain the affinity values associated to each interrupt.
292  *  The upper-word (aff3) will always be 0, so there is no need for a lock.
293  */
294 #define gic_write_irouter(v, c)		__gic_writeq_nonatomic(v, c)
295 
296 /*
297  * GICR_TYPER is an ID register and doesn't need atomicity.
298  */
299 #define gic_read_typer(c)		__gic_readq_nonatomic(c)
300 
301 /*
302  * GITS_BASER - hi and lo bits may be accessed independently.
303  */
304 #define gits_read_baser(c)		__gic_readq_nonatomic(c)
305 #define gits_write_baser(v, c)		__gic_writeq_nonatomic(v, c)
306 
307 /*
308  * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
309  * won't be being used during any updates and can be changed non-atomically
310  */
311 #define gicr_read_propbaser(c)		__gic_readq_nonatomic(c)
312 #define gicr_write_propbaser(v, c)	__gic_writeq_nonatomic(v, c)
313 #define gicr_read_pendbaser(c)		__gic_readq_nonatomic(c)
314 #define gicr_write_pendbaser(v, c)	__gic_writeq_nonatomic(v, c)
315 
316 /*
317  * GICR_xLPIR - only the lower bits are significant
318  */
319 #define gic_read_lpir(c)		readl_relaxed(c)
320 #define gic_write_lpir(v, c)		writel_relaxed(lower_32_bits(v), c)
321 
322 /*
323  * GITS_TYPER is an ID register and doesn't need atomicity.
324  */
325 #define gits_read_typer(c)		__gic_readq_nonatomic(c)
326 
327 /*
328  * GITS_CBASER - hi and lo bits may be accessed independently.
329  */
330 #define gits_read_cbaser(c)		__gic_readq_nonatomic(c)
331 #define gits_write_cbaser(v, c)		__gic_writeq_nonatomic(v, c)
332 
333 /*
334  * GITS_CWRITER - hi and lo bits may be accessed independently.
335  */
336 #define gits_write_cwriter(v, c)	__gic_writeq_nonatomic(v, c)
337 
338 /*
339  * GITS_VPROPBASER - hi and lo bits may be accessed independently.
340  */
341 #define gits_write_vpropbaser(v, c)	__gic_writeq_nonatomic(v, c)
342 
343 /*
344  * GITS_VPENDBASER - the Valid bit must be cleared before changing
345  * anything else.
346  */
347 static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)
348 {
349 	u32 tmp;
350 
351 	tmp = readl_relaxed(addr + 4);
352 	if (tmp & (GICR_VPENDBASER_Valid >> 32)) {
353 		tmp &= ~(GICR_VPENDBASER_Valid >> 32);
354 		writel_relaxed(tmp, addr + 4);
355 	}
356 
357 	/*
358 	 * Use the fact that __gic_writeq_nonatomic writes the second
359 	 * half of the 64bit quantity after the first.
360 	 */
361 	__gic_writeq_nonatomic(val, addr);
362 }
363 
364 #define gits_read_vpendbaser(c)		__gic_readq_nonatomic(c)
365 
366 static inline bool gic_prio_masking_enabled(void)
367 {
368 	return false;
369 }
370 
371 static inline void gic_pmr_mask_irqs(void)
372 {
373 	/* Should not get called. */
374 	WARN_ON_ONCE(true);
375 }
376 
377 static inline void gic_arch_enable_irqs(void)
378 {
379 	/* Should not get called. */
380 	WARN_ON_ONCE(true);
381 }
382 
383 #endif /* !__ASSEMBLY__ */
384 #endif /* !__ASM_ARCH_GICV3_H */
385