1*7c607944SMylène Josserand/* SPDX-License-Identifier: GPL-2.0 */ 2*7c607944SMylène Josserand/* 3*7c607944SMylène Josserand * Copyright (C) 2014 Renesas Electronics Corporation 4*7c607944SMylène Josserand * 5*7c607944SMylène Josserand * Initialization of CNTVOFF register from secure mode 6*7c607944SMylène Josserand * 7*7c607944SMylène Josserand */ 8*7c607944SMylène Josserand 9*7c607944SMylène Josserand#include <linux/linkage.h> 10*7c607944SMylène Josserand#include <asm/assembler.h> 11*7c607944SMylène Josserand 12*7c607944SMylène JosserandENTRY(secure_cntvoff_init) 13*7c607944SMylène Josserand .arch armv7-a 14*7c607944SMylène Josserand /* 15*7c607944SMylène Josserand * CNTVOFF has to be initialized either from non-secure Hypervisor 16*7c607944SMylène Josserand * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled 17*7c607944SMylène Josserand * then it should be handled by the secure code. The CPU must implement 18*7c607944SMylène Josserand * the virtualization extensions. 19*7c607944SMylène Josserand */ 20*7c607944SMylène Josserand cps #MON_MODE 21*7c607944SMylène Josserand mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */ 22*7c607944SMylène Josserand orr r0, r1, #1 23*7c607944SMylène Josserand mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ 24*7c607944SMylène Josserand isb 25*7c607944SMylène Josserand mov r0, #0 26*7c607944SMylène Josserand mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */ 27*7c607944SMylène Josserand isb 28*7c607944SMylène Josserand mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */ 29*7c607944SMylène Josserand isb 30*7c607944SMylène Josserand cps #SVC_MODE 31*7c607944SMylène Josserand ret lr 32*7c607944SMylène JosserandENDPROC(secure_cntvoff_init) 33