xref: /linux/arch/arm/boot/dts/vt8500/wm8850.dtsi (revision f9bff0e31881d03badf191d3b0005839391f5f2b) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 */
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	compatible = "wm,wm8850";
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-a9";
20			reg = <0x0>;
21		};
22	};
23
24	memory {
25		device_type = "memory";
26		reg = <0x0 0x0>;
27	};
28
29	aliases {
30		serial0 = &uart0;
31		serial1 = &uart1;
32		serial2 = &uart2;
33		serial3 = &uart3;
34	};
35
36	soc {
37		#address-cells = <1>;
38		#size-cells = <1>;
39		compatible = "simple-bus";
40		ranges;
41		interrupt-parent = <&intc0>;
42
43		intc0: interrupt-controller@d8140000 {
44			compatible = "via,vt8500-intc";
45			interrupt-controller;
46			reg = <0xd8140000 0x10000>;
47			#interrupt-cells = <1>;
48		};
49
50		/* Secondary IC cascaded to intc0 */
51		intc1: interrupt-controller@d8150000 {
52			compatible = "via,vt8500-intc";
53			interrupt-controller;
54			#interrupt-cells = <1>;
55			reg = <0xD8150000 0x10000>;
56			interrupts = <56 57 58 59 60 61 62 63>;
57		};
58
59		pinctrl: pinctrl@d8110000 {
60			compatible = "wm,wm8850-pinctrl";
61			reg = <0xd8110000 0x10000>;
62			interrupt-controller;
63			#interrupt-cells = <2>;
64			gpio-controller;
65			#gpio-cells = <2>;
66		};
67
68		pmc@d8130000 {
69			compatible = "via,vt8500-pmc";
70			reg = <0xd8130000 0x1000>;
71
72			clocks {
73				#address-cells = <1>;
74				#size-cells = <0>;
75
76				ref25: ref25M {
77					#clock-cells = <0>;
78					compatible = "fixed-clock";
79					clock-frequency = <25000000>;
80				};
81
82				ref24: ref24M {
83					#clock-cells = <0>;
84					compatible = "fixed-clock";
85					clock-frequency = <24000000>;
86				};
87
88				plla: plla {
89					#clock-cells = <0>;
90					compatible = "wm,wm8850-pll-clock";
91					clocks = <&ref24>;
92					reg = <0x200>;
93				};
94
95				pllb: pllb {
96					#clock-cells = <0>;
97					compatible = "wm,wm8850-pll-clock";
98					clocks = <&ref24>;
99					reg = <0x204>;
100				};
101
102				pllc: pllc {
103					#clock-cells = <0>;
104					compatible = "wm,wm8850-pll-clock";
105					clocks = <&ref24>;
106					reg = <0x208>;
107				};
108
109				plld: plld {
110					#clock-cells = <0>;
111					compatible = "wm,wm8850-pll-clock";
112					clocks = <&ref24>;
113					reg = <0x20c>;
114				};
115
116				plle: plle {
117					#clock-cells = <0>;
118					compatible = "wm,wm8850-pll-clock";
119					clocks = <&ref24>;
120					reg = <0x210>;
121				};
122
123				pllf: pllf {
124					#clock-cells = <0>;
125					compatible = "wm,wm8850-pll-clock";
126					clocks = <&ref24>;
127					reg = <0x214>;
128				};
129
130				pllg: pllg {
131					#clock-cells = <0>;
132					compatible = "wm,wm8850-pll-clock";
133					clocks = <&ref24>;
134					reg = <0x218>;
135				};
136
137				clkarm: arm {
138					#clock-cells = <0>;
139					compatible = "via,vt8500-device-clock";
140					clocks = <&plla>;
141					divisor-reg = <0x300>;
142				};
143
144				clkahb: ahb {
145					#clock-cells = <0>;
146					compatible = "via,vt8500-device-clock";
147					clocks = <&pllb>;
148					divisor-reg = <0x304>;
149				};
150
151				clkapb: apb {
152					#clock-cells = <0>;
153					compatible = "via,vt8500-device-clock";
154					clocks = <&pllb>;
155					divisor-reg = <0x320>;
156				};
157
158				clkddr: ddr {
159					#clock-cells = <0>;
160					compatible = "via,vt8500-device-clock";
161					clocks = <&plld>;
162					divisor-reg = <0x310>;
163				};
164
165				clkuart0: uart0 {
166					#clock-cells = <0>;
167					compatible = "via,vt8500-device-clock";
168					clocks = <&ref24>;
169					enable-reg = <0x254>;
170					enable-bit = <24>;
171				};
172
173				clkuart1: uart1 {
174					#clock-cells = <0>;
175					compatible = "via,vt8500-device-clock";
176					clocks = <&ref24>;
177					enable-reg = <0x254>;
178					enable-bit = <25>;
179				};
180
181                                clkuart2: uart2 {
182                                        #clock-cells = <0>;
183                                        compatible = "via,vt8500-device-clock";
184                                        clocks = <&ref24>;
185                                        enable-reg = <0x254>;
186                                        enable-bit = <26>;
187                                };
188
189                                clkuart3: uart3 {
190                                        #clock-cells = <0>;
191                                        compatible = "via,vt8500-device-clock";
192                                        clocks = <&ref24>;
193                                        enable-reg = <0x254>;
194                                        enable-bit = <27>;
195                                };
196
197				clkpwm: pwm {
198					#clock-cells = <0>;
199					compatible = "via,vt8500-device-clock";
200					clocks = <&pllb>;
201					divisor-reg = <0x350>;
202					enable-reg = <0x250>;
203					enable-bit = <17>;
204				};
205
206				clksdhc: sdhc {
207					#clock-cells = <0>;
208					compatible = "via,vt8500-device-clock";
209					clocks = <&pllb>;
210					divisor-reg = <0x330>;
211					divisor-mask = <0x3f>;
212					enable-reg = <0x250>;
213					enable-bit = <0>;
214				};
215			};
216		};
217
218		fb: fb@d8051700 {
219			compatible = "wm,wm8505-fb";
220			reg = <0xd8051700 0x200>;
221		};
222
223		ge_rops@d8050400 {
224			compatible = "wm,prizm-ge-rops";
225			reg = <0xd8050400 0x100>;
226		};
227
228		pwm: pwm@d8220000 {
229			#pwm-cells = <3>;
230			compatible = "via,vt8500-pwm";
231			reg = <0xd8220000 0x100>;
232			clocks = <&clkpwm>;
233		};
234
235		timer@d8130100 {
236			compatible = "via,vt8500-timer";
237			reg = <0xd8130100 0x28>;
238			interrupts = <36>;
239		};
240
241		ehci@d8007900 {
242			compatible = "via,vt8500-ehci";
243			reg = <0xd8007900 0x200>;
244			interrupts = <26>;
245		};
246
247		uhci@d8007b00 {
248			compatible = "platform-uhci";
249			reg = <0xd8007b00 0x200>;
250			interrupts = <26>;
251		};
252
253		uhci@d8008d00 {
254			compatible = "platform-uhci";
255			reg = <0xd8008d00 0x200>;
256			interrupts = <26>;
257		};
258
259		uart0: serial@d8200000 {
260			compatible = "via,vt8500-uart";
261			reg = <0xd8200000 0x1040>;
262			interrupts = <32>;
263			clocks = <&clkuart0>;
264			status = "disabled";
265		};
266
267		uart1: serial@d82b0000 {
268			compatible = "via,vt8500-uart";
269			reg = <0xd82b0000 0x1040>;
270			interrupts = <33>;
271			clocks = <&clkuart1>;
272			status = "disabled";
273		};
274
275                uart2: serial@d8210000 {
276                        compatible = "via,vt8500-uart";
277                        reg = <0xd8210000 0x1040>;
278                        interrupts = <47>;
279                        clocks = <&clkuart2>;
280			status = "disabled";
281                };
282
283                uart3: serial@d82c0000 {
284                        compatible = "via,vt8500-uart";
285                        reg = <0xd82c0000 0x1040>;
286                        interrupts = <50>;
287                        clocks = <&clkuart3>;
288			status = "disabled";
289                };
290
291		rtc@d8100000 {
292			compatible = "via,vt8500-rtc";
293			reg = <0xd8100000 0x10000>;
294			interrupts = <48>;
295		};
296
297		sdhc@d800a000 {
298			compatible = "wm,wm8505-sdhc";
299			reg = <0xd800a000 0x1000>;
300			interrupts = <20 21>;
301			clocks = <&clksdhc>;
302			bus-width = <4>;
303			sdon-inverted;
304		};
305
306		ethernet@d8004000 {
307			compatible = "via,vt8500-rhine";
308			reg = <0xd8004000 0x100>;
309			interrupts = <10>;
310                };
311	};
312};
313