xref: /linux/arch/arm/boot/dts/vt8500/wm8850.dtsi (revision 18f0817d2e9af479a40a1be4d83a849894d6b3f8) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 */
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	compatible = "wm,wm8850";
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-a9";
20			reg = <0x0>;
21		};
22	};
23
24	memory {
25		device_type = "memory";
26		reg = <0x0 0x0>;
27	};
28
29	aliases {
30		serial0 = &uart0;
31		serial1 = &uart1;
32		serial2 = &uart2;
33		serial3 = &uart3;
34	};
35
36	soc {
37		#address-cells = <1>;
38		#size-cells = <1>;
39		compatible = "simple-bus";
40		ranges;
41		interrupt-parent = <&intc0>;
42
43		intc0: interrupt-controller@d8140000 {
44			compatible = "via,vt8500-intc";
45			interrupt-controller;
46			reg = <0xd8140000 0x10000>;
47			#interrupt-cells = <1>;
48		};
49
50		/* Secondary IC cascaded to intc0 */
51		intc1: interrupt-controller@d8150000 {
52			compatible = "via,vt8500-intc";
53			interrupt-controller;
54			#interrupt-cells = <1>;
55			reg = <0xD8150000 0x10000>;
56			interrupts = <56 57 58 59 60 61 62 63>;
57		};
58
59		pinctrl: pinctrl@d8110000 {
60			compatible = "wm,wm8850-pinctrl";
61			reg = <0xd8110000 0x10000>;
62			interrupt-controller;
63			#interrupt-cells = <2>;
64			gpio-controller;
65			#gpio-cells = <2>;
66		};
67
68		chipid@d8120000 {
69			compatible = "via,vt8500-scc-id";
70			reg = <0xd8120000 0x4>;
71		};
72
73		pmc@d8130000 {
74			compatible = "via,vt8500-pmc";
75			reg = <0xd8130000 0x1000>;
76
77			clocks {
78				#address-cells = <1>;
79				#size-cells = <0>;
80
81				ref25: ref25M {
82					#clock-cells = <0>;
83					compatible = "fixed-clock";
84					clock-frequency = <25000000>;
85				};
86
87				ref24: ref24M {
88					#clock-cells = <0>;
89					compatible = "fixed-clock";
90					clock-frequency = <24000000>;
91				};
92
93				plla: plla {
94					#clock-cells = <0>;
95					compatible = "wm,wm8850-pll-clock";
96					clocks = <&ref24>;
97					reg = <0x200>;
98				};
99
100				pllb: pllb {
101					#clock-cells = <0>;
102					compatible = "wm,wm8850-pll-clock";
103					clocks = <&ref24>;
104					reg = <0x204>;
105				};
106
107				pllc: pllc {
108					#clock-cells = <0>;
109					compatible = "wm,wm8850-pll-clock";
110					clocks = <&ref24>;
111					reg = <0x208>;
112				};
113
114				plld: plld {
115					#clock-cells = <0>;
116					compatible = "wm,wm8850-pll-clock";
117					clocks = <&ref24>;
118					reg = <0x20c>;
119				};
120
121				plle: plle {
122					#clock-cells = <0>;
123					compatible = "wm,wm8850-pll-clock";
124					clocks = <&ref24>;
125					reg = <0x210>;
126				};
127
128				pllf: pllf {
129					#clock-cells = <0>;
130					compatible = "wm,wm8850-pll-clock";
131					clocks = <&ref24>;
132					reg = <0x214>;
133				};
134
135				pllg: pllg {
136					#clock-cells = <0>;
137					compatible = "wm,wm8850-pll-clock";
138					clocks = <&ref24>;
139					reg = <0x218>;
140				};
141
142				clkarm: arm {
143					#clock-cells = <0>;
144					compatible = "via,vt8500-device-clock";
145					clocks = <&plla>;
146					divisor-reg = <0x300>;
147				};
148
149				clkahb: ahb {
150					#clock-cells = <0>;
151					compatible = "via,vt8500-device-clock";
152					clocks = <&pllb>;
153					divisor-reg = <0x304>;
154				};
155
156				clkapb: apb {
157					#clock-cells = <0>;
158					compatible = "via,vt8500-device-clock";
159					clocks = <&pllb>;
160					divisor-reg = <0x320>;
161				};
162
163				clkddr: ddr {
164					#clock-cells = <0>;
165					compatible = "via,vt8500-device-clock";
166					clocks = <&plld>;
167					divisor-reg = <0x310>;
168				};
169
170				clkuart0: uart0 {
171					#clock-cells = <0>;
172					compatible = "via,vt8500-device-clock";
173					clocks = <&ref24>;
174					enable-reg = <0x254>;
175					enable-bit = <24>;
176				};
177
178				clkuart1: uart1 {
179					#clock-cells = <0>;
180					compatible = "via,vt8500-device-clock";
181					clocks = <&ref24>;
182					enable-reg = <0x254>;
183					enable-bit = <25>;
184				};
185
186                                clkuart2: uart2 {
187                                        #clock-cells = <0>;
188                                        compatible = "via,vt8500-device-clock";
189                                        clocks = <&ref24>;
190                                        enable-reg = <0x254>;
191                                        enable-bit = <26>;
192                                };
193
194                                clkuart3: uart3 {
195                                        #clock-cells = <0>;
196                                        compatible = "via,vt8500-device-clock";
197                                        clocks = <&ref24>;
198                                        enable-reg = <0x254>;
199                                        enable-bit = <27>;
200                                };
201
202				clkpwm: pwm {
203					#clock-cells = <0>;
204					compatible = "via,vt8500-device-clock";
205					clocks = <&pllb>;
206					divisor-reg = <0x350>;
207					enable-reg = <0x250>;
208					enable-bit = <17>;
209				};
210
211				clksdhc: sdhc {
212					#clock-cells = <0>;
213					compatible = "via,vt8500-device-clock";
214					clocks = <&pllb>;
215					divisor-reg = <0x330>;
216					divisor-mask = <0x3f>;
217					enable-reg = <0x250>;
218					enable-bit = <0>;
219				};
220			};
221		};
222
223		fb: fb@d8051700 {
224			compatible = "wm,wm8505-fb";
225			reg = <0xd8051700 0x200>;
226		};
227
228		ge_rops@d8050400 {
229			compatible = "wm,prizm-ge-rops";
230			reg = <0xd8050400 0x100>;
231		};
232
233		pwm: pwm@d8220000 {
234			#pwm-cells = <3>;
235			compatible = "via,vt8500-pwm";
236			reg = <0xd8220000 0x100>;
237			clocks = <&clkpwm>;
238		};
239
240		timer@d8130100 {
241			compatible = "via,vt8500-timer";
242			reg = <0xd8130100 0x28>;
243			interrupts = <36>, <37>, <38>, <39>;
244		};
245
246		usb@d8007900 {
247			compatible = "via,vt8500-ehci";
248			reg = <0xd8007900 0x200>;
249			interrupts = <26>;
250		};
251
252		usb@d8007b00 {
253			compatible = "platform-uhci";
254			reg = <0xd8007b00 0x200>;
255			interrupts = <26>;
256		};
257
258		usb@d8008d00 {
259			compatible = "platform-uhci";
260			reg = <0xd8008d00 0x200>;
261			interrupts = <26>;
262		};
263
264		uart0: serial@d8200000 {
265			compatible = "via,vt8500-uart";
266			reg = <0xd8200000 0x1040>;
267			interrupts = <32>;
268			clocks = <&clkuart0>;
269			status = "disabled";
270		};
271
272		uart1: serial@d82b0000 {
273			compatible = "via,vt8500-uart";
274			reg = <0xd82b0000 0x1040>;
275			interrupts = <33>;
276			clocks = <&clkuart1>;
277			status = "disabled";
278		};
279
280                uart2: serial@d8210000 {
281                        compatible = "via,vt8500-uart";
282                        reg = <0xd8210000 0x1040>;
283                        interrupts = <47>;
284                        clocks = <&clkuart2>;
285			status = "disabled";
286                };
287
288                uart3: serial@d82c0000 {
289                        compatible = "via,vt8500-uart";
290                        reg = <0xd82c0000 0x1040>;
291                        interrupts = <50>;
292                        clocks = <&clkuart3>;
293			status = "disabled";
294                };
295
296		rtc@d8100000 {
297			compatible = "via,vt8500-rtc";
298			reg = <0xd8100000 0x10000>;
299			interrupts = <48>;
300		};
301
302		sdhc@d800a000 {
303			compatible = "wm,wm8505-sdhc";
304			reg = <0xd800a000 0x1000>;
305			interrupts = <20 21>;
306			clocks = <&clksdhc>;
307			bus-width = <4>;
308			sdon-inverted;
309		};
310
311		ethernet@d8004000 {
312			compatible = "via,vt8500-rhine";
313			reg = <0xd8004000 0x100>;
314			interrupts = <10>;
315                };
316	};
317};
318