1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC 4 * 5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 6 */ 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 compatible = "wm,wm8750"; 12 13 cpus { 14 #address-cells = <0>; 15 #size-cells = <0>; 16 17 cpu { 18 device_type = "cpu"; 19 compatible = "arm,arm1176jzf"; 20 }; 21 }; 22 23 memory { 24 device_type = "memory"; 25 reg = <0x0 0x0>; 26 }; 27 28 aliases { 29 serial0 = &uart0; 30 serial1 = &uart1; 31 serial2 = &uart2; 32 serial3 = &uart3; 33 serial4 = &uart4; 34 serial5 = &uart5; 35 i2c0 = &i2c_0; 36 i2c1 = &i2c_1; 37 }; 38 39 soc { 40 #address-cells = <1>; 41 #size-cells = <1>; 42 compatible = "simple-bus"; 43 ranges; 44 interrupt-parent = <&intc0>; 45 46 intc0: interrupt-controller@d8140000 { 47 compatible = "via,vt8500-intc"; 48 interrupt-controller; 49 reg = <0xd8140000 0x10000>; 50 #interrupt-cells = <1>; 51 }; 52 53 /* Secondary IC cascaded to intc0 */ 54 intc1: interrupt-controller@d8150000 { 55 compatible = "via,vt8500-intc"; 56 interrupt-controller; 57 #interrupt-cells = <1>; 58 reg = <0xD8150000 0x10000>; 59 interrupts = <56 57 58 59 60 61 62 63>; 60 }; 61 62 pinctrl: pinctrl@d8110000 { 63 compatible = "wm,wm8750-pinctrl"; 64 reg = <0xd8110000 0x10000>; 65 interrupt-controller; 66 #interrupt-cells = <2>; 67 gpio-controller; 68 #gpio-cells = <2>; 69 }; 70 71 chipid@d8120000 { 72 compatible = "via,vt8500-scc-id"; 73 reg = <0xd8120000 0x4>; 74 }; 75 76 pmc@d8130000 { 77 compatible = "via,vt8500-pmc"; 78 reg = <0xd8130000 0x1000>; 79 80 clocks { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 ref24: ref24M { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <24000000>; 88 }; 89 90 ref25: ref25M { 91 #clock-cells = <0>; 92 compatible = "fixed-clock"; 93 clock-frequency = <25000000>; 94 }; 95 96 plla: plla { 97 #clock-cells = <0>; 98 compatible = "wm,wm8750-pll-clock"; 99 clocks = <&ref25>; 100 reg = <0x200>; 101 }; 102 103 pllb: pllb { 104 #clock-cells = <0>; 105 compatible = "wm,wm8750-pll-clock"; 106 clocks = <&ref25>; 107 reg = <0x204>; 108 }; 109 110 pllc: pllc { 111 #clock-cells = <0>; 112 compatible = "wm,wm8750-pll-clock"; 113 clocks = <&ref25>; 114 reg = <0x208>; 115 }; 116 117 plld: plld { 118 #clock-cells = <0>; 119 compatible = "wm,wm8750-pll-clock"; 120 clocks = <&ref25>; 121 reg = <0x20C>; 122 }; 123 124 plle: plle { 125 #clock-cells = <0>; 126 compatible = "wm,wm8750-pll-clock"; 127 clocks = <&ref25>; 128 reg = <0x210>; 129 }; 130 131 clkarm: arm { 132 #clock-cells = <0>; 133 compatible = "via,vt8500-device-clock"; 134 clocks = <&plla>; 135 divisor-reg = <0x300>; 136 }; 137 138 clkahb: ahb { 139 #clock-cells = <0>; 140 compatible = "via,vt8500-device-clock"; 141 clocks = <&pllb>; 142 divisor-reg = <0x304>; 143 }; 144 145 clkapb: apb { 146 #clock-cells = <0>; 147 compatible = "via,vt8500-device-clock"; 148 clocks = <&pllb>; 149 divisor-reg = <0x320>; 150 }; 151 152 clkddr: ddr { 153 #clock-cells = <0>; 154 compatible = "via,vt8500-device-clock"; 155 clocks = <&plld>; 156 divisor-reg = <0x310>; 157 }; 158 159 clkuart0: uart0 { 160 #clock-cells = <0>; 161 compatible = "via,vt8500-device-clock"; 162 clocks = <&ref24>; 163 enable-reg = <0x254>; 164 enable-bit = <24>; 165 }; 166 167 clkuart1: uart1 { 168 #clock-cells = <0>; 169 compatible = "via,vt8500-device-clock"; 170 clocks = <&ref24>; 171 enable-reg = <0x254>; 172 enable-bit = <25>; 173 }; 174 175 clkuart2: uart2 { 176 #clock-cells = <0>; 177 compatible = "via,vt8500-device-clock"; 178 clocks = <&ref24>; 179 enable-reg = <0x254>; 180 enable-bit = <26>; 181 }; 182 183 clkuart3: uart3 { 184 #clock-cells = <0>; 185 compatible = "via,vt8500-device-clock"; 186 clocks = <&ref24>; 187 enable-reg = <0x254>; 188 enable-bit = <27>; 189 }; 190 191 clkuart4: uart4 { 192 #clock-cells = <0>; 193 compatible = "via,vt8500-device-clock"; 194 clocks = <&ref24>; 195 enable-reg = <0x254>; 196 enable-bit = <28>; 197 }; 198 199 clkuart5: uart5 { 200 #clock-cells = <0>; 201 compatible = "via,vt8500-device-clock"; 202 clocks = <&ref24>; 203 enable-reg = <0x254>; 204 enable-bit = <29>; 205 }; 206 207 clkpwm: pwm { 208 #clock-cells = <0>; 209 compatible = "via,vt8500-device-clock"; 210 clocks = <&pllb>; 211 divisor-reg = <0x350>; 212 enable-reg = <0x250>; 213 enable-bit = <17>; 214 }; 215 216 clksdhc: sdhc { 217 #clock-cells = <0>; 218 compatible = "via,vt8500-device-clock"; 219 clocks = <&pllb>; 220 divisor-reg = <0x330>; 221 divisor-mask = <0x3f>; 222 enable-reg = <0x250>; 223 enable-bit = <0>; 224 }; 225 226 clki2c0: i2c0clk { 227 #clock-cells = <0>; 228 compatible = "via,vt8500-device-clock"; 229 clocks = <&pllb>; 230 divisor-reg = <0x3A0>; 231 enable-reg = <0x250>; 232 enable-bit = <8>; 233 }; 234 235 clki2c1: i2c1clk { 236 #clock-cells = <0>; 237 compatible = "via,vt8500-device-clock"; 238 clocks = <&pllb>; 239 divisor-reg = <0x3A4>; 240 enable-reg = <0x250>; 241 enable-bit = <9>; 242 }; 243 }; 244 }; 245 246 pwm: pwm@d8220000 { 247 #pwm-cells = <3>; 248 compatible = "via,vt8500-pwm"; 249 reg = <0xd8220000 0x100>; 250 clocks = <&clkpwm>; 251 }; 252 253 timer@d8130100 { 254 compatible = "via,vt8500-timer"; 255 reg = <0xd8130100 0x28>; 256 interrupts = <36>, <37>, <38>, <39>; 257 }; 258 259 usb@d8007900 { 260 compatible = "via,vt8500-ehci"; 261 reg = <0xd8007900 0x200>; 262 interrupts = <26>; 263 }; 264 265 usb@d8007b00 { 266 compatible = "platform-uhci"; 267 reg = <0xd8007b00 0x200>; 268 interrupts = <26>; 269 }; 270 271 usb@d8008d00 { 272 compatible = "platform-uhci"; 273 reg = <0xd8008d00 0x200>; 274 interrupts = <26>; 275 }; 276 277 uart0: serial@d8200000 { 278 compatible = "via,vt8500-uart"; 279 reg = <0xd8200000 0x1040>; 280 interrupts = <32>; 281 clocks = <&clkuart0>; 282 status = "disabled"; 283 }; 284 285 uart1: serial@d82b0000 { 286 compatible = "via,vt8500-uart"; 287 reg = <0xd82b0000 0x1040>; 288 interrupts = <33>; 289 clocks = <&clkuart1>; 290 status = "disabled"; 291 }; 292 293 uart2: serial@d8210000 { 294 compatible = "via,vt8500-uart"; 295 reg = <0xd8210000 0x1040>; 296 interrupts = <47>; 297 clocks = <&clkuart2>; 298 status = "disabled"; 299 }; 300 301 uart3: serial@d82c0000 { 302 compatible = "via,vt8500-uart"; 303 reg = <0xd82c0000 0x1040>; 304 interrupts = <50>; 305 clocks = <&clkuart3>; 306 status = "disabled"; 307 }; 308 309 uart4: serial@d8370000 { 310 compatible = "via,vt8500-uart"; 311 reg = <0xd8370000 0x1040>; 312 interrupts = <30>; 313 clocks = <&clkuart4>; 314 status = "disabled"; 315 }; 316 317 uart5: serial@d8380000 { 318 compatible = "via,vt8500-uart"; 319 reg = <0xd8380000 0x1040>; 320 interrupts = <43>; 321 clocks = <&clkuart5>; 322 status = "disabled"; 323 }; 324 325 rtc@d8100000 { 326 compatible = "via,vt8500-rtc"; 327 reg = <0xd8100000 0x10000>; 328 interrupts = <48>; 329 }; 330 331 sdhc@d800a000 { 332 compatible = "wm,wm8505-sdhc"; 333 reg = <0xd800a000 0x1000>; 334 interrupts = <20 21>; 335 clocks = <&clksdhc>; 336 bus-width = <4>; 337 sdon-inverted; 338 }; 339 340 i2c_0: i2c@d8280000 { 341 compatible = "wm,wm8505-i2c"; 342 reg = <0xd8280000 0x1000>; 343 interrupts = <19>; 344 clocks = <&clki2c0>; 345 clock-frequency = <400000>; 346 }; 347 348 i2c_1: i2c@d8320000 { 349 compatible = "wm,wm8505-i2c"; 350 reg = <0xd8320000 0x1000>; 351 interrupts = <18>; 352 clocks = <&clki2c1>; 353 clock-frequency = <400000>; 354 }; 355 }; 356}; 357