1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC 4 * 5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 6 */ 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 compatible = "wm,wm8650"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "arm,arm926ej-s"; 20 reg = <0x0>; 21 }; 22 }; 23 24 aliases { 25 serial0 = &uart0; 26 serial1 = &uart1; 27 }; 28 29 soc { 30 #address-cells = <1>; 31 #size-cells = <1>; 32 compatible = "simple-bus"; 33 ranges; 34 interrupt-parent = <&intc0>; 35 36 intc0: interrupt-controller@d8140000 { 37 compatible = "via,vt8500-intc"; 38 interrupt-controller; 39 reg = <0xd8140000 0x10000>; 40 #interrupt-cells = <1>; 41 }; 42 43 /* Secondary IC cascaded to intc0 */ 44 intc1: interrupt-controller@d8150000 { 45 compatible = "via,vt8500-intc"; 46 interrupt-controller; 47 #interrupt-cells = <1>; 48 reg = <0xD8150000 0x10000>; 49 interrupts = <56 57 58 59 60 61 62 63>; 50 }; 51 52 pinctrl: pinctrl@d8110000 { 53 compatible = "wm,wm8650-pinctrl"; 54 reg = <0xd8110000 0x10000>; 55 interrupt-controller; 56 #interrupt-cells = <2>; 57 gpio-controller; 58 #gpio-cells = <2>; 59 }; 60 61 chipid@d8120000 { 62 compatible = "via,vt8500-scc-id"; 63 reg = <0xd8120000 0x4>; 64 }; 65 66 pmc@d8130000 { 67 compatible = "via,vt8500-pmc"; 68 reg = <0xd8130000 0x1000>; 69 70 clocks { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 ref25: ref25M { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <25000000>; 78 }; 79 80 ref24: ref24M { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <24000000>; 84 }; 85 86 plla: plla { 87 #clock-cells = <0>; 88 compatible = "wm,wm8650-pll-clock"; 89 clocks = <&ref25>; 90 reg = <0x200>; 91 }; 92 93 pllb: pllb { 94 #clock-cells = <0>; 95 compatible = "wm,wm8650-pll-clock"; 96 clocks = <&ref25>; 97 reg = <0x204>; 98 }; 99 100 pllc: pllc { 101 #clock-cells = <0>; 102 compatible = "wm,wm8650-pll-clock"; 103 clocks = <&ref25>; 104 reg = <0x208>; 105 }; 106 107 plld: plld { 108 #clock-cells = <0>; 109 compatible = "wm,wm8650-pll-clock"; 110 clocks = <&ref25>; 111 reg = <0x20c>; 112 }; 113 114 plle: plle { 115 #clock-cells = <0>; 116 compatible = "wm,wm8650-pll-clock"; 117 clocks = <&ref25>; 118 reg = <0x210>; 119 }; 120 121 clkarm: arm { 122 #clock-cells = <0>; 123 compatible = "via,vt8500-device-clock"; 124 clocks = <&plla>; 125 divisor-reg = <0x300>; 126 }; 127 128 clkahb: ahb { 129 #clock-cells = <0>; 130 compatible = "via,vt8500-device-clock"; 131 clocks = <&pllb>; 132 divisor-reg = <0x304>; 133 }; 134 135 clkapb: apb { 136 #clock-cells = <0>; 137 compatible = "via,vt8500-device-clock"; 138 clocks = <&pllb>; 139 divisor-reg = <0x320>; 140 }; 141 142 clkddr: ddr { 143 #clock-cells = <0>; 144 compatible = "via,vt8500-device-clock"; 145 clocks = <&plld>; 146 divisor-reg = <0x310>; 147 }; 148 149 clkuart0: uart0 { 150 #clock-cells = <0>; 151 compatible = "via,vt8500-device-clock"; 152 clocks = <&ref24>; 153 enable-reg = <0x250>; 154 enable-bit = <1>; 155 }; 156 157 clkuart1: uart1 { 158 #clock-cells = <0>; 159 compatible = "via,vt8500-device-clock"; 160 clocks = <&ref24>; 161 enable-reg = <0x250>; 162 enable-bit = <2>; 163 }; 164 165 clksdhc: sdhc { 166 #clock-cells = <0>; 167 compatible = "via,vt8500-device-clock"; 168 clocks = <&pllb>; 169 divisor-reg = <0x328>; 170 divisor-mask = <0x3f>; 171 enable-reg = <0x254>; 172 enable-bit = <18>; 173 }; 174 }; 175 }; 176 177 timer@d8130100 { 178 compatible = "via,vt8500-timer"; 179 reg = <0xd8130100 0x28>; 180 interrupts = <36>, <37>, <38>, <39>; 181 }; 182 183 usb@d8007900 { 184 compatible = "via,vt8500-ehci"; 185 reg = <0xd8007900 0x200>; 186 interrupts = <43>; 187 }; 188 189 usb@d8007b00 { 190 compatible = "platform-uhci"; 191 reg = <0xd8007b00 0x200>; 192 interrupts = <43>; 193 }; 194 195 mmc@d800a000 { 196 compatible = "wm,wm8505-sdhc"; 197 reg = <0xd800a000 0x400>; 198 interrupts = <20>, <21>; 199 clocks = <&clksdhc>; 200 bus-width = <4>; 201 sdon-inverted; 202 }; 203 204 fb: fb@d8050800 { 205 compatible = "wm,wm8505-fb"; 206 reg = <0xd8050800 0x200>; 207 }; 208 209 ge_rops@d8050400 { 210 compatible = "wm,prizm-ge-rops"; 211 reg = <0xd8050400 0x100>; 212 }; 213 214 uart0: serial@d8200000 { 215 compatible = "via,vt8500-uart"; 216 reg = <0xd8200000 0x1040>; 217 interrupts = <32>; 218 clocks = <&clkuart0>; 219 status = "disabled"; 220 }; 221 222 uart1: serial@d82b0000 { 223 compatible = "via,vt8500-uart"; 224 reg = <0xd82b0000 0x1040>; 225 interrupts = <33>; 226 clocks = <&clkuart1>; 227 status = "disabled"; 228 }; 229 230 rtc@d8100000 { 231 compatible = "via,vt8500-rtc"; 232 reg = <0xd8100000 0x10000>; 233 interrupts = <48>; 234 }; 235 236 ethernet@d8004000 { 237 compatible = "via,vt8500-rhine"; 238 reg = <0xd8004000 0x100>; 239 interrupts = <10>; 240 }; 241 }; 242}; 243