1&l4_abe { /* 0x40100000 */ 2 compatible = "ti,omap5-l4-abe", "simple-pm-bus"; 3 reg = <0x40100000 0x400>, 4 <0x40100400 0x400>; 5 reg-names = "la", "ap"; 6 power-domains = <&prm_abe>; 7 /* OMAP5_L4_ABE_CLKCTRL is read-only */ 8 #address-cells = <1>; 9 #size-cells = <1>; 10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ 11 <0x49000000 0x49000000 0x100000>; 12 segment@0 { /* 0x40100000 */ 13 compatible = "simple-pm-bus"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = 17 /* CPU to L4 ABE mapping */ 18 <0x00000000 0x00000000 0x000400>, /* ap 0 */ 19 <0x00000400 0x00000400 0x000400>, /* ap 1 */ 20 <0x00022000 0x00022000 0x001000>, /* ap 2 */ 21 <0x00023000 0x00023000 0x001000>, /* ap 3 */ 22 <0x00024000 0x00024000 0x001000>, /* ap 4 */ 23 <0x00025000 0x00025000 0x001000>, /* ap 5 */ 24 <0x00026000 0x00026000 0x001000>, /* ap 6 */ 25 <0x00027000 0x00027000 0x001000>, /* ap 7 */ 26 <0x00028000 0x00028000 0x001000>, /* ap 8 */ 27 <0x00029000 0x00029000 0x001000>, /* ap 9 */ 28 <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ 29 <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ 30 <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ 31 <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ 32 <0x00030000 0x00030000 0x001000>, /* ap 14 */ 33 <0x00031000 0x00031000 0x001000>, /* ap 15 */ 34 <0x00032000 0x00032000 0x001000>, /* ap 16 */ 35 <0x00033000 0x00033000 0x001000>, /* ap 17 */ 36 <0x00038000 0x00038000 0x001000>, /* ap 18 */ 37 <0x00039000 0x00039000 0x001000>, /* ap 19 */ 38 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ 39 <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ 40 <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ 41 <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ 42 <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ 43 <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ 44 <0x00080000 0x00080000 0x010000>, /* ap 26 */ 45 <0x00080000 0x00080000 0x001000>, /* ap 27 */ 46 <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ 47 <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ 48 <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ 49 <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ 50 <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ 51 <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ 52 53 /* L3 to L4 ABE mapping */ 54 <0x49000000 0x49000000 0x000400>, /* ap 0 */ 55 <0x49000400 0x49000400 0x000400>, /* ap 1 */ 56 <0x49022000 0x49022000 0x001000>, /* ap 2 */ 57 <0x49023000 0x49023000 0x001000>, /* ap 3 */ 58 <0x49024000 0x49024000 0x001000>, /* ap 4 */ 59 <0x49025000 0x49025000 0x001000>, /* ap 5 */ 60 <0x49026000 0x49026000 0x001000>, /* ap 6 */ 61 <0x49027000 0x49027000 0x001000>, /* ap 7 */ 62 <0x49028000 0x49028000 0x001000>, /* ap 8 */ 63 <0x49029000 0x49029000 0x001000>, /* ap 9 */ 64 <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ 65 <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ 66 <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ 67 <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ 68 <0x49030000 0x49030000 0x001000>, /* ap 14 */ 69 <0x49031000 0x49031000 0x001000>, /* ap 15 */ 70 <0x49032000 0x49032000 0x001000>, /* ap 16 */ 71 <0x49033000 0x49033000 0x001000>, /* ap 17 */ 72 <0x49038000 0x49038000 0x001000>, /* ap 18 */ 73 <0x49039000 0x49039000 0x001000>, /* ap 19 */ 74 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ 75 <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ 76 <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ 77 <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ 78 <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ 79 <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ 80 <0x49080000 0x49080000 0x010000>, /* ap 26 */ 81 <0x49080000 0x49080000 0x001000>, /* ap 27 */ 82 <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ 83 <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ 84 <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ 85 <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ 86 <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ 87 <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ 88 89 target-module@22000 { /* 0x40122000, ap 2 02.0 */ 90 compatible = "ti,sysc-omap2", "ti,sysc"; 91 reg = <0x2208c 0x4>; 92 reg-names = "sysc"; 93 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 94 SYSC_OMAP2_ENAWAKEUP | 95 SYSC_OMAP2_SOFTRESET)>; 96 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 97 <SYSC_IDLE_NO>, 98 <SYSC_IDLE_SMART>; 99 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 100 clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>; 101 clock-names = "fck"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0x0 0x22000 0x1000>, 105 <0x49022000 0x49022000 0x1000>; 106 107 mcbsp1: mcbsp@0 { 108 compatible = "ti,omap4-mcbsp"; 109 reg = <0x0 0xff>, /* MPU private access */ 110 <0x49022000 0xff>; /* L3 Interconnect */ 111 reg-names = "mpu", "dma"; 112 clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 24>; 113 clock-names = "fck"; 114 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 115 interrupt-names = "common"; 116 ti,buffer-size = <128>; 117 dmas = <&sdma 33>, 118 <&sdma 34>; 119 dma-names = "tx", "rx"; 120 status = "disabled"; 121 }; 122 }; 123 124 target-module@24000 { /* 0x40124000, ap 4 04.0 */ 125 compatible = "ti,sysc-omap2", "ti,sysc"; 126 reg = <0x2408c 0x4>; 127 reg-names = "sysc"; 128 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 129 SYSC_OMAP2_ENAWAKEUP | 130 SYSC_OMAP2_SOFTRESET)>; 131 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 132 <SYSC_IDLE_NO>, 133 <SYSC_IDLE_SMART>; 134 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 135 clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>; 136 clock-names = "fck"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges = <0x0 0x24000 0x1000>, 140 <0x49024000 0x49024000 0x1000>; 141 142 mcbsp2: mcbsp@0 { 143 compatible = "ti,omap4-mcbsp"; 144 reg = <0x0 0xff>, /* MPU private access */ 145 <0x49024000 0xff>; /* L3 Interconnect */ 146 reg-names = "mpu", "dma"; 147 clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 24>; 148 clock-names = "fck"; 149 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 150 interrupt-names = "common"; 151 ti,buffer-size = <128>; 152 dmas = <&sdma 17>, 153 <&sdma 18>; 154 dma-names = "tx", "rx"; 155 status = "disabled"; 156 }; 157 }; 158 159 target-module@26000 { /* 0x40126000, ap 6 06.0 */ 160 compatible = "ti,sysc-omap2", "ti,sysc"; 161 reg = <0x2608c 0x4>; 162 reg-names = "sysc"; 163 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 164 SYSC_OMAP2_ENAWAKEUP | 165 SYSC_OMAP2_SOFTRESET)>; 166 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 167 <SYSC_IDLE_NO>, 168 <SYSC_IDLE_SMART>; 169 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 170 clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>; 171 clock-names = "fck"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges = <0x0 0x26000 0x1000>, 175 <0x49026000 0x49026000 0x1000>; 176 177 mcbsp3: mcbsp@0 { 178 compatible = "ti,omap4-mcbsp"; 179 reg = <0x0 0xff>, /* MPU private access */ 180 <0x49026000 0xff>; /* L3 Interconnect */ 181 reg-names = "mpu", "dma"; 182 clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 24>; 183 clock-names = "fck"; 184 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "common"; 186 ti,buffer-size = <128>; 187 dmas = <&sdma 19>, 188 <&sdma 20>; 189 dma-names = "tx", "rx"; 190 status = "disabled"; 191 }; 192 }; 193 194 target-module@28000 { /* 0x40128000, ap 8 08.0 */ 195 compatible = "ti,sysc"; 196 status = "disabled"; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges = <0x0 0x28000 0x1000>, 200 <0x49028000 0x49028000 0x1000>; 201 }; 202 203 target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ 204 compatible = "ti,sysc"; 205 status = "disabled"; 206 #address-cells = <1>; 207 #size-cells = <1>; 208 ranges = <0x0 0x2a000 0x1000>, 209 <0x4902a000 0x4902a000 0x1000>; 210 }; 211 212 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ 213 compatible = "ti,sysc-omap4", "ti,sysc"; 214 reg = <0x2e000 0x4>, 215 <0x2e010 0x4>; 216 reg-names = "rev", "sysc"; 217 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 218 SYSC_OMAP4_SOFTRESET)>; 219 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 220 <SYSC_IDLE_NO>, 221 <SYSC_IDLE_SMART>, 222 <SYSC_IDLE_SMART_WKUP>; 223 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 224 clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>; 225 clock-names = "fck"; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0x0 0x2e000 0x1000>, 229 <0x4902e000 0x4902e000 0x1000>; 230 231 dmic: dmic@0 { 232 compatible = "ti,omap4-dmic"; 233 reg = <0x0 0x7f>, /* MPU private access */ 234 <0x4902e000 0x7f>; /* L3 Interconnect */ 235 reg-names = "mpu", "dma"; 236 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 237 dmas = <&sdma 67>; 238 dma-names = "up_link"; 239 status = "disabled"; 240 }; 241 }; 242 243 target-module@30000 { /* 0x40130000, ap 14 0e.0 */ 244 compatible = "ti,sysc"; 245 status = "disabled"; 246 #address-cells = <1>; 247 #size-cells = <1>; 248 ranges = <0x0 0x30000 0x1000>, 249 <0x49030000 0x49030000 0x1000>; 250 }; 251 252 mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ 253 compatible = "ti,sysc-omap4", "ti,sysc"; 254 reg = <0x32000 0x4>, 255 <0x32010 0x4>; 256 reg-names = "rev", "sysc"; 257 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 258 SYSC_OMAP4_SOFTRESET)>; 259 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 260 <SYSC_IDLE_NO>, 261 <SYSC_IDLE_SMART>, 262 <SYSC_IDLE_SMART_WKUP>; 263 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 264 clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>; 265 clock-names = "fck"; 266 #address-cells = <1>; 267 #size-cells = <1>; 268 ranges = <0x0 0x32000 0x1000>, 269 <0x49032000 0x49032000 0x1000>; 270 271 /* Must be only enabled for boards with pdmclk wired */ 272 status = "disabled"; 273 274 mcpdm: mcpdm@0 { 275 compatible = "ti,omap4-mcpdm"; 276 reg = <0x0 0x7f>, /* MPU private access */ 277 <0x49032000 0x7f>; /* L3 Interconnect */ 278 reg-names = "mpu", "dma"; 279 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 280 dmas = <&sdma 65>, 281 <&sdma 66>; 282 dma-names = "up_link", "dn_link"; 283 }; 284 }; 285 286 target-module@38000 { /* 0x40138000, ap 18 12.0 */ 287 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 288 reg = <0x38000 0x4>, 289 <0x38010 0x4>; 290 reg-names = "rev", "sysc"; 291 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 292 SYSC_OMAP4_SOFTRESET)>; 293 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 294 <SYSC_IDLE_NO>, 295 <SYSC_IDLE_SMART>, 296 <SYSC_IDLE_SMART_WKUP>; 297 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 298 clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>; 299 clock-names = "fck"; 300 #address-cells = <1>; 301 #size-cells = <1>; 302 ranges = <0x0 0x38000 0x1000>, 303 <0x49038000 0x49038000 0x1000>; 304 305 timer5: timer@0 { 306 compatible = "ti,omap5430-timer"; 307 reg = <0x0 0x80>, 308 <0x49038000 0x80>; 309 clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>, 310 <&dss_syc_gfclk_div>; 311 clock-names = "fck", "timer_sys_ck"; 312 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 313 ti,timer-dsp; 314 ti,timer-pwm; 315 }; 316 }; 317 318 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ 319 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 320 reg = <0x3a000 0x4>, 321 <0x3a010 0x4>; 322 reg-names = "rev", "sysc"; 323 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 324 SYSC_OMAP4_SOFTRESET)>; 325 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 326 <SYSC_IDLE_NO>, 327 <SYSC_IDLE_SMART>, 328 <SYSC_IDLE_SMART_WKUP>; 329 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 330 clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>; 331 clock-names = "fck"; 332 #address-cells = <1>; 333 #size-cells = <1>; 334 ranges = <0x0 0x3a000 0x1000>, 335 <0x4903a000 0x4903a000 0x1000>; 336 337 timer6: timer@0 { 338 compatible = "ti,omap5430-timer"; 339 reg = <0x0 0x80>, 340 <0x4903a000 0x80>; 341 clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>, 342 <&dss_syc_gfclk_div>; 343 clock-names = "fck", "timer_sys_ck"; 344 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 345 ti,timer-dsp; 346 ti,timer-pwm; 347 }; 348 }; 349 350 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ 351 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 352 reg = <0x3c000 0x4>, 353 <0x3c010 0x4>; 354 reg-names = "rev", "sysc"; 355 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 356 SYSC_OMAP4_SOFTRESET)>; 357 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 358 <SYSC_IDLE_NO>, 359 <SYSC_IDLE_SMART>, 360 <SYSC_IDLE_SMART_WKUP>; 361 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 362 clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>; 363 clock-names = "fck"; 364 #address-cells = <1>; 365 #size-cells = <1>; 366 ranges = <0x0 0x3c000 0x1000>, 367 <0x4903c000 0x4903c000 0x1000>; 368 369 timer7: timer@0 { 370 compatible = "ti,omap5430-timer"; 371 reg = <0x0 0x80>, 372 <0x4903c000 0x80>; 373 clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>, 374 <&dss_syc_gfclk_div>; 375 clock-names = "fck", "timer_sys_ck"; 376 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 377 ti,timer-dsp; 378 }; 379 }; 380 381 target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ 382 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 383 reg = <0x3e000 0x4>, 384 <0x3e010 0x4>; 385 reg-names = "rev", "sysc"; 386 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 387 SYSC_OMAP4_SOFTRESET)>; 388 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 389 <SYSC_IDLE_NO>, 390 <SYSC_IDLE_SMART>, 391 <SYSC_IDLE_SMART_WKUP>; 392 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ 393 clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>; 394 clock-names = "fck"; 395 #address-cells = <1>; 396 #size-cells = <1>; 397 ranges = <0x0 0x3e000 0x1000>, 398 <0x4903e000 0x4903e000 0x1000>; 399 400 timer8: timer@0 { 401 compatible = "ti,omap5430-timer"; 402 reg = <0x0 0x80>, 403 <0x4903e000 0x80>; 404 clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>, 405 <&dss_syc_gfclk_div>; 406 clock-names = "fck", "timer_sys_ck"; 407 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 408 ti,timer-dsp; 409 ti,timer-pwm; 410 }; 411 }; 412 413 target-module@80000 { /* 0x40180000, ap 26 1a.0 */ 414 compatible = "ti,sysc"; 415 status = "disabled"; 416 #address-cells = <1>; 417 #size-cells = <1>; 418 ranges = <0x0 0x80000 0x10000>, 419 <0x49080000 0x49080000 0x10000>; 420 }; 421 422 target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ 423 compatible = "ti,sysc"; 424 status = "disabled"; 425 #address-cells = <1>; 426 #size-cells = <1>; 427 ranges = <0x0 0xa0000 0x10000>, 428 <0x490a0000 0x490a0000 0x10000>; 429 }; 430 431 target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ 432 compatible = "ti,sysc"; 433 status = "disabled"; 434 #address-cells = <1>; 435 #size-cells = <1>; 436 ranges = <0x0 0xc0000 0x10000>, 437 <0x490c0000 0x490c0000 0x10000>; 438 }; 439 440 target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ 441 compatible = "ti,sysc-omap4", "ti,sysc"; 442 reg = <0xf1000 0x4>, 443 <0xf1010 0x4>; 444 reg-names = "rev", "sysc"; 445 ti,sysc-midle = <SYSC_IDLE_FORCE>, 446 <SYSC_IDLE_NO>, 447 <SYSC_IDLE_SMART>, 448 <SYSC_IDLE_SMART_WKUP>; 449 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 450 <SYSC_IDLE_NO>, 451 <SYSC_IDLE_SMART>; 452 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 453 clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>; 454 clock-names = "fck"; 455 #address-cells = <1>; 456 #size-cells = <1>; 457 ranges = <0x0 0xf1000 0x1000>, 458 <0x490f1000 0x490f1000 0x1000>; 459 }; 460 }; 461}; 462 463