1&l4_abe { /* 0x40100000 */ 2 compatible = "ti,omap4-l4-abe", "simple-pm-bus"; 3 reg = <0x40100000 0x400>, 4 <0x40100400 0x400>; 5 reg-names = "la", "ap"; 6 power-domains = <&prm_abe>; 7 /* OMAP4_L4_ABE_CLKCTRL is read-only */ 8 #address-cells = <1>; 9 #size-cells = <1>; 10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ 11 <0x49000000 0x49000000 0x100000>; 12 segment@0 { /* 0x40100000 */ 13 compatible = "simple-pm-bus"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = 17 /* CPU to L4 ABE mapping */ 18 <0x00000000 0x00000000 0x000400>, /* ap 0 */ 19 <0x00000400 0x00000400 0x000400>, /* ap 1 */ 20 <0x00022000 0x00022000 0x001000>, /* ap 2 */ 21 <0x00023000 0x00023000 0x001000>, /* ap 3 */ 22 <0x00024000 0x00024000 0x001000>, /* ap 4 */ 23 <0x00025000 0x00025000 0x001000>, /* ap 5 */ 24 <0x00026000 0x00026000 0x001000>, /* ap 6 */ 25 <0x00027000 0x00027000 0x001000>, /* ap 7 */ 26 <0x00028000 0x00028000 0x001000>, /* ap 8 */ 27 <0x00029000 0x00029000 0x001000>, /* ap 9 */ 28 <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ 29 <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ 30 <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ 31 <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ 32 <0x00030000 0x00030000 0x001000>, /* ap 14 */ 33 <0x00031000 0x00031000 0x001000>, /* ap 15 */ 34 <0x00032000 0x00032000 0x001000>, /* ap 16 */ 35 <0x00033000 0x00033000 0x001000>, /* ap 17 */ 36 <0x00038000 0x00038000 0x001000>, /* ap 18 */ 37 <0x00039000 0x00039000 0x001000>, /* ap 19 */ 38 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ 39 <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ 40 <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ 41 <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ 42 <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ 43 <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ 44 <0x00080000 0x00080000 0x010000>, /* ap 26 */ 45 <0x00080000 0x00080000 0x001000>, /* ap 27 */ 46 <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ 47 <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ 48 <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ 49 <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ 50 <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ 51 <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ 52 53 /* L3 to L4 ABE mapping */ 54 <0x49000000 0x49000000 0x000400>, /* ap 0 */ 55 <0x49000400 0x49000400 0x000400>, /* ap 1 */ 56 <0x49022000 0x49022000 0x001000>, /* ap 2 */ 57 <0x49023000 0x49023000 0x001000>, /* ap 3 */ 58 <0x49024000 0x49024000 0x001000>, /* ap 4 */ 59 <0x49025000 0x49025000 0x001000>, /* ap 5 */ 60 <0x49026000 0x49026000 0x001000>, /* ap 6 */ 61 <0x49027000 0x49027000 0x001000>, /* ap 7 */ 62 <0x49028000 0x49028000 0x001000>, /* ap 8 */ 63 <0x49029000 0x49029000 0x001000>, /* ap 9 */ 64 <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ 65 <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ 66 <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ 67 <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ 68 <0x49030000 0x49030000 0x001000>, /* ap 14 */ 69 <0x49031000 0x49031000 0x001000>, /* ap 15 */ 70 <0x49032000 0x49032000 0x001000>, /* ap 16 */ 71 <0x49033000 0x49033000 0x001000>, /* ap 17 */ 72 <0x49038000 0x49038000 0x001000>, /* ap 18 */ 73 <0x49039000 0x49039000 0x001000>, /* ap 19 */ 74 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ 75 <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ 76 <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ 77 <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ 78 <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ 79 <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ 80 <0x49080000 0x49080000 0x010000>, /* ap 26 */ 81 <0x49080000 0x49080000 0x001000>, /* ap 27 */ 82 <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ 83 <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ 84 <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ 85 <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ 86 <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ 87 <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ 88 89 target-module@22000 { /* 0x40122000, ap 2 02.0 */ 90 compatible = "ti,sysc-omap2", "ti,sysc"; 91 reg = <0x2208c 0x4>; 92 reg-names = "sysc"; 93 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 94 SYSC_OMAP2_ENAWAKEUP | 95 SYSC_OMAP2_SOFTRESET)>; 96 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 97 <SYSC_IDLE_NO>, 98 <SYSC_IDLE_SMART>; 99 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 100 clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>; 101 clock-names = "fck"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0x0 0x22000 0x1000>, 105 <0x49022000 0x49022000 0x1000>; 106 107 mcbsp1: mcbsp@0 { 108 compatible = "ti,omap4-mcbsp"; 109 reg = <0x0 0xff>, /* MPU private access */ 110 <0x49022000 0xff>; /* L3 Interconnect */ 111 reg-names = "mpu", "dma"; 112 clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 24>; 113 clock-names = "fck"; 114 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 115 interrupt-names = "common"; 116 ti,buffer-size = <128>; 117 dmas = <&sdma 33>, 118 <&sdma 34>; 119 dma-names = "tx", "rx"; 120 status = "disabled"; 121 }; 122 }; 123 124 target-module@24000 { /* 0x40124000, ap 4 04.0 */ 125 compatible = "ti,sysc-omap2", "ti,sysc"; 126 reg = <0x2408c 0x4>; 127 reg-names = "sysc"; 128 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 129 SYSC_OMAP2_ENAWAKEUP | 130 SYSC_OMAP2_SOFTRESET)>; 131 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 132 <SYSC_IDLE_NO>, 133 <SYSC_IDLE_SMART>; 134 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 135 clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>; 136 clock-names = "fck"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges = <0x0 0x24000 0x1000>, 140 <0x49024000 0x49024000 0x1000>; 141 142 mcbsp2: mcbsp@0 { 143 compatible = "ti,omap4-mcbsp"; 144 reg = <0x0 0xff>, /* MPU private access */ 145 <0x49024000 0xff>; /* L3 Interconnect */ 146 reg-names = "mpu", "dma"; 147 clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 24>; 148 clock-names = "fck"; 149 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 150 interrupt-names = "common"; 151 ti,buffer-size = <128>; 152 dmas = <&sdma 17>, 153 <&sdma 18>; 154 dma-names = "tx", "rx"; 155 status = "disabled"; 156 }; 157 }; 158 159 target-module@26000 { /* 0x40126000, ap 6 06.0 */ 160 compatible = "ti,sysc-omap2", "ti,sysc"; 161 reg = <0x2608c 0x4>; 162 reg-names = "sysc"; 163 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 164 SYSC_OMAP2_ENAWAKEUP | 165 SYSC_OMAP2_SOFTRESET)>; 166 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 167 <SYSC_IDLE_NO>, 168 <SYSC_IDLE_SMART>; 169 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 170 clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>; 171 clock-names = "fck"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges = <0x0 0x26000 0x1000>, 175 <0x49026000 0x49026000 0x1000>; 176 177 mcbsp3: mcbsp@0 { 178 compatible = "ti,omap4-mcbsp"; 179 reg = <0x0 0xff>, /* MPU private access */ 180 <0x49026000 0xff>; /* L3 Interconnect */ 181 reg-names = "mpu", "dma"; 182 clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 24>; 183 clock-names = "fck"; 184 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "common"; 186 ti,buffer-size = <128>; 187 dmas = <&sdma 19>, 188 <&sdma 20>; 189 dma-names = "tx", "rx"; 190 status = "disabled"; 191 }; 192 }; 193 194 target-module@28000 { /* 0x40128000, ap 8 08.0 */ 195 /* 0x4012a000, ap 10 0a.0 */ 196 compatible = "ti,sysc-mcasp", "ti,sysc"; 197 reg = <0x28000 0x4>, 198 <0x28004 0x4>; 199 reg-names = "rev", "sysc"; 200 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 201 <SYSC_IDLE_NO>, 202 <SYSC_IDLE_SMART>; 203 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 204 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; 205 clock-names = "fck"; 206 #address-cells = <1>; 207 #size-cells = <1>; 208 ranges = <0x0 0x28000 0x1000>, 209 <0x49028000 0x49028000 0x1000>, 210 <0x2000 0x2a000 0x1000>, 211 <0x4902a000 0x4902a000 0x1000>; 212 213 mcasp0: mcasp@0 { 214 compatible = "ti,omap4-mcasp-audio"; 215 reg = <0x0 0x2000>, 216 <0x4902a000 0x1000>; /* L3 data port */ 217 reg-names = "mpu","dat"; 218 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 219 interrupt-names = "tx"; 220 dmas = <&sdma 8>; 221 dma-names = "tx"; 222 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; 223 clock-names = "fck"; 224 op-mode = <1>; /* MCASP_DIT_MODE */ 225 serial-dir = < 1 >; /* 1 TX serializers */ 226 status = "disabled"; 227 }; 228 }; 229 230 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ 231 compatible = "ti,sysc-omap4", "ti,sysc"; 232 reg = <0x2e000 0x4>, 233 <0x2e010 0x4>; 234 reg-names = "rev", "sysc"; 235 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 236 SYSC_OMAP4_SOFTRESET)>; 237 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 238 <SYSC_IDLE_NO>, 239 <SYSC_IDLE_SMART>, 240 <SYSC_IDLE_SMART_WKUP>; 241 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 242 clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>; 243 clock-names = "fck"; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges = <0x0 0x2e000 0x1000>, 247 <0x4902e000 0x4902e000 0x1000>; 248 249 dmic: dmic@0 { 250 compatible = "ti,omap4-dmic"; 251 reg = <0x0 0x7f>, /* MPU private access */ 252 <0x4902e000 0x7f>; /* L3 Interconnect */ 253 reg-names = "mpu", "dma"; 254 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 255 dmas = <&sdma 67>; 256 dma-names = "up_link"; 257 status = "disabled"; 258 }; 259 }; 260 261 target-module@30000 { /* 0x40130000, ap 14 0e.0 */ 262 compatible = "ti,sysc-omap2", "ti,sysc"; 263 reg = <0x30000 0x4>, 264 <0x30010 0x4>, 265 <0x30014 0x4>; 266 reg-names = "rev", "sysc", "syss"; 267 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 268 SYSC_OMAP2_SOFTRESET)>; 269 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 270 <SYSC_IDLE_NO>, 271 <SYSC_IDLE_SMART>, 272 <SYSC_IDLE_SMART_WKUP>; 273 ti,syss-mask = <1>; 274 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 275 clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; 276 clock-names = "fck"; 277 #address-cells = <1>; 278 #size-cells = <1>; 279 ranges = <0x0 0x30000 0x1000>, 280 <0x49030000 0x49030000 0x1000>; 281 282 wdt3: wdt@0 { 283 compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 284 reg = <0x0 0x80>; 285 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 286 }; 287 }; 288 289 mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ 290 compatible = "ti,sysc-omap4", "ti,sysc"; 291 reg = <0x32000 0x4>, 292 <0x32010 0x4>; 293 reg-names = "rev", "sysc"; 294 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 295 SYSC_OMAP4_SOFTRESET)>; 296 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 297 <SYSC_IDLE_NO>, 298 <SYSC_IDLE_SMART>, 299 <SYSC_IDLE_SMART_WKUP>; 300 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 301 clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>; 302 clock-names = "fck"; 303 #address-cells = <1>; 304 #size-cells = <1>; 305 ranges = <0x0 0x32000 0x1000>, 306 <0x49032000 0x49032000 0x1000>; 307 308 /* Must be only enabled for boards with pdmclk wired */ 309 status = "disabled"; 310 311 mcpdm: mcpdm@0 { 312 compatible = "ti,omap4-mcpdm"; 313 reg = <0x0 0x7f>, /* MPU private access */ 314 <0x49032000 0x7f>; /* L3 Interconnect */ 315 reg-names = "mpu", "dma"; 316 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 317 dmas = <&sdma 65>, 318 <&sdma 66>; 319 dma-names = "up_link", "dn_link"; 320 }; 321 }; 322 323 target-module@38000 { /* 0x40138000, ap 18 12.0 */ 324 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 325 reg = <0x38000 0x4>, 326 <0x38010 0x4>; 327 reg-names = "rev", "sysc"; 328 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 329 SYSC_OMAP4_SOFTRESET)>; 330 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 331 <SYSC_IDLE_NO>, 332 <SYSC_IDLE_SMART>, 333 <SYSC_IDLE_SMART_WKUP>; 334 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 335 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>; 336 clock-names = "fck"; 337 #address-cells = <1>; 338 #size-cells = <1>; 339 ranges = <0x0 0x38000 0x1000>, 340 <0x49038000 0x49038000 0x1000>; 341 342 timer5: timer@0 { 343 compatible = "ti,omap4430-timer"; 344 reg = <0x00000000 0x80>, 345 <0x49038000 0x80>; 346 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>, 347 <&syc_clk_div_ck>; 348 clock-names = "fck", "timer_sys_ck"; 349 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 350 ti,timer-dsp; 351 }; 352 }; 353 354 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ 355 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 356 reg = <0x3a000 0x4>, 357 <0x3a010 0x4>; 358 reg-names = "rev", "sysc"; 359 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 360 SYSC_OMAP4_SOFTRESET)>; 361 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 362 <SYSC_IDLE_NO>, 363 <SYSC_IDLE_SMART>, 364 <SYSC_IDLE_SMART_WKUP>; 365 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 366 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>; 367 clock-names = "fck"; 368 #address-cells = <1>; 369 #size-cells = <1>; 370 ranges = <0x0 0x3a000 0x1000>, 371 <0x4903a000 0x4903a000 0x1000>; 372 373 timer6: timer@0 { 374 compatible = "ti,omap4430-timer"; 375 reg = <0x00000000 0x80>, 376 <0x4903a000 0x80>; 377 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>, 378 <&syc_clk_div_ck>; 379 clock-names = "fck", "timer_sys_ck"; 380 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 381 ti,timer-dsp; 382 }; 383 }; 384 385 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ 386 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 387 reg = <0x3c000 0x4>, 388 <0x3c010 0x4>; 389 reg-names = "rev", "sysc"; 390 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 391 SYSC_OMAP4_SOFTRESET)>; 392 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 393 <SYSC_IDLE_NO>, 394 <SYSC_IDLE_SMART>, 395 <SYSC_IDLE_SMART_WKUP>; 396 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 397 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>; 398 clock-names = "fck"; 399 #address-cells = <1>; 400 #size-cells = <1>; 401 ranges = <0x0 0x3c000 0x1000>, 402 <0x4903c000 0x4903c000 0x1000>; 403 404 timer7: timer@0 { 405 compatible = "ti,omap4430-timer"; 406 reg = <0x00000000 0x80>, 407 <0x4903c000 0x80>; 408 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>, 409 <&syc_clk_div_ck>; 410 clock-names = "fck", "timer_sys_ck"; 411 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 412 ti,timer-dsp; 413 }; 414 }; 415 416 target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ 417 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 418 reg = <0x3e000 0x4>, 419 <0x3e010 0x4>; 420 reg-names = "rev", "sysc"; 421 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 422 SYSC_OMAP4_SOFTRESET)>; 423 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 424 <SYSC_IDLE_NO>, 425 <SYSC_IDLE_SMART>, 426 <SYSC_IDLE_SMART_WKUP>; 427 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 428 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>; 429 clock-names = "fck"; 430 #address-cells = <1>; 431 #size-cells = <1>; 432 ranges = <0x0 0x3e000 0x1000>, 433 <0x4903e000 0x4903e000 0x1000>; 434 435 timer8: timer@0 { 436 compatible = "ti,omap4430-timer"; 437 reg = <0x00000000 0x80>, 438 <0x4903e000 0x80>; 439 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>, 440 <&syc_clk_div_ck>; 441 clock-names = "fck", "timer_sys_ck"; 442 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 443 ti,timer-pwm; 444 ti,timer-dsp; 445 }; 446 }; 447 448 target-module@80000 { /* 0x40180000, ap 26 1a.0 */ 449 compatible = "ti,sysc"; 450 status = "disabled"; 451 #address-cells = <1>; 452 #size-cells = <1>; 453 ranges = <0x0 0x80000 0x10000>, 454 <0x49080000 0x49080000 0x10000>; 455 }; 456 457 target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ 458 compatible = "ti,sysc"; 459 status = "disabled"; 460 #address-cells = <1>; 461 #size-cells = <1>; 462 ranges = <0x0 0xa0000 0x10000>, 463 <0x490a0000 0x490a0000 0x10000>; 464 }; 465 466 target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ 467 compatible = "ti,sysc"; 468 status = "disabled"; 469 #address-cells = <1>; 470 #size-cells = <1>; 471 ranges = <0x0 0xc0000 0x10000>, 472 <0x490c0000 0x490c0000 0x10000>; 473 }; 474 475 target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ 476 compatible = "ti,sysc-omap4", "ti,sysc"; 477 reg = <0xf1000 0x4>, 478 <0xf1010 0x4>; 479 reg-names = "rev", "sysc"; 480 ti,sysc-midle = <SYSC_IDLE_FORCE>, 481 <SYSC_IDLE_NO>, 482 <SYSC_IDLE_SMART>, 483 <SYSC_IDLE_SMART_WKUP>; 484 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 485 <SYSC_IDLE_NO>, 486 <SYSC_IDLE_SMART>; 487 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ 488 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; 489 clock-names = "fck"; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 ranges = <0x0 0xf1000 0x1000>, 493 <0x490f1000 0x490f1000 0x1000>; 494 495 /* 496 * No child device binding or driver in mainline. 497 * See Android tree and related upstreaming efforts 498 * for the old driver. 499 */ 500 }; 501 }; 502}; 503 504