1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Device Tree Source for OMAP3430 ES1 clock data 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 */ 7&cm_clocks { 8 gfx_l3_ck: gfx_l3_ck@b10 { 9 #clock-cells = <0>; 10 compatible = "ti,wait-gate-clock"; 11 clocks = <&l3_ick>; 12 reg = <0x0b10>; 13 ti,bit-shift = <0>; 14 }; 15 16 gfx_l3_fck: gfx_l3_fck@b40 { 17 #clock-cells = <0>; 18 compatible = "ti,divider-clock"; 19 clocks = <&l3_ick>; 20 ti,max-div = <7>; 21 reg = <0x0b40>; 22 ti,index-starts-at-one; 23 }; 24 25 gfx_l3_ick: gfx_l3_ick { 26 #clock-cells = <0>; 27 compatible = "fixed-factor-clock"; 28 clocks = <&gfx_l3_ck>; 29 clock-mult = <1>; 30 clock-div = <1>; 31 }; 32 33 gfx_cg1_ck: gfx_cg1_ck@b00 { 34 #clock-cells = <0>; 35 compatible = "ti,wait-gate-clock"; 36 clocks = <&gfx_l3_fck>; 37 reg = <0x0b00>; 38 ti,bit-shift = <1>; 39 }; 40 41 gfx_cg2_ck: gfx_cg2_ck@b00 { 42 #clock-cells = <0>; 43 compatible = "ti,wait-gate-clock"; 44 clocks = <&gfx_l3_fck>; 45 reg = <0x0b00>; 46 ti,bit-shift = <2>; 47 }; 48 49 clock@a00 { 50 compatible = "ti,clksel"; 51 reg = <0xa00>; 52 #clock-cells = <2>; 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 d2d_26m_fck: clock-d2d-26m-fck@3 { 57 reg = <3>; 58 #clock-cells = <0>; 59 compatible = "ti,wait-gate-clock"; 60 clock-output-names = "d2d_26m_fck"; 61 clocks = <&sys_ck>; 62 }; 63 64 fshostusb_fck: clock-fshostusb-fck@5 { 65 reg = <5>; 66 #clock-cells = <0>; 67 compatible = "ti,wait-gate-clock"; 68 clock-output-names = "fshostusb_fck"; 69 clocks = <&core_48m_fck>; 70 }; 71 72 ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 { 73 reg = <0>; 74 #clock-cells = <0>; 75 compatible = "ti,composite-no-wait-gate-clock"; 76 clock-output-names = "ssi_ssr_gate_fck_3430es1"; 77 clocks = <&corex2_fck>; 78 }; 79 }; 80 81 clock@a40 { 82 compatible = "ti,clksel"; 83 reg = <0xa40>; 84 #clock-cells = <2>; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 { 89 reg = <8>; 90 #clock-cells = <0>; 91 compatible = "ti,composite-divider-clock"; 92 clock-output-names = "ssi_ssr_div_fck_3430es1"; 93 clocks = <&corex2_fck>; 94 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; 95 }; 96 97 usb_l4_div_ick: clock-usb-l4-div-ick@4 { 98 reg = <4>; 99 #clock-cells = <0>; 100 compatible = "ti,composite-divider-clock"; 101 clock-output-names = "usb_l4_div_ick"; 102 clocks = <&l4_ick>; 103 ti,max-div = <1>; 104 ti,index-starts-at-one; 105 }; 106 }; 107 108 ssi_ssr_fck: ssi_ssr_fck_3430es1 { 109 #clock-cells = <0>; 110 compatible = "ti,composite-clock"; 111 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; 112 }; 113 114 ssi_sst_fck: ssi_sst_fck_3430es1 { 115 #clock-cells = <0>; 116 compatible = "fixed-factor-clock"; 117 clocks = <&ssi_ssr_fck>; 118 clock-mult = <1>; 119 clock-div = <2>; 120 }; 121 122 clock@a10 { 123 compatible = "ti,clksel"; 124 reg = <0xa10>; 125 #clock-cells = <2>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 129 hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 { 130 reg = <4>; 131 #clock-cells = <0>; 132 compatible = "ti,omap3-no-wait-interface-clock"; 133 clock-output-names = "hsotgusb_ick_3430es1"; 134 clocks = <&core_l3_ick>; 135 }; 136 137 fac_ick: clock-fac-ick@8 { 138 reg = <8>; 139 #clock-cells = <0>; 140 compatible = "ti,omap3-interface-clock"; 141 clock-output-names = "fac_ick"; 142 clocks = <&core_l4_ick>; 143 }; 144 145 ssi_ick: clock-ssi-ick-3430es1@0 { 146 reg = <0>; 147 #clock-cells = <0>; 148 compatible = "ti,omap3-no-wait-interface-clock"; 149 clock-output-names = "ssi_ick_3430es1"; 150 clocks = <&ssi_l4_ick>; 151 }; 152 153 usb_l4_gate_ick: clock-usb-l4-gate-ick@5 { 154 reg = <5>; 155 #clock-cells = <0>; 156 compatible = "ti,composite-interface-clock"; 157 clock-output-names = "usb_l4_gate_ick"; 158 clocks = <&l4_ick>; 159 }; 160 }; 161 162 ssi_l4_ick: ssi_l4_ick { 163 #clock-cells = <0>; 164 compatible = "fixed-factor-clock"; 165 clocks = <&l4_ick>; 166 clock-mult = <1>; 167 clock-div = <1>; 168 }; 169 170 usb_l4_ick: usb_l4_ick { 171 #clock-cells = <0>; 172 compatible = "ti,composite-clock"; 173 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; 174 }; 175 176 clock@e00 { 177 compatible = "ti,clksel"; 178 reg = <0xe00>; 179 #clock-cells = <2>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 183 dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 { 184 reg = <0>; 185 #clock-cells = <0>; 186 compatible = "ti,gate-clock"; 187 clock-output-names = "dss1_alwon_fck_3430es1"; 188 clocks = <&dpll4_m4x2_ck>; 189 ti,set-rate-parent; 190 }; 191 }; 192 193 dss_ick: dss_ick_3430es1@e10 { 194 #clock-cells = <0>; 195 compatible = "ti,omap3-no-wait-interface-clock"; 196 clocks = <&l4_ick>; 197 reg = <0x0e10>; 198 ti,bit-shift = <0>; 199 }; 200}; 201 202&cm_clockdomains { 203 core_l3_clkdm: core_l3_clkdm { 204 compatible = "ti,clockdomain"; 205 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; 206 }; 207 208 gfx_3430es1_clkdm: gfx_3430es1_clkdm { 209 compatible = "ti,clockdomain"; 210 clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; 211 }; 212 213 dss_clkdm: dss_clkdm { 214 compatible = "ti,clockdomain"; 215 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, 216 <&dss1_alwon_fck>, <&dss_ick>; 217 }; 218 219 d2d_clkdm: d2d_clkdm { 220 compatible = "ti,clockdomain"; 221 clocks = <&d2d_26m_fck>; 222 }; 223 224 core_l4_clkdm: core_l4_clkdm { 225 compatible = "ti,clockdomain"; 226 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, 227 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, 228 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, 229 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, 230 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, 231 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, 232 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, 233 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, 234 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, 235 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; 236 }; 237}; 238