1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Device Tree Source for DRA7xx clock data 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 */ 7&cm_core_aon_clocks { 8 atl_clkin0_ck: clock-atl-clkin0 { 9 #clock-cells = <0>; 10 compatible = "ti,dra7-atl-clock"; 11 clock-output-names = "atl_clkin0_ck"; 12 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 13 }; 14 15 atl_clkin1_ck: clock-atl-clkin1 { 16 #clock-cells = <0>; 17 compatible = "ti,dra7-atl-clock"; 18 clock-output-names = "atl_clkin1_ck"; 19 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 20 }; 21 22 atl_clkin2_ck: clock-atl-clkin2 { 23 #clock-cells = <0>; 24 compatible = "ti,dra7-atl-clock"; 25 clock-output-names = "atl_clkin2_ck"; 26 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 27 }; 28 29 atl_clkin3_ck: clock-atl-clkin3 { 30 #clock-cells = <0>; 31 compatible = "ti,dra7-atl-clock"; 32 clock-output-names = "atl_clkin3_ck"; 33 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 34 }; 35 36 hdmi_clkin_ck: clock-hdmi-clkin { 37 #clock-cells = <0>; 38 compatible = "fixed-clock"; 39 clock-output-names = "hdmi_clkin_ck"; 40 clock-frequency = <0>; 41 }; 42 43 mlb_clkin_ck: clock-mlb-clkin { 44 #clock-cells = <0>; 45 compatible = "fixed-clock"; 46 clock-output-names = "mlb_clkin_ck"; 47 clock-frequency = <0>; 48 }; 49 50 mlbp_clkin_ck: clock-mlbp-clkin { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-output-names = "mlbp_clkin_ck"; 54 clock-frequency = <0>; 55 }; 56 57 pciesref_acs_clk_ck: clock-pciesref-acs { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-output-names = "pciesref_acs_clk_ck"; 61 clock-frequency = <100000000>; 62 }; 63 64 ref_clkin0_ck: clock-ref-clkin0 { 65 #clock-cells = <0>; 66 compatible = "fixed-clock"; 67 clock-output-names = "ref_clkin0_ck"; 68 clock-frequency = <0>; 69 }; 70 71 ref_clkin1_ck: clock-ref-clkin1 { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-output-names = "ref_clkin1_ck"; 75 clock-frequency = <0>; 76 }; 77 78 ref_clkin2_ck: clock-ref-clkin2 { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-output-names = "ref_clkin2_ck"; 82 clock-frequency = <0>; 83 }; 84 85 ref_clkin3_ck: clock-ref-clkin3 { 86 #clock-cells = <0>; 87 compatible = "fixed-clock"; 88 clock-output-names = "ref_clkin3_ck"; 89 clock-frequency = <0>; 90 }; 91 92 rmii_clk_ck: clock-rmii { 93 #clock-cells = <0>; 94 compatible = "fixed-clock"; 95 clock-output-names = "rmii_clk_ck"; 96 clock-frequency = <0>; 97 }; 98 99 sdvenc_clkin_ck: clock-sdvenc-clkin { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-output-names = "sdvenc_clkin_ck"; 103 clock-frequency = <0>; 104 }; 105 106 secure_32k_clk_src_ck: clock-secure-32k-clk-src { 107 #clock-cells = <0>; 108 compatible = "fixed-clock"; 109 clock-output-names = "secure_32k_clk_src_ck"; 110 clock-frequency = <32768>; 111 }; 112 113 sys_clk32_crystal_ck: clock-sys-clk32-crystal { 114 #clock-cells = <0>; 115 compatible = "fixed-clock"; 116 clock-output-names = "sys_clk32_crystal_ck"; 117 clock-frequency = <32768>; 118 }; 119 120 sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { 121 #clock-cells = <0>; 122 compatible = "fixed-factor-clock"; 123 clock-output-names = "sys_clk32_pseudo_ck"; 124 clocks = <&sys_clkin1>; 125 clock-mult = <1>; 126 clock-div = <610>; 127 }; 128 129 virt_12000000_ck: clock-virt-12000000 { 130 #clock-cells = <0>; 131 compatible = "fixed-clock"; 132 clock-output-names = "virt_12000000_ck"; 133 clock-frequency = <12000000>; 134 }; 135 136 virt_13000000_ck: clock-virt-13000000 { 137 #clock-cells = <0>; 138 compatible = "fixed-clock"; 139 clock-output-names = "virt_13000000_ck"; 140 clock-frequency = <13000000>; 141 }; 142 143 virt_16800000_ck: clock-virt-16800000 { 144 #clock-cells = <0>; 145 compatible = "fixed-clock"; 146 clock-output-names = "virt_16800000_ck"; 147 clock-frequency = <16800000>; 148 }; 149 150 virt_19200000_ck: clock-virt-19200000 { 151 #clock-cells = <0>; 152 compatible = "fixed-clock"; 153 clock-output-names = "virt_19200000_ck"; 154 clock-frequency = <19200000>; 155 }; 156 157 virt_20000000_ck: clock-virt-20000000 { 158 #clock-cells = <0>; 159 compatible = "fixed-clock"; 160 clock-output-names = "virt_20000000_ck"; 161 clock-frequency = <20000000>; 162 }; 163 164 virt_26000000_ck: clock-virt-26000000 { 165 #clock-cells = <0>; 166 compatible = "fixed-clock"; 167 clock-output-names = "virt_26000000_ck"; 168 clock-frequency = <26000000>; 169 }; 170 171 virt_27000000_ck: clock-virt-27000000 { 172 #clock-cells = <0>; 173 compatible = "fixed-clock"; 174 clock-output-names = "virt_27000000_ck"; 175 clock-frequency = <27000000>; 176 }; 177 178 virt_38400000_ck: clock-virt-38400000 { 179 #clock-cells = <0>; 180 compatible = "fixed-clock"; 181 clock-output-names = "virt_38400000_ck"; 182 clock-frequency = <38400000>; 183 }; 184 185 sys_clkin2: clock-sys-clkin2 { 186 #clock-cells = <0>; 187 compatible = "fixed-clock"; 188 clock-output-names = "sys_clkin2"; 189 clock-frequency = <22579200>; 190 }; 191 192 usb_otg_clkin_ck: clock-usb-otg-clkin { 193 #clock-cells = <0>; 194 compatible = "fixed-clock"; 195 clock-output-names = "usb_otg_clkin_ck"; 196 clock-frequency = <0>; 197 }; 198 199 video1_clkin_ck: clock-video1-clkin { 200 #clock-cells = <0>; 201 compatible = "fixed-clock"; 202 clock-output-names = "video1_clkin_ck"; 203 clock-frequency = <0>; 204 }; 205 206 video1_m2_clkin_ck: clock-video1-m2-clkin { 207 #clock-cells = <0>; 208 compatible = "fixed-clock"; 209 clock-output-names = "video1_m2_clkin_ck"; 210 clock-frequency = <0>; 211 }; 212 213 video2_clkin_ck: clock-video2-clkin { 214 #clock-cells = <0>; 215 compatible = "fixed-clock"; 216 clock-output-names = "video2_clkin_ck"; 217 clock-frequency = <0>; 218 }; 219 220 video2_m2_clkin_ck: clock-video2-m2-clkin { 221 #clock-cells = <0>; 222 compatible = "fixed-clock"; 223 clock-output-names = "video2_m2_clkin_ck"; 224 clock-frequency = <0>; 225 }; 226 227 dpll_abe_ck: clock@1e0 { 228 #clock-cells = <0>; 229 compatible = "ti,omap4-dpll-m4xen-clock"; 230 clock-output-names = "dpll_abe_ck"; 231 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; 232 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 233 }; 234 235 dpll_abe_x2_ck: clock-dpll-abe-x2 { 236 #clock-cells = <0>; 237 compatible = "ti,omap4-dpll-x2-clock"; 238 clock-output-names = "dpll_abe_x2_ck"; 239 clocks = <&dpll_abe_ck>; 240 }; 241 242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { 243 #clock-cells = <0>; 244 compatible = "ti,divider-clock"; 245 clock-output-names = "dpll_abe_m2x2_ck"; 246 clocks = <&dpll_abe_x2_ck>; 247 ti,max-div = <31>; 248 ti,autoidle-shift = <8>; 249 reg = <0x01f0>; 250 ti,index-starts-at-one; 251 ti,invert-autoidle-bit; 252 }; 253 254 abe_clk: clock-abe@108 { 255 #clock-cells = <0>; 256 compatible = "ti,divider-clock"; 257 clock-output-names = "abe_clk"; 258 clocks = <&dpll_abe_m2x2_ck>; 259 ti,max-div = <4>; 260 reg = <0x0108>; 261 ti,index-power-of-two; 262 }; 263 264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { 265 #clock-cells = <0>; 266 compatible = "ti,divider-clock"; 267 clock-output-names = "dpll_abe_m2_ck"; 268 clocks = <&dpll_abe_ck>; 269 ti,max-div = <31>; 270 ti,autoidle-shift = <8>; 271 reg = <0x01f0>; 272 ti,index-starts-at-one; 273 ti,invert-autoidle-bit; 274 }; 275 276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { 277 #clock-cells = <0>; 278 compatible = "ti,divider-clock"; 279 clock-output-names = "dpll_abe_m3x2_ck"; 280 clocks = <&dpll_abe_x2_ck>; 281 ti,max-div = <31>; 282 ti,autoidle-shift = <8>; 283 reg = <0x01f4>; 284 ti,index-starts-at-one; 285 ti,invert-autoidle-bit; 286 }; 287 288 /* CM_CLKSEL_DPLL_CORE */ 289 clock@12c { 290 compatible = "ti,clksel"; 291 reg = <0x12c>; 292 #clock-cells = <2>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 296 dpll_core_byp_mux: clock@23 { 297 reg = <23>; 298 compatible = "ti,mux-clock"; 299 clock-output-names = "dpll_core_byp_mux"; 300 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 301 #clock-cells = <0>; 302 }; 303 }; 304 305 dpll_core_ck: clock@120 { 306 #clock-cells = <0>; 307 compatible = "ti,omap4-dpll-core-clock"; 308 clock-output-names = "dpll_core_ck"; 309 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; 310 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 311 }; 312 313 dpll_core_x2_ck: clock-dpll-core-x2 { 314 #clock-cells = <0>; 315 compatible = "ti,omap4-dpll-x2-clock"; 316 clock-output-names = "dpll_core_x2_ck"; 317 clocks = <&dpll_core_ck>; 318 }; 319 320 dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { 321 #clock-cells = <0>; 322 compatible = "ti,divider-clock"; 323 clock-output-names = "dpll_core_h12x2_ck"; 324 clocks = <&dpll_core_x2_ck>; 325 ti,max-div = <63>; 326 ti,autoidle-shift = <8>; 327 reg = <0x013c>; 328 ti,index-starts-at-one; 329 ti,invert-autoidle-bit; 330 }; 331 332 mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { 333 #clock-cells = <0>; 334 compatible = "fixed-factor-clock"; 335 clock-output-names = "mpu_dpll_hs_clk_div"; 336 clocks = <&dpll_core_h12x2_ck>; 337 clock-mult = <1>; 338 clock-div = <1>; 339 }; 340 341 dpll_mpu_ck: clock@160 { 342 #clock-cells = <0>; 343 compatible = "ti,omap5-mpu-dpll-clock"; 344 clock-output-names = "dpll_mpu_ck"; 345 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; 346 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; 347 }; 348 349 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { 350 #clock-cells = <0>; 351 compatible = "ti,divider-clock"; 352 clock-output-names = "dpll_mpu_m2_ck"; 353 clocks = <&dpll_mpu_ck>; 354 ti,max-div = <31>; 355 ti,autoidle-shift = <8>; 356 reg = <0x0170>; 357 ti,index-starts-at-one; 358 ti,invert-autoidle-bit; 359 }; 360 361 mpu_dclk_div: clock-mpu-dclk-div { 362 #clock-cells = <0>; 363 compatible = "fixed-factor-clock"; 364 clock-output-names = "mpu_dclk_div"; 365 clocks = <&dpll_mpu_m2_ck>; 366 clock-mult = <1>; 367 clock-div = <1>; 368 }; 369 370 dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { 371 #clock-cells = <0>; 372 compatible = "fixed-factor-clock"; 373 clock-output-names = "dsp_dpll_hs_clk_div"; 374 clocks = <&dpll_core_h12x2_ck>; 375 clock-mult = <1>; 376 clock-div = <1>; 377 }; 378 379 /* CM_CLKSEL_DPLL_DSP */ 380 clock@240 { 381 compatible = "ti,clksel"; 382 reg = <0x240>; 383 #clock-cells = <2>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 387 dpll_dsp_byp_mux: clock@23 { 388 reg = <23>; 389 compatible = "ti,mux-clock"; 390 clock-output-names = "dpll_dsp_byp_mux"; 391 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; 392 #clock-cells = <0>; 393 }; 394 }; 395 396 dpll_dsp_ck: clock@234 { 397 #clock-cells = <0>; 398 compatible = "ti,omap4-dpll-clock"; 399 clock-output-names = "dpll_dsp_ck"; 400 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; 401 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; 402 assigned-clocks = <&dpll_dsp_ck>; 403 assigned-clock-rates = <600000000>; 404 }; 405 406 dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { 407 #clock-cells = <0>; 408 compatible = "ti,divider-clock"; 409 clock-output-names = "dpll_dsp_m2_ck"; 410 clocks = <&dpll_dsp_ck>; 411 ti,max-div = <31>; 412 ti,autoidle-shift = <8>; 413 reg = <0x0244>; 414 ti,index-starts-at-one; 415 ti,invert-autoidle-bit; 416 assigned-clocks = <&dpll_dsp_m2_ck>; 417 assigned-clock-rates = <600000000>; 418 }; 419 420 iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { 421 #clock-cells = <0>; 422 compatible = "fixed-factor-clock"; 423 clock-output-names = "iva_dpll_hs_clk_div"; 424 clocks = <&dpll_core_h12x2_ck>; 425 clock-mult = <1>; 426 clock-div = <1>; 427 }; 428 429 /* CM_CLKSEL_DPLL_IVA */ 430 clock@1ac { 431 compatible = "ti,clksel"; 432 reg = <0x1ac>; 433 #clock-cells = <2>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 437 dpll_iva_byp_mux: clock@23 { 438 reg = <23>; 439 compatible = "ti,mux-clock"; 440 clock-output-names = "dpll_iva_byp_mux"; 441 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; 442 #clock-cells = <0>; 443 }; 444 }; 445 446 dpll_iva_ck: clock@1a0 { 447 #clock-cells = <0>; 448 compatible = "ti,omap4-dpll-clock"; 449 clock-output-names = "dpll_iva_ck"; 450 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; 451 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 452 assigned-clocks = <&dpll_iva_ck>; 453 assigned-clock-rates = <1165000000>; 454 }; 455 456 dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { 457 #clock-cells = <0>; 458 compatible = "ti,divider-clock"; 459 clock-output-names = "dpll_iva_m2_ck"; 460 clocks = <&dpll_iva_ck>; 461 ti,max-div = <31>; 462 ti,autoidle-shift = <8>; 463 reg = <0x01b0>; 464 ti,index-starts-at-one; 465 ti,invert-autoidle-bit; 466 assigned-clocks = <&dpll_iva_m2_ck>; 467 assigned-clock-rates = <388333334>; 468 }; 469 470 iva_dclk: clock-iva-dclk { 471 #clock-cells = <0>; 472 compatible = "fixed-factor-clock"; 473 clock-output-names = "iva_dclk"; 474 clocks = <&dpll_iva_m2_ck>; 475 clock-mult = <1>; 476 clock-div = <1>; 477 }; 478 479 /* CM_CLKSEL_DPLL_GPU */ 480 clock@2e4 { 481 compatible = "ti,clksel"; 482 reg = <0x2e4>; 483 #clock-cells = <2>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 487 dpll_gpu_byp_mux: clock@23 { 488 reg = <23>; 489 compatible = "ti,mux-clock"; 490 clock-output-names = "dpll_gpu_byp_mux"; 491 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 492 #clock-cells = <0>; 493 }; 494 }; 495 496 dpll_gpu_ck: clock@2d8 { 497 #clock-cells = <0>; 498 compatible = "ti,omap4-dpll-clock"; 499 clock-output-names = "dpll_gpu_ck"; 500 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; 501 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; 502 assigned-clocks = <&dpll_gpu_ck>; 503 assigned-clock-rates = <1277000000>; 504 }; 505 506 dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { 507 #clock-cells = <0>; 508 compatible = "ti,divider-clock"; 509 clock-output-names = "dpll_gpu_m2_ck"; 510 clocks = <&dpll_gpu_ck>; 511 ti,max-div = <31>; 512 ti,autoidle-shift = <8>; 513 reg = <0x02e8>; 514 ti,index-starts-at-one; 515 ti,invert-autoidle-bit; 516 assigned-clocks = <&dpll_gpu_m2_ck>; 517 assigned-clock-rates = <425666667>; 518 }; 519 520 dpll_core_m2_ck: clock-dpll-core-m2-8@130 { 521 #clock-cells = <0>; 522 compatible = "ti,divider-clock"; 523 clock-output-names = "dpll_core_m2_ck"; 524 clocks = <&dpll_core_ck>; 525 ti,max-div = <31>; 526 ti,autoidle-shift = <8>; 527 reg = <0x0130>; 528 ti,index-starts-at-one; 529 ti,invert-autoidle-bit; 530 }; 531 532 core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { 533 #clock-cells = <0>; 534 compatible = "fixed-factor-clock"; 535 clock-output-names = "core_dpll_out_dclk_div"; 536 clocks = <&dpll_core_m2_ck>; 537 clock-mult = <1>; 538 clock-div = <1>; 539 }; 540 541 /* CM_CLKSEL_DPLL_DDR */ 542 clock@21c { 543 compatible = "ti,clksel"; 544 reg = <0x21c>; 545 #clock-cells = <2>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 dpll_ddr_byp_mux: clock@23 { 550 reg = <23>; 551 compatible = "ti,mux-clock"; 552 clock-output-names = "dpll_ddr_byp_mux"; 553 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 554 #clock-cells = <0>; 555 }; 556 }; 557 558 dpll_ddr_ck: clock@210 { 559 #clock-cells = <0>; 560 compatible = "ti,omap4-dpll-clock"; 561 clock-output-names = "dpll_ddr_ck"; 562 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; 563 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; 564 }; 565 566 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { 567 #clock-cells = <0>; 568 compatible = "ti,divider-clock"; 569 clock-output-names = "dpll_ddr_m2_ck"; 570 clocks = <&dpll_ddr_ck>; 571 ti,max-div = <31>; 572 ti,autoidle-shift = <8>; 573 reg = <0x0220>; 574 ti,index-starts-at-one; 575 ti,invert-autoidle-bit; 576 }; 577 578 /* CM_CLKSEL_DPLL_GMAC */ 579 clock@2b4 { 580 compatible = "ti,clksel"; 581 reg = <0x2b4>; 582 #clock-cells = <2>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 586 dpll_gmac_byp_mux: clock@23 { 587 reg = <23>; 588 compatible = "ti,mux-clock"; 589 clock-output-names = "dpll_gmac_byp_mux"; 590 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 591 #clock-cells = <0>; 592 }; 593 }; 594 595 dpll_gmac_ck: clock@2a8 { 596 #clock-cells = <0>; 597 compatible = "ti,omap4-dpll-clock"; 598 clock-output-names = "dpll_gmac_ck"; 599 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; 600 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; 601 }; 602 603 dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { 604 #clock-cells = <0>; 605 compatible = "ti,divider-clock"; 606 clock-output-names = "dpll_gmac_m2_ck"; 607 clocks = <&dpll_gmac_ck>; 608 ti,max-div = <31>; 609 ti,autoidle-shift = <8>; 610 reg = <0x02b8>; 611 ti,index-starts-at-one; 612 ti,invert-autoidle-bit; 613 }; 614 615 video2_dclk_div: clock-video2-dclk-div { 616 #clock-cells = <0>; 617 compatible = "fixed-factor-clock"; 618 clock-output-names = "video2_dclk_div"; 619 clocks = <&video2_m2_clkin_ck>; 620 clock-mult = <1>; 621 clock-div = <1>; 622 }; 623 624 video1_dclk_div: clock-video1-dclk-div { 625 #clock-cells = <0>; 626 compatible = "fixed-factor-clock"; 627 clock-output-names = "video1_dclk_div"; 628 clocks = <&video1_m2_clkin_ck>; 629 clock-mult = <1>; 630 clock-div = <1>; 631 }; 632 633 hdmi_dclk_div: clock-hdmi-dclk-div { 634 #clock-cells = <0>; 635 compatible = "fixed-factor-clock"; 636 clock-output-names = "hdmi_dclk_div"; 637 clocks = <&hdmi_clkin_ck>; 638 clock-mult = <1>; 639 clock-div = <1>; 640 }; 641 642 per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { 643 #clock-cells = <0>; 644 compatible = "fixed-factor-clock"; 645 clock-output-names = "per_dpll_hs_clk_div"; 646 clocks = <&dpll_abe_m3x2_ck>; 647 clock-mult = <1>; 648 clock-div = <2>; 649 }; 650 651 usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { 652 #clock-cells = <0>; 653 compatible = "fixed-factor-clock"; 654 clock-output-names = "usb_dpll_hs_clk_div"; 655 clocks = <&dpll_abe_m3x2_ck>; 656 clock-mult = <1>; 657 clock-div = <3>; 658 }; 659 660 eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { 661 #clock-cells = <0>; 662 compatible = "fixed-factor-clock"; 663 clock-output-names = "eve_dpll_hs_clk_div"; 664 clocks = <&dpll_core_h12x2_ck>; 665 clock-mult = <1>; 666 clock-div = <1>; 667 }; 668 669 /* CM_CLKSEL_DPLL_EVE */ 670 clock@290 { 671 compatible = "ti,clksel"; 672 reg = <0x290>; 673 #clock-cells = <2>; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 677 dpll_eve_byp_mux: clock@23 { 678 reg = <23>; 679 compatible = "ti,mux-clock"; 680 clock-output-names = "dpll_eve_byp_mux"; 681 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; 682 #clock-cells = <0>; 683 }; 684 }; 685 686 dpll_eve_ck: clock@284 { 687 #clock-cells = <0>; 688 compatible = "ti,omap4-dpll-clock"; 689 clock-output-names = "dpll_eve_ck"; 690 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; 691 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; 692 }; 693 694 dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { 695 #clock-cells = <0>; 696 compatible = "ti,divider-clock"; 697 clock-output-names = "dpll_eve_m2_ck"; 698 clocks = <&dpll_eve_ck>; 699 ti,max-div = <31>; 700 ti,autoidle-shift = <8>; 701 reg = <0x0294>; 702 ti,index-starts-at-one; 703 ti,invert-autoidle-bit; 704 }; 705 706 eve_dclk_div: clock-eve-dclk-div { 707 #clock-cells = <0>; 708 compatible = "fixed-factor-clock"; 709 clock-output-names = "eve_dclk_div"; 710 clocks = <&dpll_eve_m2_ck>; 711 clock-mult = <1>; 712 clock-div = <1>; 713 }; 714 715 dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { 716 #clock-cells = <0>; 717 compatible = "ti,divider-clock"; 718 clock-output-names = "dpll_core_h13x2_ck"; 719 clocks = <&dpll_core_x2_ck>; 720 ti,max-div = <63>; 721 ti,autoidle-shift = <8>; 722 reg = <0x0140>; 723 ti,index-starts-at-one; 724 ti,invert-autoidle-bit; 725 }; 726 727 dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { 728 #clock-cells = <0>; 729 compatible = "ti,divider-clock"; 730 clock-output-names = "dpll_core_h14x2_ck"; 731 clocks = <&dpll_core_x2_ck>; 732 ti,max-div = <63>; 733 ti,autoidle-shift = <8>; 734 reg = <0x0144>; 735 ti,index-starts-at-one; 736 ti,invert-autoidle-bit; 737 }; 738 739 dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { 740 #clock-cells = <0>; 741 compatible = "ti,divider-clock"; 742 clock-output-names = "dpll_core_h22x2_ck"; 743 clocks = <&dpll_core_x2_ck>; 744 ti,max-div = <63>; 745 ti,autoidle-shift = <8>; 746 reg = <0x0154>; 747 ti,index-starts-at-one; 748 ti,invert-autoidle-bit; 749 }; 750 751 dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { 752 #clock-cells = <0>; 753 compatible = "ti,divider-clock"; 754 clock-output-names = "dpll_core_h23x2_ck"; 755 clocks = <&dpll_core_x2_ck>; 756 ti,max-div = <63>; 757 ti,autoidle-shift = <8>; 758 reg = <0x0158>; 759 ti,index-starts-at-one; 760 ti,invert-autoidle-bit; 761 }; 762 763 dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { 764 #clock-cells = <0>; 765 compatible = "ti,divider-clock"; 766 clock-output-names = "dpll_core_h24x2_ck"; 767 clocks = <&dpll_core_x2_ck>; 768 ti,max-div = <63>; 769 ti,autoidle-shift = <8>; 770 reg = <0x015c>; 771 ti,index-starts-at-one; 772 ti,invert-autoidle-bit; 773 }; 774 775 dpll_ddr_x2_ck: clock-dpll-ddr-x2 { 776 #clock-cells = <0>; 777 compatible = "ti,omap4-dpll-x2-clock"; 778 clock-output-names = "dpll_ddr_x2_ck"; 779 clocks = <&dpll_ddr_ck>; 780 }; 781 782 dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { 783 #clock-cells = <0>; 784 compatible = "ti,divider-clock"; 785 clock-output-names = "dpll_ddr_h11x2_ck"; 786 clocks = <&dpll_ddr_x2_ck>; 787 ti,max-div = <63>; 788 ti,autoidle-shift = <8>; 789 reg = <0x0228>; 790 ti,index-starts-at-one; 791 ti,invert-autoidle-bit; 792 }; 793 794 dpll_dsp_x2_ck: clock-dpll-dsp-x2 { 795 #clock-cells = <0>; 796 compatible = "ti,omap4-dpll-x2-clock"; 797 clock-output-names = "dpll_dsp_x2_ck"; 798 clocks = <&dpll_dsp_ck>; 799 }; 800 801 dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { 802 #clock-cells = <0>; 803 compatible = "ti,divider-clock"; 804 clock-output-names = "dpll_dsp_m3x2_ck"; 805 clocks = <&dpll_dsp_x2_ck>; 806 ti,max-div = <31>; 807 ti,autoidle-shift = <8>; 808 reg = <0x0248>; 809 ti,index-starts-at-one; 810 ti,invert-autoidle-bit; 811 assigned-clocks = <&dpll_dsp_m3x2_ck>; 812 assigned-clock-rates = <400000000>; 813 }; 814 815 dpll_gmac_x2_ck: clock-dpll-gmac-x2 { 816 #clock-cells = <0>; 817 compatible = "ti,omap4-dpll-x2-clock"; 818 clock-output-names = "dpll_gmac_x2_ck"; 819 clocks = <&dpll_gmac_ck>; 820 }; 821 822 dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { 823 #clock-cells = <0>; 824 compatible = "ti,divider-clock"; 825 clock-output-names = "dpll_gmac_h11x2_ck"; 826 clocks = <&dpll_gmac_x2_ck>; 827 ti,max-div = <63>; 828 ti,autoidle-shift = <8>; 829 reg = <0x02c0>; 830 ti,index-starts-at-one; 831 ti,invert-autoidle-bit; 832 }; 833 834 dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { 835 #clock-cells = <0>; 836 compatible = "ti,divider-clock"; 837 clock-output-names = "dpll_gmac_h12x2_ck"; 838 clocks = <&dpll_gmac_x2_ck>; 839 ti,max-div = <63>; 840 ti,autoidle-shift = <8>; 841 reg = <0x02c4>; 842 ti,index-starts-at-one; 843 ti,invert-autoidle-bit; 844 }; 845 846 dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { 847 #clock-cells = <0>; 848 compatible = "ti,divider-clock"; 849 clock-output-names = "dpll_gmac_h13x2_ck"; 850 clocks = <&dpll_gmac_x2_ck>; 851 ti,max-div = <63>; 852 ti,autoidle-shift = <8>; 853 reg = <0x02c8>; 854 ti,index-starts-at-one; 855 ti,invert-autoidle-bit; 856 }; 857 858 dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { 859 #clock-cells = <0>; 860 compatible = "ti,divider-clock"; 861 clock-output-names = "dpll_gmac_m3x2_ck"; 862 clocks = <&dpll_gmac_x2_ck>; 863 ti,max-div = <31>; 864 ti,autoidle-shift = <8>; 865 reg = <0x02bc>; 866 ti,index-starts-at-one; 867 ti,invert-autoidle-bit; 868 }; 869 870 gmii_m_clk_div: clock-gmii-m-clk-div { 871 #clock-cells = <0>; 872 compatible = "fixed-factor-clock"; 873 clock-output-names = "gmii_m_clk_div"; 874 clocks = <&dpll_gmac_h11x2_ck>; 875 clock-mult = <1>; 876 clock-div = <2>; 877 }; 878 879 hdmi_clk2_div: clock-hdmi-clk2-div { 880 #clock-cells = <0>; 881 compatible = "fixed-factor-clock"; 882 clock-output-names = "hdmi_clk2_div"; 883 clocks = <&hdmi_clkin_ck>; 884 clock-mult = <1>; 885 clock-div = <1>; 886 }; 887 888 hdmi_div_clk: clock-hdmi-div { 889 #clock-cells = <0>; 890 compatible = "fixed-factor-clock"; 891 clock-output-names = "hdmi_div_clk"; 892 clocks = <&hdmi_clkin_ck>; 893 clock-mult = <1>; 894 clock-div = <1>; 895 }; 896 897 /* CM_CLKSEL_CORE */ 898 clock@100 { 899 compatible = "ti,clksel"; 900 reg = <0x100>; 901 #clock-cells = <2>; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 905 l3_iclk_div: clock@4 { 906 reg = <4>; 907 compatible = "ti,divider-clock"; 908 clock-output-names = "l3_iclk_div"; 909 ti,max-div = <2>; 910 clocks = <&dpll_core_h12x2_ck>; 911 ti,index-power-of-two; 912 #clock-cells = <0>; 913 }; 914 }; 915 916 l4_root_clk_div: clock-l4-root-clk-div { 917 #clock-cells = <0>; 918 compatible = "fixed-factor-clock"; 919 clock-output-names = "l4_root_clk_div"; 920 clocks = <&l3_iclk_div>; 921 clock-mult = <1>; 922 clock-div = <2>; 923 }; 924 925 video1_clk2_div: clock-video1-clk2-div { 926 #clock-cells = <0>; 927 compatible = "fixed-factor-clock"; 928 clock-output-names = "video1_clk2_div"; 929 clocks = <&video1_clkin_ck>; 930 clock-mult = <1>; 931 clock-div = <1>; 932 }; 933 934 video1_div_clk: clock-video1-div { 935 #clock-cells = <0>; 936 compatible = "fixed-factor-clock"; 937 clock-output-names = "video1_div_clk"; 938 clocks = <&video1_clkin_ck>; 939 clock-mult = <1>; 940 clock-div = <1>; 941 }; 942 943 video2_clk2_div: clock-video2-clk2-div { 944 #clock-cells = <0>; 945 compatible = "fixed-factor-clock"; 946 clock-output-names = "video2_clk2_div"; 947 clocks = <&video2_clkin_ck>; 948 clock-mult = <1>; 949 clock-div = <1>; 950 }; 951 952 video2_div_clk: clock-video2-div { 953 #clock-cells = <0>; 954 compatible = "fixed-factor-clock"; 955 clock-output-names = "video2_div_clk"; 956 clocks = <&video2_clkin_ck>; 957 clock-mult = <1>; 958 clock-div = <1>; 959 }; 960 961 dummy_ck: clock-dummy { 962 #clock-cells = <0>; 963 compatible = "fixed-clock"; 964 clock-output-names = "dummy_ck"; 965 clock-frequency = <0>; 966 }; 967}; 968&prm_clocks { 969 sys_clkin1: clock-sys-clkin1@110 { 970 #clock-cells = <0>; 971 compatible = "ti,mux-clock"; 972 clock-output-names = "sys_clkin1"; 973 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; 974 reg = <0x0110>; 975 ti,index-starts-at-one; 976 }; 977 978 /* CM_CLKSEL_ABE_PLL_SYS */ 979 clock@118 { 980 compatible = "ti,clksel"; 981 reg = <0x118>; 982 #clock-cells = <2>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 986 abe_dpll_sys_clk_mux: clock@0 { 987 reg = <0>; 988 compatible = "ti,mux-clock"; 989 clock-output-names = "abe_dpll_sys_clk_mux"; 990 clocks = <&sys_clkin1>, <&sys_clkin2>; 991 #clock-cells = <0>; 992 }; 993 }; 994 995 abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { 996 #clock-cells = <0>; 997 compatible = "ti,mux-clock"; 998 clock-output-names = "abe_dpll_bypass_clk_mux"; 999 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; 1000 reg = <0x0114>; 1001 }; 1002 1003 abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { 1004 #clock-cells = <0>; 1005 compatible = "ti,mux-clock"; 1006 clock-output-names = "abe_dpll_clk_mux"; 1007 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; 1008 reg = <0x010c>; 1009 }; 1010 1011 abe_24m_fclk: clock-abe-24m@11c { 1012 #clock-cells = <0>; 1013 compatible = "ti,divider-clock"; 1014 clock-output-names = "abe_24m_fclk"; 1015 clocks = <&dpll_abe_m2x2_ck>; 1016 reg = <0x011c>; 1017 ti,dividers = <8>, <16>; 1018 }; 1019 1020 aess_fclk: clock-aess@178 { 1021 #clock-cells = <0>; 1022 compatible = "ti,divider-clock"; 1023 clock-output-names = "aess_fclk"; 1024 clocks = <&abe_clk>; 1025 reg = <0x0178>; 1026 ti,max-div = <2>; 1027 }; 1028 1029 abe_giclk_div: clock-abe-giclk-div@174 { 1030 #clock-cells = <0>; 1031 compatible = "ti,divider-clock"; 1032 clock-output-names = "abe_giclk_div"; 1033 clocks = <&aess_fclk>; 1034 reg = <0x0174>; 1035 ti,max-div = <2>; 1036 }; 1037 1038 abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { 1039 #clock-cells = <0>; 1040 compatible = "ti,divider-clock"; 1041 clock-output-names = "abe_lp_clk_div"; 1042 clocks = <&dpll_abe_m2x2_ck>; 1043 reg = <0x01d8>; 1044 ti,dividers = <16>, <32>; 1045 }; 1046 1047 abe_sys_clk_div: clock-abe-sys-clk-div@120 { 1048 #clock-cells = <0>; 1049 compatible = "ti,divider-clock"; 1050 clock-output-names = "abe_sys_clk_div"; 1051 clocks = <&sys_clkin1>; 1052 reg = <0x0120>; 1053 ti,max-div = <2>; 1054 }; 1055 1056 adc_gfclk_mux: clock-adc-gfclk-mux@1dc { 1057 #clock-cells = <0>; 1058 compatible = "ti,mux-clock"; 1059 clock-output-names = "adc_gfclk_mux"; 1060 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; 1061 reg = <0x01dc>; 1062 }; 1063 1064 sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { 1065 #clock-cells = <0>; 1066 compatible = "ti,divider-clock"; 1067 clock-output-names = "sys_clk1_dclk_div"; 1068 clocks = <&sys_clkin1>; 1069 ti,max-div = <64>; 1070 reg = <0x01c8>; 1071 ti,index-power-of-two; 1072 }; 1073 1074 sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { 1075 #clock-cells = <0>; 1076 compatible = "ti,divider-clock"; 1077 clock-output-names = "sys_clk2_dclk_div"; 1078 clocks = <&sys_clkin2>; 1079 ti,max-div = <64>; 1080 reg = <0x01cc>; 1081 ti,index-power-of-two; 1082 }; 1083 1084 per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { 1085 #clock-cells = <0>; 1086 compatible = "ti,divider-clock"; 1087 clock-output-names = "per_abe_x1_dclk_div"; 1088 clocks = <&dpll_abe_m2_ck>; 1089 ti,max-div = <64>; 1090 reg = <0x01bc>; 1091 ti,index-power-of-two; 1092 }; 1093 1094 /* CM_CLKSEL_DPLL_USB */ 1095 clock@18c { 1096 compatible = "ti,clksel"; 1097 reg = <0x18c>; 1098 #clock-cells = <2>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 1102 dsp_gclk_div: clock@0 { 1103 reg = <0>; 1104 compatible = "ti,divider-clock"; 1105 clock-output-names = "dsp_gclk_div"; 1106 clocks = <&dpll_dsp_m2_ck>; 1107 ti,max-div = <64>; 1108 ti,index-power-of-two; 1109 #clock-cells = <0>; 1110 }; 1111 }; 1112 1113 gpu_dclk: clock-gpu-dclk@1a0 { 1114 #clock-cells = <0>; 1115 compatible = "ti,divider-clock"; 1116 clock-output-names = "gpu_dclk"; 1117 clocks = <&dpll_gpu_m2_ck>; 1118 ti,max-div = <64>; 1119 reg = <0x01a0>; 1120 ti,index-power-of-two; 1121 }; 1122 1123 emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { 1124 #clock-cells = <0>; 1125 compatible = "ti,divider-clock"; 1126 clock-output-names = "emif_phy_dclk_div"; 1127 clocks = <&dpll_ddr_m2_ck>; 1128 ti,max-div = <64>; 1129 reg = <0x0190>; 1130 ti,index-power-of-two; 1131 }; 1132 1133 gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { 1134 #clock-cells = <0>; 1135 compatible = "ti,divider-clock"; 1136 clock-output-names = "gmac_250m_dclk_div"; 1137 clocks = <&dpll_gmac_m2_ck>; 1138 ti,max-div = <64>; 1139 reg = <0x019c>; 1140 ti,index-power-of-two; 1141 }; 1142 1143 gmac_main_clk: clock-gmac-main { 1144 #clock-cells = <0>; 1145 compatible = "fixed-factor-clock"; 1146 clock-output-names = "gmac_main_clk"; 1147 clocks = <&gmac_250m_dclk_div>; 1148 clock-mult = <1>; 1149 clock-div = <2>; 1150 }; 1151 1152 l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { 1153 #clock-cells = <0>; 1154 compatible = "ti,divider-clock"; 1155 clock-output-names = "l3init_480m_dclk_div"; 1156 clocks = <&dpll_usb_m2_ck>; 1157 ti,max-div = <64>; 1158 reg = <0x01ac>; 1159 ti,index-power-of-two; 1160 }; 1161 1162 usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { 1163 #clock-cells = <0>; 1164 compatible = "ti,divider-clock"; 1165 clock-output-names = "usb_otg_dclk_div"; 1166 clocks = <&usb_otg_clkin_ck>; 1167 ti,max-div = <64>; 1168 reg = <0x0184>; 1169 ti,index-power-of-two; 1170 }; 1171 1172 sata_dclk_div: clock-sata-dclk-div@1c0 { 1173 #clock-cells = <0>; 1174 compatible = "ti,divider-clock"; 1175 clock-output-names = "sata_dclk_div"; 1176 clocks = <&sys_clkin1>; 1177 ti,max-div = <64>; 1178 reg = <0x01c0>; 1179 ti,index-power-of-two; 1180 }; 1181 1182 pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { 1183 #clock-cells = <0>; 1184 compatible = "ti,divider-clock"; 1185 clock-output-names = "pcie2_dclk_div"; 1186 clocks = <&dpll_pcie_ref_m2_ck>; 1187 ti,max-div = <64>; 1188 reg = <0x01b8>; 1189 ti,index-power-of-two; 1190 }; 1191 1192 pcie_dclk_div: clock-pcie-dclk-div@1b4 { 1193 #clock-cells = <0>; 1194 compatible = "ti,divider-clock"; 1195 clock-output-names = "pcie_dclk_div"; 1196 clocks = <&apll_pcie_m2_ck>; 1197 ti,max-div = <64>; 1198 reg = <0x01b4>; 1199 ti,index-power-of-two; 1200 }; 1201 1202 emu_dclk_div: clock-emu-dclk-div@194 { 1203 #clock-cells = <0>; 1204 compatible = "ti,divider-clock"; 1205 clock-output-names = "emu_dclk_div"; 1206 clocks = <&sys_clkin1>; 1207 ti,max-div = <64>; 1208 reg = <0x0194>; 1209 ti,index-power-of-two; 1210 }; 1211 1212 secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { 1213 #clock-cells = <0>; 1214 compatible = "ti,divider-clock"; 1215 clock-output-names = "secure_32k_dclk_div"; 1216 clocks = <&secure_32k_clk_src_ck>; 1217 ti,max-div = <64>; 1218 reg = <0x01c4>; 1219 ti,index-power-of-two; 1220 }; 1221 1222 clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { 1223 #clock-cells = <0>; 1224 compatible = "ti,mux-clock"; 1225 clock-output-names = "clkoutmux0_clk_mux"; 1226 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; 1227 reg = <0x0158>; 1228 }; 1229 1230 clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { 1231 #clock-cells = <0>; 1232 compatible = "ti,mux-clock"; 1233 clock-output-names = "clkoutmux1_clk_mux"; 1234 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; 1235 reg = <0x015c>; 1236 }; 1237 1238 clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { 1239 #clock-cells = <0>; 1240 compatible = "ti,mux-clock"; 1241 clock-output-names = "clkoutmux2_clk_mux"; 1242 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; 1243 reg = <0x0160>; 1244 }; 1245 1246 custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { 1247 #clock-cells = <0>; 1248 compatible = "fixed-factor-clock"; 1249 clock-output-names = "custefuse_sys_gfclk_div"; 1250 clocks = <&sys_clkin1>; 1251 clock-mult = <1>; 1252 clock-div = <2>; 1253 }; 1254 1255 eve_clk: clock-eve@180 { 1256 #clock-cells = <0>; 1257 compatible = "ti,mux-clock"; 1258 clock-output-names = "eve_clk"; 1259 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; 1260 reg = <0x0180>; 1261 }; 1262 1263 hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { 1264 #clock-cells = <0>; 1265 compatible = "ti,mux-clock"; 1266 clock-output-names = "hdmi_dpll_clk_mux"; 1267 clocks = <&sys_clkin1>, <&sys_clkin2>; 1268 reg = <0x0164>; 1269 }; 1270 1271 mlb_clk: clock-mlb@134 { 1272 #clock-cells = <0>; 1273 compatible = "ti,divider-clock"; 1274 clock-output-names = "mlb_clk"; 1275 clocks = <&mlb_clkin_ck>; 1276 ti,max-div = <64>; 1277 reg = <0x0134>; 1278 ti,index-power-of-two; 1279 }; 1280 1281 mlbp_clk: clock-mlbp@130 { 1282 #clock-cells = <0>; 1283 compatible = "ti,divider-clock"; 1284 clock-output-names = "mlbp_clk"; 1285 clocks = <&mlbp_clkin_ck>; 1286 ti,max-div = <64>; 1287 reg = <0x0130>; 1288 ti,index-power-of-two; 1289 }; 1290 1291 per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { 1292 #clock-cells = <0>; 1293 compatible = "ti,divider-clock"; 1294 clock-output-names = "per_abe_x1_gfclk2_div"; 1295 clocks = <&dpll_abe_m2_ck>; 1296 ti,max-div = <64>; 1297 reg = <0x0138>; 1298 ti,index-power-of-two; 1299 }; 1300 1301 timer_sys_clk_div: clock-timer-sys-clk-div@144 { 1302 #clock-cells = <0>; 1303 compatible = "ti,divider-clock"; 1304 clock-output-names = "timer_sys_clk_div"; 1305 clocks = <&sys_clkin1>; 1306 reg = <0x0144>; 1307 ti,max-div = <2>; 1308 }; 1309 1310 video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { 1311 #clock-cells = <0>; 1312 compatible = "ti,mux-clock"; 1313 clock-output-names = "video1_dpll_clk_mux"; 1314 clocks = <&sys_clkin1>, <&sys_clkin2>; 1315 reg = <0x0168>; 1316 }; 1317 1318 video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { 1319 #clock-cells = <0>; 1320 compatible = "ti,mux-clock"; 1321 clock-output-names = "video2_dpll_clk_mux"; 1322 clocks = <&sys_clkin1>, <&sys_clkin2>; 1323 reg = <0x016c>; 1324 }; 1325 1326 wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { 1327 #clock-cells = <0>; 1328 compatible = "ti,mux-clock"; 1329 clock-output-names = "wkupaon_iclk_mux"; 1330 clocks = <&sys_clkin1>, <&abe_lp_clk_div>; 1331 reg = <0x0108>; 1332 }; 1333}; 1334 1335&cm_core_clocks { 1336 dpll_pcie_ref_ck: clock@200 { 1337 #clock-cells = <0>; 1338 compatible = "ti,omap4-dpll-clock"; 1339 clock-output-names = "dpll_pcie_ref_ck"; 1340 clocks = <&sys_clkin1>, <&sys_clkin1>; 1341 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; 1342 }; 1343 1344 dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { 1345 #clock-cells = <0>; 1346 compatible = "ti,divider-clock"; 1347 clock-output-names = "dpll_pcie_ref_m2ldo_ck"; 1348 clocks = <&dpll_pcie_ref_ck>; 1349 ti,max-div = <31>; 1350 ti,autoidle-shift = <8>; 1351 reg = <0x0210>; 1352 ti,index-starts-at-one; 1353 ti,invert-autoidle-bit; 1354 }; 1355 1356 apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { 1357 compatible = "ti,mux-clock"; 1358 clock-output-names = "apll_pcie_in_clk_mux"; 1359 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; 1360 #clock-cells = <0>; 1361 reg = <0x021c 0x4>; 1362 ti,bit-shift = <7>; 1363 }; 1364 1365 apll_pcie_ck: clock@21c { 1366 #clock-cells = <0>; 1367 compatible = "ti,dra7-apll-clock"; 1368 clock-output-names = "apll_pcie_ck"; 1369 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; 1370 reg = <0x021c>, <0x0220>; 1371 }; 1372 1373 optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { 1374 compatible = "ti,divider-clock"; 1375 clock-output-names = "optfclk_pciephy_div"; 1376 clocks = <&apll_pcie_ck>; 1377 #clock-cells = <0>; 1378 reg = <0x021c>; 1379 ti,bit-shift = <8>; 1380 ti,max-div = <2>; 1381 }; 1382 1383 apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { 1384 #clock-cells = <0>; 1385 compatible = "fixed-factor-clock"; 1386 clock-output-names = "apll_pcie_clkvcoldo"; 1387 clocks = <&apll_pcie_ck>; 1388 clock-mult = <1>; 1389 clock-div = <1>; 1390 }; 1391 1392 apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { 1393 #clock-cells = <0>; 1394 compatible = "fixed-factor-clock"; 1395 clock-output-names = "apll_pcie_clkvcoldo_div"; 1396 clocks = <&apll_pcie_ck>; 1397 clock-mult = <1>; 1398 clock-div = <1>; 1399 }; 1400 1401 apll_pcie_m2_ck: clock-apll-pcie-m2 { 1402 #clock-cells = <0>; 1403 compatible = "fixed-factor-clock"; 1404 clock-output-names = "apll_pcie_m2_ck"; 1405 clocks = <&apll_pcie_ck>; 1406 clock-mult = <1>; 1407 clock-div = <1>; 1408 }; 1409 1410 /* CM_CLKSEL_DPLL_PER */ 1411 clock@14c { 1412 compatible = "ti,clksel"; 1413 reg = <0x14c>; 1414 #clock-cells = <2>; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 1418 dpll_per_byp_mux: clock@23 { 1419 reg = <23>; 1420 compatible = "ti,mux-clock"; 1421 clock-output-names = "dpll_per_byp_mux"; 1422 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; 1423 #clock-cells = <0>; 1424 }; 1425 }; 1426 1427 dpll_per_ck: clock@140 { 1428 #clock-cells = <0>; 1429 compatible = "ti,omap4-dpll-clock"; 1430 clock-output-names = "dpll_per_ck"; 1431 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; 1432 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 1433 }; 1434 1435 dpll_per_m2_ck: clock-dpll-per-m2-8@150 { 1436 #clock-cells = <0>; 1437 compatible = "ti,divider-clock"; 1438 clock-output-names = "dpll_per_m2_ck"; 1439 clocks = <&dpll_per_ck>; 1440 ti,max-div = <31>; 1441 ti,autoidle-shift = <8>; 1442 reg = <0x0150>; 1443 ti,index-starts-at-one; 1444 ti,invert-autoidle-bit; 1445 }; 1446 1447 func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { 1448 #clock-cells = <0>; 1449 compatible = "fixed-factor-clock"; 1450 clock-output-names = "func_96m_aon_dclk_div"; 1451 clocks = <&dpll_per_m2_ck>; 1452 clock-mult = <1>; 1453 clock-div = <1>; 1454 }; 1455 1456 /* CM_CLKSEL_DPLL_USB */ 1457 clock@18c { 1458 compatible = "ti,clksel"; 1459 reg = <0x18c>; 1460 #clock-cells = <2>; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 1464 dpll_usb_byp_mux: clock@23 { 1465 reg = <23>; 1466 compatible = "ti,mux-clock"; 1467 clock-output-names = "dpll_usb_byp_mux"; 1468 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; 1469 #clock-cells = <0>; 1470 }; 1471 }; 1472 1473 dpll_usb_ck: clock@180 { 1474 #clock-cells = <0>; 1475 compatible = "ti,omap4-dpll-j-type-clock"; 1476 clock-output-names = "dpll_usb_ck"; 1477 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; 1478 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 1479 }; 1480 1481 dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { 1482 #clock-cells = <0>; 1483 compatible = "ti,divider-clock"; 1484 clock-output-names = "dpll_usb_m2_ck"; 1485 clocks = <&dpll_usb_ck>; 1486 ti,max-div = <127>; 1487 ti,autoidle-shift = <8>; 1488 reg = <0x0190>; 1489 ti,index-starts-at-one; 1490 ti,invert-autoidle-bit; 1491 }; 1492 1493 dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { 1494 #clock-cells = <0>; 1495 compatible = "ti,divider-clock"; 1496 clock-output-names = "dpll_pcie_ref_m2_ck"; 1497 clocks = <&dpll_pcie_ref_ck>; 1498 ti,max-div = <127>; 1499 ti,autoidle-shift = <8>; 1500 reg = <0x0210>; 1501 ti,index-starts-at-one; 1502 ti,invert-autoidle-bit; 1503 }; 1504 1505 dpll_per_x2_ck: clock-dpll-per-x2 { 1506 #clock-cells = <0>; 1507 compatible = "ti,omap4-dpll-x2-clock"; 1508 clock-output-names = "dpll_per_x2_ck"; 1509 clocks = <&dpll_per_ck>; 1510 }; 1511 1512 dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { 1513 #clock-cells = <0>; 1514 compatible = "ti,divider-clock"; 1515 clock-output-names = "dpll_per_h11x2_ck"; 1516 clocks = <&dpll_per_x2_ck>; 1517 ti,max-div = <63>; 1518 ti,autoidle-shift = <8>; 1519 reg = <0x0158>; 1520 ti,index-starts-at-one; 1521 ti,invert-autoidle-bit; 1522 }; 1523 1524 dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { 1525 #clock-cells = <0>; 1526 compatible = "ti,divider-clock"; 1527 clock-output-names = "dpll_per_h12x2_ck"; 1528 clocks = <&dpll_per_x2_ck>; 1529 ti,max-div = <63>; 1530 ti,autoidle-shift = <8>; 1531 reg = <0x015c>; 1532 ti,index-starts-at-one; 1533 ti,invert-autoidle-bit; 1534 }; 1535 1536 dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { 1537 #clock-cells = <0>; 1538 compatible = "ti,divider-clock"; 1539 clock-output-names = "dpll_per_h13x2_ck"; 1540 clocks = <&dpll_per_x2_ck>; 1541 ti,max-div = <63>; 1542 ti,autoidle-shift = <8>; 1543 reg = <0x0160>; 1544 ti,index-starts-at-one; 1545 ti,invert-autoidle-bit; 1546 }; 1547 1548 dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { 1549 #clock-cells = <0>; 1550 compatible = "ti,divider-clock"; 1551 clock-output-names = "dpll_per_h14x2_ck"; 1552 clocks = <&dpll_per_x2_ck>; 1553 ti,max-div = <63>; 1554 ti,autoidle-shift = <8>; 1555 reg = <0x0164>; 1556 ti,index-starts-at-one; 1557 ti,invert-autoidle-bit; 1558 }; 1559 1560 dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { 1561 #clock-cells = <0>; 1562 compatible = "ti,divider-clock"; 1563 clock-output-names = "dpll_per_m2x2_ck"; 1564 clocks = <&dpll_per_x2_ck>; 1565 ti,max-div = <31>; 1566 ti,autoidle-shift = <8>; 1567 reg = <0x0150>; 1568 ti,index-starts-at-one; 1569 ti,invert-autoidle-bit; 1570 }; 1571 1572 dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { 1573 #clock-cells = <0>; 1574 compatible = "fixed-factor-clock"; 1575 clock-output-names = "dpll_usb_clkdcoldo"; 1576 clocks = <&dpll_usb_ck>; 1577 clock-mult = <1>; 1578 clock-div = <1>; 1579 }; 1580 1581 func_128m_clk: clock-func-128m { 1582 #clock-cells = <0>; 1583 compatible = "fixed-factor-clock"; 1584 clock-output-names = "func_128m_clk"; 1585 clocks = <&dpll_per_h11x2_ck>; 1586 clock-mult = <1>; 1587 clock-div = <2>; 1588 }; 1589 1590 func_12m_fclk: clock-func-12m-fclk { 1591 #clock-cells = <0>; 1592 compatible = "fixed-factor-clock"; 1593 clock-output-names = "func_12m_fclk"; 1594 clocks = <&dpll_per_m2x2_ck>; 1595 clock-mult = <1>; 1596 clock-div = <16>; 1597 }; 1598 1599 func_24m_clk: clock-func-24m { 1600 #clock-cells = <0>; 1601 compatible = "fixed-factor-clock"; 1602 clock-output-names = "func_24m_clk"; 1603 clocks = <&dpll_per_m2_ck>; 1604 clock-mult = <1>; 1605 clock-div = <4>; 1606 }; 1607 1608 func_48m_fclk: clock-func-48m-fclk { 1609 #clock-cells = <0>; 1610 compatible = "fixed-factor-clock"; 1611 clock-output-names = "func_48m_fclk"; 1612 clocks = <&dpll_per_m2x2_ck>; 1613 clock-mult = <1>; 1614 clock-div = <4>; 1615 }; 1616 1617 func_96m_fclk: clock-func-96m-fclk { 1618 #clock-cells = <0>; 1619 compatible = "fixed-factor-clock"; 1620 clock-output-names = "func_96m_fclk"; 1621 clocks = <&dpll_per_m2x2_ck>; 1622 clock-mult = <1>; 1623 clock-div = <2>; 1624 }; 1625 1626 l3init_60m_fclk: clock-l3init-60m@104 { 1627 #clock-cells = <0>; 1628 compatible = "ti,divider-clock"; 1629 clock-output-names = "l3init_60m_fclk"; 1630 clocks = <&dpll_usb_m2_ck>; 1631 reg = <0x0104>; 1632 ti,dividers = <1>, <8>; 1633 }; 1634 1635 clkout2_clk: clock-clkout2-8@6b0 { 1636 #clock-cells = <0>; 1637 compatible = "ti,gate-clock"; 1638 clock-output-names = "clkout2_clk"; 1639 clocks = <&clkoutmux2_clk_mux>; 1640 ti,bit-shift = <8>; 1641 reg = <0x06b0>; 1642 }; 1643 1644 l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { 1645 #clock-cells = <0>; 1646 compatible = "ti,gate-clock"; 1647 clock-output-names = "l3init_960m_gfclk"; 1648 clocks = <&dpll_usb_clkdcoldo>; 1649 ti,bit-shift = <8>; 1650 reg = <0x06c0>; 1651 }; 1652 1653 usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { 1654 #clock-cells = <0>; 1655 compatible = "ti,gate-clock"; 1656 clock-output-names = "usb_phy1_always_on_clk32k"; 1657 clocks = <&sys_32k_ck>; 1658 ti,bit-shift = <8>; 1659 reg = <0x0640>; 1660 }; 1661 1662 usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { 1663 #clock-cells = <0>; 1664 compatible = "ti,gate-clock"; 1665 clock-output-names = "usb_phy2_always_on_clk32k"; 1666 clocks = <&sys_32k_ck>; 1667 ti,bit-shift = <8>; 1668 reg = <0x0688>; 1669 }; 1670 1671 usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { 1672 #clock-cells = <0>; 1673 compatible = "ti,gate-clock"; 1674 clock-output-names = "usb_phy3_always_on_clk32k"; 1675 clocks = <&sys_32k_ck>; 1676 ti,bit-shift = <8>; 1677 reg = <0x0698>; 1678 }; 1679 1680 gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { 1681 #clock-cells = <0>; 1682 compatible = "ti,mux-clock"; 1683 clock-output-names = "gpu_core_gclk_mux"; 1684 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; 1685 ti,bit-shift = <24>; 1686 reg = <0x1220>; 1687 assigned-clocks = <&gpu_core_gclk_mux>; 1688 assigned-clock-parents = <&dpll_gpu_m2_ck>; 1689 }; 1690 1691 gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { 1692 #clock-cells = <0>; 1693 compatible = "ti,mux-clock"; 1694 clock-output-names = "gpu_hyd_gclk_mux"; 1695 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; 1696 ti,bit-shift = <26>; 1697 reg = <0x1220>; 1698 assigned-clocks = <&gpu_hyd_gclk_mux>; 1699 assigned-clock-parents = <&dpll_gpu_m2_ck>; 1700 }; 1701 1702 l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { 1703 #clock-cells = <0>; 1704 compatible = "ti,divider-clock"; 1705 clock-output-names = "l3instr_ts_gclk_div"; 1706 clocks = <&wkupaon_iclk_mux>; 1707 ti,bit-shift = <24>; 1708 reg = <0x0e50>; 1709 ti,dividers = <8>, <16>, <32>; 1710 }; 1711 1712 vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { 1713 #clock-cells = <0>; 1714 compatible = "ti,mux-clock"; 1715 clock-output-names = "vip1_gclk_mux"; 1716 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; 1717 ti,bit-shift = <24>; 1718 reg = <0x1020>; 1719 }; 1720 1721 vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { 1722 #clock-cells = <0>; 1723 compatible = "ti,mux-clock"; 1724 clock-output-names = "vip2_gclk_mux"; 1725 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; 1726 ti,bit-shift = <24>; 1727 reg = <0x1028>; 1728 }; 1729 1730 vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 { 1731 #clock-cells = <0>; 1732 compatible = "ti,mux-clock"; 1733 clock-output-names = "vip3_gclk_mux"; 1734 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; 1735 ti,bit-shift = <24>; 1736 reg = <0x1030>; 1737 }; 1738}; 1739 1740&cm_core_clockdomains { 1741 coreaon_clkdm: clock-coreaon-clkdm { 1742 compatible = "ti,clockdomain"; 1743 clock-output-names = "coreaon_clkdm"; 1744 clocks = <&dpll_usb_ck>; 1745 }; 1746}; 1747 1748&scm_conf_clocks { 1749 dss_deshdcp_clk: clock-dss-deshdcp-0@558 { 1750 #clock-cells = <0>; 1751 compatible = "ti,gate-clock"; 1752 clock-output-names = "dss_deshdcp_clk"; 1753 clocks = <&l3_iclk_div>; 1754 ti,bit-shift = <0>; 1755 reg = <0x558>; 1756 }; 1757 1758 ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 { 1759 #clock-cells = <0>; 1760 compatible = "ti,gate-clock"; 1761 clock-output-names = "ehrpwm0_tbclk"; 1762 clocks = <&l4_root_clk_div>; 1763 ti,bit-shift = <20>; 1764 reg = <0x0558>; 1765 }; 1766 1767 ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 { 1768 #clock-cells = <0>; 1769 compatible = "ti,gate-clock"; 1770 clock-output-names = "ehrpwm1_tbclk"; 1771 clocks = <&l4_root_clk_div>; 1772 ti,bit-shift = <21>; 1773 reg = <0x0558>; 1774 }; 1775 1776 ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 { 1777 #clock-cells = <0>; 1778 compatible = "ti,gate-clock"; 1779 clock-output-names = "ehrpwm2_tbclk"; 1780 clocks = <&l4_root_clk_div>; 1781 ti,bit-shift = <22>; 1782 reg = <0x0558>; 1783 }; 1784 1785 sys_32k_ck: clock-sys-32k@6c4 { 1786 #clock-cells = <0>; 1787 compatible = "ti,mux-clock"; 1788 clock-output-names = "sys_32k_ck"; 1789 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; 1790 ti,bit-shift = <8>; 1791 reg = <0x6c4>; 1792 }; 1793}; 1794 1795&cm_core_aon { 1796 mpu_cm: clock@300 { 1797 compatible = "ti,omap4-cm"; 1798 clock-output-names = "mpu_cm"; 1799 reg = <0x300 0x100>; 1800 #address-cells = <1>; 1801 #size-cells = <1>; 1802 ranges = <0 0x300 0x100>; 1803 1804 mpu_clkctrl: clock@20 { 1805 compatible = "ti,clkctrl"; 1806 clock-output-names = "mpu_clkctrl"; 1807 reg = <0x20 0x4>; 1808 #clock-cells = <2>; 1809 }; 1810 1811 }; 1812 1813 dsp1_cm: clock@400 { 1814 compatible = "ti,omap4-cm"; 1815 clock-output-names = "dsp1_cm"; 1816 reg = <0x400 0x100>; 1817 #address-cells = <1>; 1818 #size-cells = <1>; 1819 ranges = <0 0x400 0x100>; 1820 1821 dsp1_clkctrl: clock@20 { 1822 compatible = "ti,clkctrl"; 1823 clock-output-names = "dsp1_clkctrl"; 1824 reg = <0x20 0x4>; 1825 #clock-cells = <2>; 1826 }; 1827 1828 }; 1829 1830 ipu_cm: clock@500 { 1831 compatible = "ti,omap4-cm"; 1832 clock-output-names = "ipu_cm"; 1833 reg = <0x500 0x100>; 1834 #address-cells = <1>; 1835 #size-cells = <1>; 1836 ranges = <0 0x500 0x100>; 1837 1838 ipu1_clkctrl: clock@20 { 1839 compatible = "ti,clkctrl"; 1840 clock-output-names = "ipu1_clkctrl"; 1841 reg = <0x20 0x4>; 1842 #clock-cells = <2>; 1843 assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; 1844 assigned-clock-parents = <&dpll_core_h22x2_ck>; 1845 }; 1846 1847 ipu_clkctrl: clock@50 { 1848 compatible = "ti,clkctrl"; 1849 clock-output-names = "ipu_clkctrl"; 1850 reg = <0x50 0x34>; 1851 #clock-cells = <2>; 1852 }; 1853 1854 }; 1855 1856 dsp2_cm: clock@600 { 1857 compatible = "ti,omap4-cm"; 1858 clock-output-names = "dsp2_cm"; 1859 reg = <0x600 0x100>; 1860 #address-cells = <1>; 1861 #size-cells = <1>; 1862 ranges = <0 0x600 0x100>; 1863 1864 dsp2_clkctrl: clock@20 { 1865 compatible = "ti,clkctrl"; 1866 clock-output-names = "dsp2_clkctrl"; 1867 reg = <0x20 0x4>; 1868 #clock-cells = <2>; 1869 }; 1870 1871 }; 1872 1873 rtc_cm: clock@700 { 1874 compatible = "ti,omap4-cm"; 1875 clock-output-names = "rtc_cm"; 1876 reg = <0x700 0x60>; 1877 #address-cells = <1>; 1878 #size-cells = <1>; 1879 ranges = <0 0x700 0x60>; 1880 1881 rtc_clkctrl: clock@20 { 1882 compatible = "ti,clkctrl"; 1883 clock-output-names = "rtc_clkctrl"; 1884 reg = <0x20 0x28>; 1885 #clock-cells = <2>; 1886 }; 1887 }; 1888 1889 vpe_cm: clock@760 { 1890 compatible = "ti,omap4-cm"; 1891 clock-output-names = "vpe_cm"; 1892 reg = <0x760 0xc>; 1893 #address-cells = <1>; 1894 #size-cells = <1>; 1895 ranges = <0 0x760 0xc>; 1896 1897 vpe_clkctrl: clock@0 { 1898 compatible = "ti,clkctrl"; 1899 clock-output-names = "vpe_clkctrl"; 1900 reg = <0x0 0xc>; 1901 #clock-cells = <2>; 1902 }; 1903 }; 1904 1905}; 1906 1907&cm_core { 1908 coreaon_cm: clock@600 { 1909 compatible = "ti,omap4-cm"; 1910 clock-output-names = "coreaon_cm"; 1911 reg = <0x600 0x100>; 1912 #address-cells = <1>; 1913 #size-cells = <1>; 1914 ranges = <0 0x600 0x100>; 1915 1916 coreaon_clkctrl: clock@20 { 1917 compatible = "ti,clkctrl"; 1918 clock-output-names = "coreaon_clkctrl"; 1919 reg = <0x20 0x1c>; 1920 #clock-cells = <2>; 1921 }; 1922 }; 1923 1924 l3main1_cm: clock@700 { 1925 compatible = "ti,omap4-cm"; 1926 clock-output-names = "l3main1_cm"; 1927 reg = <0x700 0x100>; 1928 #address-cells = <1>; 1929 #size-cells = <1>; 1930 ranges = <0 0x700 0x100>; 1931 1932 l3main1_clkctrl: clock@20 { 1933 compatible = "ti,clkctrl"; 1934 clock-output-names = "l3main1_clkctrl"; 1935 reg = <0x20 0x74>; 1936 #clock-cells = <2>; 1937 }; 1938 1939 }; 1940 1941 ipu2_cm: clock@900 { 1942 compatible = "ti,omap4-cm"; 1943 clock-output-names = "ipu2_cm"; 1944 reg = <0x900 0x100>; 1945 #address-cells = <1>; 1946 #size-cells = <1>; 1947 ranges = <0 0x900 0x100>; 1948 1949 ipu2_clkctrl: clock@20 { 1950 compatible = "ti,clkctrl"; 1951 clock-output-names = "ipu2_clkctrl"; 1952 reg = <0x20 0x4>; 1953 #clock-cells = <2>; 1954 }; 1955 1956 }; 1957 1958 dma_cm: clock@a00 { 1959 compatible = "ti,omap4-cm"; 1960 clock-output-names = "dma_cm"; 1961 reg = <0xa00 0x100>; 1962 #address-cells = <1>; 1963 #size-cells = <1>; 1964 ranges = <0 0xa00 0x100>; 1965 1966 dma_clkctrl: clock@20 { 1967 compatible = "ti,clkctrl"; 1968 clock-output-names = "dma_clkctrl"; 1969 reg = <0x20 0x4>; 1970 #clock-cells = <2>; 1971 }; 1972 }; 1973 1974 emif_cm: clock@b00 { 1975 compatible = "ti,omap4-cm"; 1976 clock-output-names = "emif_cm"; 1977 reg = <0xb00 0x100>; 1978 #address-cells = <1>; 1979 #size-cells = <1>; 1980 ranges = <0 0xb00 0x100>; 1981 1982 emif_clkctrl: clock@20 { 1983 compatible = "ti,clkctrl"; 1984 clock-output-names = "emif_clkctrl"; 1985 reg = <0x20 0x4>; 1986 #clock-cells = <2>; 1987 }; 1988 }; 1989 1990 atl_cm: clock@c00 { 1991 compatible = "ti,omap4-cm"; 1992 clock-output-names = "atl_cm"; 1993 reg = <0xc00 0x100>; 1994 #address-cells = <1>; 1995 #size-cells = <1>; 1996 ranges = <0 0xc00 0x100>; 1997 1998 atl_clkctrl: clock@0 { 1999 compatible = "ti,clkctrl"; 2000 clock-output-names = "atl_clkctrl"; 2001 reg = <0x0 0x4>; 2002 #clock-cells = <2>; 2003 }; 2004 }; 2005 2006 l4cfg_cm: clock@d00 { 2007 compatible = "ti,omap4-cm"; 2008 clock-output-names = "l4cfg_cm"; 2009 reg = <0xd00 0x100>; 2010 #address-cells = <1>; 2011 #size-cells = <1>; 2012 ranges = <0 0xd00 0x100>; 2013 2014 l4cfg_clkctrl: clock@20 { 2015 compatible = "ti,clkctrl"; 2016 clock-output-names = "l4cfg_clkctrl"; 2017 reg = <0x20 0x84>; 2018 #clock-cells = <2>; 2019 }; 2020 }; 2021 2022 l3instr_cm: clock@e00 { 2023 compatible = "ti,omap4-cm"; 2024 clock-output-names = "l3instr_cm"; 2025 reg = <0xe00 0x100>; 2026 #address-cells = <1>; 2027 #size-cells = <1>; 2028 ranges = <0 0xe00 0x100>; 2029 2030 l3instr_clkctrl: clock@20 { 2031 compatible = "ti,clkctrl"; 2032 clock-output-names = "l3instr_clkctrl"; 2033 reg = <0x20 0xc>; 2034 #clock-cells = <2>; 2035 }; 2036 }; 2037 2038 iva_cm: clock@f00 { 2039 compatible = "ti,omap4-cm"; 2040 clock-output-names = "iva_cm"; 2041 reg = <0xf00 0x100>; 2042 #address-cells = <1>; 2043 #size-cells = <1>; 2044 ranges = <0 0xf00 0x100>; 2045 2046 iva_clkctrl: clock@20 { 2047 compatible = "ti,clkctrl"; 2048 clock-output-names = "iva_clkctrl"; 2049 reg = <0x20 0xc>; 2050 #clock-cells = <2>; 2051 }; 2052 }; 2053 2054 cam_cm: clock@1000 { 2055 compatible = "ti,omap4-cm"; 2056 clock-output-names = "cam_cm"; 2057 reg = <0x1000 0x100>; 2058 #address-cells = <1>; 2059 #size-cells = <1>; 2060 ranges = <0 0x1000 0x100>; 2061 2062 cam_clkctrl: clock@20 { 2063 compatible = "ti,clkctrl"; 2064 clock-output-names = "cam_clkctrl"; 2065 reg = <0x20 0x2c>; 2066 #clock-cells = <2>; 2067 }; 2068 }; 2069 2070 dss_cm: clock@1100 { 2071 compatible = "ti,omap4-cm"; 2072 clock-output-names = "dss_cm"; 2073 reg = <0x1100 0x100>; 2074 #address-cells = <1>; 2075 #size-cells = <1>; 2076 ranges = <0 0x1100 0x100>; 2077 2078 dss_clkctrl: clock@20 { 2079 compatible = "ti,clkctrl"; 2080 clock-output-names = "dss_clkctrl"; 2081 reg = <0x20 0x14>; 2082 #clock-cells = <2>; 2083 }; 2084 }; 2085 2086 gpu_cm: clock@1200 { 2087 compatible = "ti,omap4-cm"; 2088 clock-output-names = "gpu_cm"; 2089 reg = <0x1200 0x100>; 2090 #address-cells = <1>; 2091 #size-cells = <1>; 2092 ranges = <0 0x1200 0x100>; 2093 2094 gpu_clkctrl: clock@20 { 2095 compatible = "ti,clkctrl"; 2096 clock-output-names = "gpu_clkctrl"; 2097 reg = <0x20 0x4>; 2098 #clock-cells = <2>; 2099 }; 2100 }; 2101 2102 l3init_cm: clock@1300 { 2103 compatible = "ti,omap4-cm"; 2104 clock-output-names = "l3init_cm"; 2105 reg = <0x1300 0x100>; 2106 #address-cells = <1>; 2107 #size-cells = <1>; 2108 ranges = <0 0x1300 0x100>; 2109 2110 l3init_clkctrl: clock@20 { 2111 compatible = "ti,clkctrl"; 2112 clock-output-names = "l3init_clkctrl"; 2113 reg = <0x20 0x6c>, <0xe0 0x14>; 2114 #clock-cells = <2>; 2115 }; 2116 2117 pcie_clkctrl: clock@b0 { 2118 compatible = "ti,clkctrl"; 2119 clock-output-names = "pcie_clkctrl"; 2120 reg = <0xb0 0xc>; 2121 #clock-cells = <2>; 2122 }; 2123 2124 gmac_clkctrl: clock@d0 { 2125 compatible = "ti,clkctrl"; 2126 clock-output-names = "gmac_clkctrl"; 2127 reg = <0xd0 0x4>; 2128 #clock-cells = <2>; 2129 }; 2130 2131 }; 2132 2133 l4per_cm: clock@1700 { 2134 compatible = "ti,omap4-cm"; 2135 clock-output-names = "l4per_cm"; 2136 reg = <0x1700 0x300>; 2137 #address-cells = <1>; 2138 #size-cells = <1>; 2139 ranges = <0 0x1700 0x300>; 2140 2141 l4per_clkctrl: clock@28 { 2142 compatible = "ti,clkctrl"; 2143 clock-output-names = "l4per_clkctrl"; 2144 reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; 2145 #clock-cells = <2>; 2146 2147 assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2148 assigned-clock-parents = <&abe_24m_fclk>; 2149 }; 2150 2151 l4sec_clkctrl: clock@1a0 { 2152 compatible = "ti,clkctrl"; 2153 clock-output-names = "l4sec_clkctrl"; 2154 reg = <0x1a0 0x2c>; 2155 #clock-cells = <2>; 2156 }; 2157 2158 l4per2_clkctrl: clock@c { 2159 compatible = "ti,clkctrl"; 2160 clock-output-names = "l4per2_clkctrl"; 2161 reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; 2162 #clock-cells = <2>; 2163 }; 2164 2165 l4per3_clkctrl: clock@14 { 2166 compatible = "ti,clkctrl"; 2167 clock-output-names = "l4per3_clkctrl"; 2168 reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; 2169 #clock-cells = <2>; 2170 }; 2171 }; 2172 2173}; 2174 2175&prm { 2176 wkupaon_cm: clock@1800 { 2177 compatible = "ti,omap4-cm"; 2178 clock-output-names = "wkupaon_cm"; 2179 reg = <0x1800 0x100>; 2180 #address-cells = <1>; 2181 #size-cells = <1>; 2182 ranges = <0 0x1800 0x100>; 2183 2184 wkupaon_clkctrl: clock@20 { 2185 compatible = "ti,clkctrl"; 2186 clock-output-names = "wkupaon_clkctrl"; 2187 reg = <0x20 0x6c>; 2188 #clock-cells = <2>; 2189 }; 2190 }; 2191}; 2192