1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5/dts-v1/; 6 7#include "dra72x.dtsi" 8#include "dra7-ipu-dsp-common.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/clock/ti-dra7-atl.h> 11 12/ { 13 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; 14 15 aliases { 16 display0 = &hdmi0; 17 }; 18 19 chosen { 20 stdout-path = &uart1; 21 }; 22 23 evm_12v0: fixedregulator-evm12v0 { 24 /* main supply */ 25 compatible = "regulator-fixed"; 26 regulator-name = "evm_12v0"; 27 regulator-min-microvolt = <12000000>; 28 regulator-max-microvolt = <12000000>; 29 regulator-always-on; 30 regulator-boot-on; 31 }; 32 33 evm_5v0: fixedregulator-evm5v0 { 34 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ 35 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ 36 compatible = "regulator-fixed"; 37 regulator-name = "evm_5v0"; 38 regulator-min-microvolt = <5000000>; 39 regulator-max-microvolt = <5000000>; 40 vin-supply = <&evm_12v0>; 41 regulator-always-on; 42 regulator-boot-on; 43 }; 44 45 evm_3v6: fixedregulator-evm_3v6 { 46 compatible = "regulator-fixed"; 47 regulator-name = "evm_3v6"; 48 regulator-min-microvolt = <3600000>; 49 regulator-max-microvolt = <3600000>; 50 vin-supply = <&evm_5v0>; 51 regulator-always-on; 52 regulator-boot-on; 53 }; 54 55 vsys_3v3: fixedregulator-vsys3v3 { 56 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ 57 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ 58 compatible = "regulator-fixed"; 59 regulator-name = "vsys_3v3"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 vin-supply = <&evm_12v0>; 63 regulator-always-on; 64 regulator-boot-on; 65 }; 66 67 evm_3v3_sw: fixedregulator-evm_3v3 { 68 /* TPS22965DSG */ 69 compatible = "regulator-fixed"; 70 regulator-name = "evm_3v3"; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 vin-supply = <&vsys_3v3>; 74 regulator-always-on; 75 regulator-boot-on; 76 }; 77 78 aic_dvdd: fixedregulator-aic_dvdd { 79 /* TPS77018DBVT */ 80 compatible = "regulator-fixed"; 81 regulator-name = "aic_dvdd"; 82 vin-supply = <&evm_3v3_sw>; 83 regulator-min-microvolt = <1800000>; 84 regulator-max-microvolt = <1800000>; 85 }; 86 87 evm_3v3_sd: fixedregulator-sd { 88 compatible = "regulator-fixed"; 89 regulator-name = "evm_3v3_sd"; 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 vin-supply = <&evm_3v3_sw>; 93 enable-active-high; 94 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 95 }; 96 97 extcon_usb1: extcon_usb1 { 98 compatible = "linux,extcon-usb-gpio"; 99 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 100 }; 101 102 extcon_usb2: extcon_usb2 { 103 compatible = "linux,extcon-usb-gpio"; 104 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 105 }; 106 107 hdmi0: connector { 108 compatible = "hdmi-connector"; 109 label = "hdmi"; 110 111 type = "a"; 112 113 port { 114 hdmi_connector_in: endpoint { 115 remote-endpoint = <&tpd12s015_out>; 116 }; 117 }; 118 }; 119 120 tpd12s015: encoder { 121 compatible = "ti,tpd12s015"; 122 123 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ 124 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ 125 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ 126 127 ports { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 port@0 { 132 reg = <0>; 133 134 tpd12s015_in: endpoint { 135 remote-endpoint = <&hdmi_out>; 136 }; 137 }; 138 139 port@1 { 140 reg = <1>; 141 142 tpd12s015_out: endpoint { 143 remote-endpoint = <&hdmi_connector_in>; 144 }; 145 }; 146 }; 147 }; 148 149 sound0: sound0 { 150 compatible = "simple-audio-card"; 151 simple-audio-card,name = "DRA7xx-EVM"; 152 simple-audio-card,widgets = 153 "Headphone", "Headphone Jack", 154 "Line", "Line Out", 155 "Microphone", "Mic Jack", 156 "Line", "Line In"; 157 simple-audio-card,routing = 158 "Headphone Jack", "HPLOUT", 159 "Headphone Jack", "HPROUT", 160 "Line Out", "LLOUT", 161 "Line Out", "RLOUT", 162 "MIC3L", "Mic Jack", 163 "MIC3R", "Mic Jack", 164 "Mic Jack", "Mic Bias", 165 "LINE1L", "Line In", 166 "LINE1R", "Line In"; 167 simple-audio-card,format = "dsp_b"; 168 simple-audio-card,bitclock-master = <&sound0_master>; 169 simple-audio-card,frame-master = <&sound0_master>; 170 simple-audio-card,bitclock-inversion; 171 172 sound0_master: simple-audio-card,cpu { 173 sound-dai = <&mcasp3>; 174 system-clock-frequency = <5644800>; 175 }; 176 177 simple-audio-card,codec { 178 sound-dai = <&tlv320aic3106>; 179 clocks = <&atl_clkin2_ck>; 180 }; 181 }; 182 183 vmmcwl_fixed: fixedregulator-mmcwl { 184 compatible = "regulator-fixed"; 185 regulator-name = "vmmcwl_fixed"; 186 regulator-min-microvolt = <1800000>; 187 regulator-max-microvolt = <1800000>; 188 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; 189 enable-active-high; 190 }; 191 192 clk_ov5640_fixed: clock { 193 compatible = "fixed-clock"; 194 #clock-cells = <0>; 195 clock-frequency = <24000000>; 196 }; 197}; 198 199&dra7_pmx_core { 200 dcan1_pins_default: dcan1-default-pins { 201 pinctrl-single,pins = < 202 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 203 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 204 >; 205 }; 206 207 dcan1_pins_sleep: dcan1-sleep-pins { 208 pinctrl-single,pins = < 209 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 210 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ 211 >; 212 }; 213}; 214 215&i2c1 { 216 status = "okay"; 217 clock-frequency = <400000>; 218 219 pcf_lcd: gpio@20 { 220 compatible = "nxp,pcf8575"; 221 reg = <0x20>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 interrupt-controller; 225 #interrupt-cells = <2>; 226 }; 227 228 pcf_gpio_21: gpio@21 { 229 compatible = "nxp,pcf8575"; 230 reg = <0x21>; 231 lines-initial-states = <0x1408>; 232 gpio-controller; 233 #gpio-cells = <2>; 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 }; 237 238 tlv320aic3106: tlv320aic3106@19 { 239 #sound-dai-cells = <0>; 240 compatible = "ti,tlv320aic3106"; 241 reg = <0x19>; 242 adc-settle-ms = <40>; 243 ai3x-micbias-vg = <1>; /* 2.0V */ 244 status = "okay"; 245 246 /* Regulators */ 247 AVDD-supply = <&evm_3v3_sw>; 248 IOVDD-supply = <&evm_3v3_sw>; 249 DRVDD-supply = <&evm_3v3_sw>; 250 DVDD-supply = <&aic_dvdd>; 251 }; 252}; 253 254&i2c5 { 255 status = "okay"; 256 clock-frequency = <400000>; 257 258 pcf_hdmi: pcf8575@26 { 259 compatible = "nxp,pcf8575"; 260 reg = <0x26>; 261 gpio-controller; 262 #gpio-cells = <2>; 263 /* 264 * initial state is used here to keep the mdio interface 265 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and 266 * VIN2_S0 driven high otherwise Ethernet stops working 267 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 268 */ 269 lines-initial-states = <0x0f2b>; 270 271 hdmi-audio-hog { 272 /* vin6_sel_s0: high: VIN6, low: audio */ 273 gpio-hog; 274 gpios = <1 GPIO_ACTIVE_HIGH>; 275 output-low; 276 line-name = "vin6_sel_s0"; 277 }; 278 }; 279 280 ov5640@3c { 281 compatible = "ovti,ov5640"; 282 reg = <0x3c>; 283 284 clocks = <&clk_ov5640_fixed>; 285 clock-names = "xclk"; 286 287 port { 288 csi2_cam0: endpoint { 289 remote-endpoint = <&csi2_phy0>; 290 clock-lanes = <0>; 291 data-lanes = <1 2>; 292 }; 293 }; 294 }; 295 296}; 297 298&uart1 { 299 status = "okay"; 300 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 301 <&dra7_pmx_core 0x3e0>; 302}; 303 304&elm { 305 status = "okay"; 306}; 307 308&gpmc { 309 /* 310 * For the existing IOdelay configuration via U-Boot we don't 311 * support NAND on dra72-evm. Keep it disabled. Enabling it 312 * requires a different configuration by U-Boot. 313 */ 314 status = "disabled"; 315 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 316 nand@0,0 { 317 /* To use NAND, DIP switch SW5 must be set like so: 318 * SW5.1 (NAND_SELn) = ON (LOW) 319 * SW5.9 (GPMC_WPN) = OFF (HIGH) 320 */ 321 compatible = "ti,omap2-nand"; 322 reg = <0 0 4>; /* device IO registers */ 323 interrupt-parent = <&gpmc>; 324 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 325 <1 IRQ_TYPE_NONE>; /* termcount */ 326 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ 327 ti,nand-xfer-type = "prefetch-dma"; 328 ti,nand-ecc-opt = "bch8"; 329 ti,elm-id = <&elm>; 330 nand-bus-width = <16>; 331 gpmc,device-width = <2>; 332 gpmc,sync-clk-ps = <0>; 333 gpmc,cs-on-ns = <0>; 334 gpmc,cs-rd-off-ns = <80>; 335 gpmc,cs-wr-off-ns = <80>; 336 gpmc,adv-on-ns = <0>; 337 gpmc,adv-rd-off-ns = <60>; 338 gpmc,adv-wr-off-ns = <60>; 339 gpmc,we-on-ns = <10>; 340 gpmc,we-off-ns = <50>; 341 gpmc,oe-on-ns = <4>; 342 gpmc,oe-off-ns = <40>; 343 gpmc,access-ns = <40>; 344 gpmc,wr-access-ns = <80>; 345 gpmc,rd-cycle-ns = <80>; 346 gpmc,wr-cycle-ns = <80>; 347 gpmc,bus-turnaround-ns = <0>; 348 gpmc,cycle2cycle-delay-ns = <0>; 349 gpmc,clk-activation-ns = <0>; 350 gpmc,wr-data-mux-bus-ns = <0>; 351 /* MTD partition table */ 352 /* All SPL-* partitions are sized to minimal length 353 * which can be independently programmable. For 354 * NAND flash this is equal to size of erase-block */ 355 #address-cells = <1>; 356 #size-cells = <1>; 357 partition@0 { 358 label = "NAND.SPL"; 359 reg = <0x00000000 0x00020000>; 360 }; 361 partition@1 { 362 label = "NAND.SPL.backup1"; 363 reg = <0x00020000 0x00020000>; 364 }; 365 partition@2 { 366 label = "NAND.SPL.backup2"; 367 reg = <0x00040000 0x00020000>; 368 }; 369 partition@3 { 370 label = "NAND.SPL.backup3"; 371 reg = <0x00060000 0x00020000>; 372 }; 373 partition@4 { 374 label = "NAND.u-boot-spl-os"; 375 reg = <0x00080000 0x00040000>; 376 }; 377 partition@5 { 378 label = "NAND.u-boot"; 379 reg = <0x000c0000 0x00100000>; 380 }; 381 partition@6 { 382 label = "NAND.u-boot-env"; 383 reg = <0x001c0000 0x00020000>; 384 }; 385 partition@7 { 386 label = "NAND.u-boot-env.backup1"; 387 reg = <0x001e0000 0x00020000>; 388 }; 389 partition@8 { 390 label = "NAND.kernel"; 391 reg = <0x00200000 0x00800000>; 392 }; 393 partition@9 { 394 label = "NAND.file-system"; 395 reg = <0x00a00000 0x0f600000>; 396 }; 397 }; 398}; 399 400&omap_dwc3_1 { 401 extcon = <&extcon_usb1>; 402}; 403 404&omap_dwc3_2 { 405 extcon = <&extcon_usb2>; 406}; 407 408&usb1 { 409 dr_mode = "otg"; 410 extcon = <&extcon_usb1>; 411}; 412 413&usb2 { 414 dr_mode = "host"; 415 extcon = <&extcon_usb2>; 416}; 417 418&mmc1 { 419 status = "okay"; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&mmc1_pins_default>; 422 vmmc-supply = <&evm_3v3_sd>; 423 bus-width = <4>; 424 /* 425 * SDCD signal is not being used here - using the fact that GPIO mode 426 * is a viable alternative 427 */ 428 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 429 max-frequency = <192000000>; 430}; 431 432&mmc2 { 433 /* SW5-3 in ON position */ 434 status = "okay"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&mmc2_pins_default>; 437 bus-width = <8>; 438 non-removable; 439 max-frequency = <192000000>; 440}; 441 442&mmc4 { 443 status = "okay"; 444 vmmc-supply = <&evm_3v6>; 445 vqmmc-supply = <&vmmcwl_fixed>; 446 bus-width = <4>; 447 cap-power-off-card; 448 keep-power-in-suspend; 449 non-removable; 450 pinctrl-names = "default", "hs", "sdr12", "sdr25"; 451 pinctrl-0 = <&mmc4_pins_default>; 452 pinctrl-1 = <&mmc4_pins_default>; 453 pinctrl-2 = <&mmc4_pins_default>; 454 pinctrl-3 = <&mmc4_pins_default>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 wifi@2 { 458 compatible = "ti,wl1835"; 459 reg = <2>; 460 interrupt-parent = <&gpio5>; 461 interrupts = <7 IRQ_TYPE_EDGE_RISING>; 462 }; 463}; 464 465&dcan1 { 466 status = "okay"; 467 pinctrl-names = "default", "sleep", "active"; 468 pinctrl-0 = <&dcan1_pins_sleep>; 469 pinctrl-1 = <&dcan1_pins_sleep>; 470 pinctrl-2 = <&dcan1_pins_default>; 471}; 472 473&qspi { 474 status = "okay"; 475 476 spi-max-frequency = <76800000>; 477 flash@0 { 478 compatible = "s25fl256s1"; 479 spi-max-frequency = <76800000>; 480 reg = <0>; 481 spi-tx-bus-width = <1>; 482 spi-rx-bus-width = <4>; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 486 /* MTD partition table. 487 * The ROM checks the first four physical blocks 488 * for a valid file to boot and the flash here is 489 * 64KiB block size. 490 */ 491 partition@0 { 492 label = "QSPI.SPL"; 493 reg = <0x00000000 0x00010000>; 494 }; 495 partition@1 { 496 label = "QSPI.SPL.backup1"; 497 reg = <0x00010000 0x00010000>; 498 }; 499 partition@2 { 500 label = "QSPI.SPL.backup2"; 501 reg = <0x00020000 0x00010000>; 502 }; 503 partition@3 { 504 label = "QSPI.SPL.backup3"; 505 reg = <0x00030000 0x00010000>; 506 }; 507 partition@4 { 508 label = "QSPI.u-boot"; 509 reg = <0x00040000 0x00100000>; 510 }; 511 partition@5 { 512 label = "QSPI.u-boot-spl-os"; 513 reg = <0x00140000 0x00080000>; 514 }; 515 partition@6 { 516 label = "QSPI.u-boot-env"; 517 reg = <0x001c0000 0x00010000>; 518 }; 519 partition@7 { 520 label = "QSPI.u-boot-env.backup1"; 521 reg = <0x001d0000 0x0010000>; 522 }; 523 partition@8 { 524 label = "QSPI.kernel"; 525 reg = <0x001e0000 0x0800000>; 526 }; 527 partition@9 { 528 label = "QSPI.file-system"; 529 reg = <0x009e0000 0x01620000>; 530 }; 531 }; 532}; 533 534&dss { 535 status = "okay"; 536}; 537 538&hdmi { 539 status = "okay"; 540 541 port { 542 hdmi_out: endpoint { 543 remote-endpoint = <&tpd12s015_in>; 544 }; 545 }; 546}; 547 548&atl { 549 assigned-clocks = <&abe_dpll_sys_clk_mux>, 550 <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, 551 <&dpll_abe_ck>, 552 <&dpll_abe_m2x2_ck>, 553 <&atl_clkin2_ck>; 554 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; 555 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; 556 557 status = "okay"; 558 559 atl2 { 560 bws = <DRA7_ATL_WS_MCASP2_FSX>; 561 aws = <DRA7_ATL_WS_MCASP3_FSX>; 562 }; 563}; 564 565&mcasp3 { 566 #sound-dai-cells = <0>; 567 568 assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 569 assigned-clock-parents = <&atl_clkin2_ck>; 570 571 status = "okay"; 572 573 op-mode = <0>; /* MCASP_IIS_MODE */ 574 tdm-slots = <2>; 575 /* 4 serializer */ 576 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 577 1 2 0 0 578 >; 579 tx-num-evt = <32>; 580 rx-num-evt = <32>; 581}; 582 583&pcie1_rc { 584 status = "okay"; 585}; 586 587&csi2_0 { 588 csi2_phy0: endpoint { 589 remote-endpoint = <&csi2_cam0>; 590 clock-lanes = <0>; 591 data-lanes = <1 2>; 592 }; 593}; 594