1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Based on "omap4.dtsi" 6 */ 7 8#include <dt-bindings/bus/ti-sysc.h> 9#include <dt-bindings/clock/dra7.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/dra.h> 12 13#define MAX_SOURCES 400 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 compatible = "ti,dra7xx"; 20 interrupt-parent = <&crossbar_mpu>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 i2c3 = &i2c4; 28 i2c4 = &i2c5; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &uart6; 35 serial6 = &uart7; 36 serial7 = &uart8; 37 serial8 = &uart9; 38 serial9 = &uart10; 39 ethernet0 = &cpsw_port1; 40 ethernet1 = &cpsw_port2; 41 d_can0 = &dcan1; 42 d_can1 = &dcan2; 43 spi0 = &qspi; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 status = "disabled"; /* See ARM architected timer wrap erratum i940 */ 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&gic>; 54 }; 55 56 gic: interrupt-controller@48211000 { 57 compatible = "arm,cortex-a15-gic"; 58 interrupt-controller; 59 #interrupt-cells = <3>; 60 reg = <0x0 0x48211000 0x0 0x1000>, 61 <0x0 0x48212000 0x0 0x2000>, 62 <0x0 0x48214000 0x0 0x2000>, 63 <0x0 0x48216000 0x0 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 65 interrupt-parent = <&gic>; 66 }; 67 68 wakeupgen: interrupt-controller@48281000 { 69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 70 interrupt-controller; 71 #interrupt-cells = <3>; 72 reg = <0x0 0x48281000 0x0 0x1000>; 73 interrupt-parent = <&gic>; 74 }; 75 76 cpus { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 cpu0: cpu@0 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a15"; 83 reg = <0>; 84 85 operating-points-v2 = <&cpu0_opp_table>; 86 87 clocks = <&dpll_mpu_ck>; 88 clock-names = "cpu"; 89 90 clock-latency = <300000>; /* From omap-cpufreq driver */ 91 92 /* cooling options */ 93 #cooling-cells = <2>; /* min followed by max */ 94 95 vbb-supply = <&abb_mpu>; 96 }; 97 }; 98 99 cpu0_opp_table: opp-table { 100 compatible = "operating-points-v2-ti-cpu"; 101 syscon = <&scm_wkup>; 102 103 opp-1000000000 { 104 /* OPP NOM */ 105 opp-hz = /bits/ 64 <1000000000>; 106 opp-microvolt = <1060000 850000 1150000>, 107 <1060000 850000 1150000>; 108 opp-supported-hw = <0xFF 0x01>; 109 opp-suspend; 110 }; 111 112 opp-1176000000 { 113 /* OPP OD */ 114 opp-hz = /bits/ 64 <1176000000>; 115 opp-microvolt = <1160000 885000 1160000>, 116 <1160000 885000 1160000>; 117 118 opp-supported-hw = <0xFF 0x02>; 119 }; 120 121 opp-1500000000 { 122 /* OPP High */ 123 opp-hz = /bits/ 64 <1500000000>; 124 opp-microvolt = <1210000 950000 1250000>, 125 <1210000 950000 1250000>; 126 opp-supported-hw = <0xFF 0x04>; 127 }; 128 }; 129 130 /* 131 * XXX: Use a flat representation of the SOC interconnect. 132 * The real OMAP interconnect network is quite complex. 133 * Since it will not bring real advantage to represent that in DT for 134 * the moment, just use a fake OCP bus entry to represent the whole bus 135 * hierarchy. 136 */ 137 ocp: ocp { 138 compatible = "simple-pm-bus"; 139 power-domains = <&prm_core>; 140 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>, 141 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>; 142 #address-cells = <1>; 143 #size-cells = <1>; 144 ranges = <0x0 0x0 0x0 0xc0000000>; 145 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 146 147 l3-noc@44000000 { 148 compatible = "ti,dra7-l3-noc"; 149 reg = <0x44000000 0x1000000>, 150 <0x45000000 0x1000>; 151 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 152 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 153 }; 154 155 l4_cfg: interconnect@4a000000 { 156 }; 157 l4_wkup: interconnect@4ae00000 { 158 }; 159 l4_per1: interconnect@48000000 { 160 }; 161 162 target-module@48210000 { 163 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 164 power-domains = <&prm_mpu>; 165 clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>; 166 clock-names = "fck"; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 ranges = <0 0x48210000 0x1f0000>; 170 171 mpu { 172 compatible = "ti,omap5-mpu"; 173 }; 174 }; 175 176 l4_per2: interconnect@48400000 { 177 }; 178 l4_per3: interconnect@48800000 { 179 }; 180 181 /* 182 * Register access seems to have complex dependencies and also 183 * seems to need an enabled phy. See the TRM chapter for "Table 184 * 26-678. Main Sequence PCIe Controller Global Initialization" 185 * and also dra7xx_pcie_probe(). 186 */ 187 axi0: target-module@51000000 { 188 compatible = "ti,sysc-omap4", "ti,sysc"; 189 power-domains = <&prm_l3init>; 190 resets = <&prm_l3init 0>; 191 reset-names = "rstctrl"; 192 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>, 193 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, 194 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>; 195 clock-names = "fck", "phy-clk", "phy-clk-div"; 196 #size-cells = <1>; 197 #address-cells = <1>; 198 ranges = <0x51000000 0x51000000 0x3000>, 199 <0x20000000 0x20000000 0x10000000>; 200 dma-ranges; 201 /** 202 * To enable PCI endpoint mode, disable the pcie1_rc 203 * node and enable pcie1_ep mode. 204 */ 205 pcie1_rc: pcie@51000000 { 206 reg = <0x51000000 0x2000>, 207 <0x51002000 0x14c>, 208 <0x20001000 0x2000>; 209 reg-names = "rc_dbics", "ti_conf", "config"; 210 interrupts = <0 232 0x4>, <0 233 0x4>; 211 #address-cells = <3>; 212 #size-cells = <2>; 213 device_type = "pci"; 214 ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>, 215 <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>; 216 bus-range = <0x00 0xff>; 217 #interrupt-cells = <1>; 218 num-lanes = <1>; 219 linux,pci-domain = <0>; 220 phys = <&pcie1_phy>; 221 phy-names = "pcie-phy0"; 222 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; 223 interrupt-map-mask = <0 0 0 7>; 224 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 225 <0 0 0 2 &pcie1_intc 2>, 226 <0 0 0 3 &pcie1_intc 3>, 227 <0 0 0 4 &pcie1_intc 4>; 228 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 229 status = "disabled"; 230 pcie1_intc: interrupt-controller { 231 interrupt-controller; 232 #address-cells = <0>; 233 #interrupt-cells = <1>; 234 }; 235 }; 236 237 pcie1_ep: pcie_ep@51000000 { 238 reg = <0x51000000 0x28>, 239 <0x51002000 0x14c>, 240 <0x51001000 0x28>, 241 <0x20001000 0x10000000>; 242 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; 243 interrupts = <0 232 0x4>; 244 num-lanes = <1>; 245 num-ib-windows = <4>; 246 num-ob-windows = <16>; 247 phys = <&pcie1_phy>; 248 phy-names = "pcie-phy0"; 249 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 250 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; 251 status = "disabled"; 252 }; 253 }; 254 255 /* 256 * Register access seems to have complex dependencies and also 257 * seems to need an enabled phy. See the TRM chapter for "Table 258 * 26-678. Main Sequence PCIe Controller Global Initialization" 259 * and also dra7xx_pcie_probe(). 260 */ 261 axi1: target-module@51800000 { 262 compatible = "ti,sysc-omap4", "ti,sysc"; 263 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>, 264 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, 265 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>; 266 clock-names = "fck", "phy-clk", "phy-clk-div"; 267 power-domains = <&prm_l3init>; 268 resets = <&prm_l3init 1>; 269 reset-names = "rstctrl"; 270 #size-cells = <1>; 271 #address-cells = <1>; 272 ranges = <0x51800000 0x51800000 0x3000>, 273 <0x30000000 0x30000000 0x10000000>; 274 dma-ranges; 275 status = "disabled"; 276 pcie2_rc: pcie@51800000 { 277 reg = <0x51800000 0x2000>, 278 <0x51802000 0x14c>, 279 <0x30001000 0x2000>; 280 reg-names = "rc_dbics", "ti_conf", "config"; 281 interrupts = <0 355 0x4>, <0 356 0x4>; 282 #address-cells = <3>; 283 #size-cells = <2>; 284 device_type = "pci"; 285 ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>, 286 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>; 287 bus-range = <0x00 0xff>; 288 #interrupt-cells = <1>; 289 num-lanes = <1>; 290 linux,pci-domain = <1>; 291 phys = <&pcie2_phy>; 292 phy-names = "pcie-phy0"; 293 interrupt-map-mask = <0 0 0 7>; 294 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 295 <0 0 0 2 &pcie2_intc 2>, 296 <0 0 0 3 &pcie2_intc 3>, 297 <0 0 0 4 &pcie2_intc 4>; 298 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; 299 pcie2_intc: interrupt-controller { 300 interrupt-controller; 301 #address-cells = <0>; 302 #interrupt-cells = <1>; 303 }; 304 }; 305 }; 306 307 ocmcram1: ocmcram@40300000 { 308 compatible = "mmio-sram"; 309 reg = <0x40300000 0x80000>; 310 ranges = <0x0 0x40300000 0x80000>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 /* 314 * This is a placeholder for an optional reserved 315 * region for use by secure software. The size 316 * of this region is not known until runtime so it 317 * is set as zero to either be updated to reserve 318 * space or left unchanged to leave all SRAM for use. 319 * On HS parts that that require the reserved region 320 * either the bootloader can update the size to 321 * the required amount or the node can be overridden 322 * from the board dts file for the secure platform. 323 */ 324 sram-hs@0 { 325 compatible = "ti,secure-ram"; 326 reg = <0x0 0x0>; 327 }; 328 }; 329 330 /* 331 * NOTE: ocmcram2 and ocmcram3 are not available on all 332 * DRA7xx and AM57xx variants. Confirm availability in 333 * the data manual for the exact part number in use 334 * before enabling these nodes in the board dts file. 335 */ 336 ocmcram2: ocmcram@40400000 { 337 status = "disabled"; 338 compatible = "mmio-sram"; 339 reg = <0x40400000 0x100000>; 340 ranges = <0x0 0x40400000 0x100000>; 341 #address-cells = <1>; 342 #size-cells = <1>; 343 }; 344 345 ocmcram3: ocmcram@40500000 { 346 status = "disabled"; 347 compatible = "mmio-sram"; 348 reg = <0x40500000 0x100000>; 349 ranges = <0x0 0x40500000 0x100000>; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 }; 353 354 bandgap: bandgap@4a0021e0 { 355 reg = <0x4a0021e0 0xc 356 0x4a00232c 0xc 357 0x4a002380 0x2c 358 0x4a0023C0 0x3c 359 0x4a002564 0x8 360 0x4a002574 0x50>; 361 compatible = "ti,dra752-bandgap"; 362 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 363 #thermal-sensor-cells = <1>; 364 }; 365 366 dsp1_system: dsp_system@40d00000 { 367 compatible = "syscon"; 368 reg = <0x40d00000 0x100>; 369 }; 370 371 dra7_iodelay_core: padconf@4844a000 { 372 compatible = "ti,dra7-iodelay"; 373 reg = <0x4844a000 0x0d1c>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 #pinctrl-cells = <2>; 377 }; 378 379 target-module@43300000 { 380 compatible = "ti,sysc-omap4", "ti,sysc"; 381 reg = <0x43300000 0x4>, 382 <0x43300010 0x4>; 383 reg-names = "rev", "sysc"; 384 ti,sysc-midle = <SYSC_IDLE_FORCE>, 385 <SYSC_IDLE_NO>, 386 <SYSC_IDLE_SMART>; 387 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 388 <SYSC_IDLE_NO>, 389 <SYSC_IDLE_SMART>; 390 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; 391 clock-names = "fck"; 392 #address-cells = <1>; 393 #size-cells = <1>; 394 ranges = <0x0 0x43300000 0x100000>; 395 396 edma: dma@0 { 397 compatible = "ti,edma3-tpcc"; 398 reg = <0 0x100000>; 399 reg-names = "edma3_cc"; 400 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-names = "edma3_ccint", "edma3_mperr", 404 "edma3_ccerrint"; 405 dma-requests = <64>; 406 #dma-cells = <2>; 407 408 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; 409 410 /* 411 * memcpy is disabled, can be enabled with: 412 * ti,edma-memcpy-channels = <20 21>; 413 * for example. Note that these channels need to be 414 * masked in the xbar as well. 415 */ 416 }; 417 }; 418 419 target-module@43400000 { 420 compatible = "ti,sysc-omap4", "ti,sysc"; 421 reg = <0x43400000 0x4>, 422 <0x43400010 0x4>; 423 reg-names = "rev", "sysc"; 424 ti,sysc-midle = <SYSC_IDLE_FORCE>, 425 <SYSC_IDLE_NO>, 426 <SYSC_IDLE_SMART>; 427 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 428 <SYSC_IDLE_NO>, 429 <SYSC_IDLE_SMART>; 430 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; 431 clock-names = "fck"; 432 #address-cells = <1>; 433 #size-cells = <1>; 434 ranges = <0x0 0x43400000 0x100000>; 435 436 edma_tptc0: dma@0 { 437 compatible = "ti,edma3-tptc"; 438 reg = <0 0x100000>; 439 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-names = "edma3_tcerrint"; 441 }; 442 }; 443 444 target-module@43500000 { 445 compatible = "ti,sysc-omap4", "ti,sysc"; 446 reg = <0x43500000 0x4>, 447 <0x43500010 0x4>; 448 reg-names = "rev", "sysc"; 449 ti,sysc-midle = <SYSC_IDLE_FORCE>, 450 <SYSC_IDLE_NO>, 451 <SYSC_IDLE_SMART>; 452 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 453 <SYSC_IDLE_NO>, 454 <SYSC_IDLE_SMART>; 455 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; 456 clock-names = "fck"; 457 #address-cells = <1>; 458 #size-cells = <1>; 459 ranges = <0x0 0x43500000 0x100000>; 460 461 edma_tptc1: dma@0 { 462 compatible = "ti,edma3-tptc"; 463 reg = <0 0x100000>; 464 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-names = "edma3_tcerrint"; 466 }; 467 }; 468 469 target-module@4e000000 { 470 compatible = "ti,sysc-omap2", "ti,sysc"; 471 reg = <0x4e000000 0x4>, 472 <0x4e000010 0x4>; 473 reg-names = "rev", "sysc"; 474 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 475 <SYSC_IDLE_NO>, 476 <SYSC_IDLE_SMART>; 477 ranges = <0x0 0x4e000000 0x2000000>; 478 #size-cells = <1>; 479 #address-cells = <1>; 480 481 dmm@0 { 482 compatible = "ti,omap5-dmm"; 483 reg = <0 0x800>; 484 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 485 }; 486 }; 487 488 ipu1: ipu@58820000 { 489 compatible = "ti,dra7-ipu"; 490 reg = <0x58820000 0x10000>; 491 reg-names = "l2ram"; 492 iommus = <&mmu_ipu1>; 493 status = "disabled"; 494 resets = <&prm_ipu 0>, <&prm_ipu 1>; 495 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; 496 firmware-name = "dra7-ipu1-fw.xem4"; 497 }; 498 499 ipu2: ipu@55020000 { 500 compatible = "ti,dra7-ipu"; 501 reg = <0x55020000 0x10000>; 502 reg-names = "l2ram"; 503 iommus = <&mmu_ipu2>; 504 status = "disabled"; 505 resets = <&prm_core 0>, <&prm_core 1>; 506 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; 507 firmware-name = "dra7-ipu2-fw.xem4"; 508 }; 509 510 dsp1: dsp@40800000 { 511 compatible = "ti,dra7-dsp"; 512 reg = <0x40800000 0x48000>, 513 <0x40e00000 0x8000>, 514 <0x40f00000 0x8000>; 515 reg-names = "l2ram", "l1pram", "l1dram"; 516 ti,bootreg = <&scm_conf 0x55c 10>; 517 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; 518 status = "disabled"; 519 resets = <&prm_dsp1 0>; 520 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 521 firmware-name = "dra7-dsp1-fw.xe66"; 522 }; 523 524 target-module@40d01000 { 525 compatible = "ti,sysc-omap2", "ti,sysc"; 526 reg = <0x40d01000 0x4>, 527 <0x40d01010 0x4>, 528 <0x40d01014 0x4>; 529 reg-names = "rev", "sysc", "syss"; 530 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 531 <SYSC_IDLE_NO>, 532 <SYSC_IDLE_SMART>; 533 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 534 SYSC_OMAP2_SOFTRESET | 535 SYSC_OMAP2_AUTOIDLE)>; 536 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 537 clock-names = "fck"; 538 resets = <&prm_dsp1 1>; 539 reset-names = "rstctrl"; 540 ranges = <0x0 0x40d01000 0x1000>; 541 #size-cells = <1>; 542 #address-cells = <1>; 543 544 mmu0_dsp1: mmu@0 { 545 compatible = "ti,dra7-dsp-iommu"; 546 reg = <0x0 0x100>; 547 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 548 #iommu-cells = <0>; 549 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 550 }; 551 }; 552 553 target-module@40d02000 { 554 compatible = "ti,sysc-omap2", "ti,sysc"; 555 reg = <0x40d02000 0x4>, 556 <0x40d02010 0x4>, 557 <0x40d02014 0x4>; 558 reg-names = "rev", "sysc", "syss"; 559 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 560 <SYSC_IDLE_NO>, 561 <SYSC_IDLE_SMART>; 562 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 563 SYSC_OMAP2_SOFTRESET | 564 SYSC_OMAP2_AUTOIDLE)>; 565 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 566 clock-names = "fck"; 567 resets = <&prm_dsp1 1>; 568 reset-names = "rstctrl"; 569 ranges = <0x0 0x40d02000 0x1000>; 570 #size-cells = <1>; 571 #address-cells = <1>; 572 573 mmu1_dsp1: mmu@0 { 574 compatible = "ti,dra7-dsp-iommu"; 575 reg = <0x0 0x100>; 576 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 577 #iommu-cells = <0>; 578 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 579 }; 580 }; 581 582 target-module@58882000 { 583 compatible = "ti,sysc-omap2", "ti,sysc"; 584 reg = <0x58882000 0x4>, 585 <0x58882010 0x4>, 586 <0x58882014 0x4>; 587 reg-names = "rev", "sysc", "syss"; 588 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 589 <SYSC_IDLE_NO>, 590 <SYSC_IDLE_SMART>; 591 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 592 SYSC_OMAP2_SOFTRESET | 593 SYSC_OMAP2_AUTOIDLE)>; 594 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; 595 clock-names = "fck"; 596 resets = <&prm_ipu 2>; 597 reset-names = "rstctrl"; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 ranges = <0x0 0x58882000 0x100>; 601 602 mmu_ipu1: mmu@0 { 603 compatible = "ti,dra7-iommu"; 604 reg = <0x0 0x100>; 605 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 606 #iommu-cells = <0>; 607 ti,iommu-bus-err-back; 608 }; 609 }; 610 611 target-module@55082000 { 612 compatible = "ti,sysc-omap2", "ti,sysc"; 613 reg = <0x55082000 0x4>, 614 <0x55082010 0x4>, 615 <0x55082014 0x4>; 616 reg-names = "rev", "sysc", "syss"; 617 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 618 <SYSC_IDLE_NO>, 619 <SYSC_IDLE_SMART>; 620 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 621 SYSC_OMAP2_SOFTRESET | 622 SYSC_OMAP2_AUTOIDLE)>; 623 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; 624 clock-names = "fck"; 625 resets = <&prm_core 2>; 626 reset-names = "rstctrl"; 627 #address-cells = <1>; 628 #size-cells = <1>; 629 ranges = <0x0 0x55082000 0x100>; 630 631 mmu_ipu2: mmu@0 { 632 compatible = "ti,dra7-iommu"; 633 reg = <0x0 0x100>; 634 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 635 #iommu-cells = <0>; 636 ti,iommu-bus-err-back; 637 }; 638 }; 639 640 abb_mpu: regulator-abb-mpu@4ae07ddc { 641 compatible = "ti,abb-v3"; 642 regulator-name = "abb_mpu"; 643 #address-cells = <0>; 644 #size-cells = <0>; 645 clocks = <&sys_clkin1>; 646 ti,settling-time = <50>; 647 ti,clock-cycles = <16>; 648 649 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 650 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 651 <0x4ae0c158 0x4>; 652 reg-names = "setup-address", "control-address", 653 "int-address", "efuse-address", 654 "ldo-address"; 655 ti,tranxdone-status-mask = <0x80>; 656 /* LDOVBBMPU_FBB_MUX_CTRL */ 657 ti,ldovbb-override-mask = <0x400>; 658 /* LDOVBBMPU_FBB_VSET_OUT */ 659 ti,ldovbb-vset-mask = <0x1F>; 660 661 /* 662 * NOTE: only FBB mode used but actual vset will 663 * determine final biasing 664 */ 665 ti,abb_info = < 666 /*uV ABB efuse rbb_m fbb_m vset_m*/ 667 1060000 0 0x0 0 0x02000000 0x01F00000 668 1160000 0 0x4 0 0x02000000 0x01F00000 669 1210000 0 0x8 0 0x02000000 0x01F00000 670 >; 671 }; 672 673 abb_ivahd: regulator-abb-ivahd@4ae07e34 { 674 compatible = "ti,abb-v3"; 675 regulator-name = "abb_ivahd"; 676 #address-cells = <0>; 677 #size-cells = <0>; 678 clocks = <&sys_clkin1>; 679 ti,settling-time = <50>; 680 ti,clock-cycles = <16>; 681 682 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 683 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 684 <0x4a002470 0x4>; 685 reg-names = "setup-address", "control-address", 686 "int-address", "efuse-address", 687 "ldo-address"; 688 ti,tranxdone-status-mask = <0x40000000>; 689 /* LDOVBBIVA_FBB_MUX_CTRL */ 690 ti,ldovbb-override-mask = <0x400>; 691 /* LDOVBBIVA_FBB_VSET_OUT */ 692 ti,ldovbb-vset-mask = <0x1F>; 693 694 /* 695 * NOTE: only FBB mode used but actual vset will 696 * determine final biasing 697 */ 698 ti,abb_info = < 699 /*uV ABB efuse rbb_m fbb_m vset_m*/ 700 1055000 0 0x0 0 0x02000000 0x01F00000 701 1150000 0 0x4 0 0x02000000 0x01F00000 702 1250000 0 0x8 0 0x02000000 0x01F00000 703 >; 704 }; 705 706 abb_dspeve: regulator-abb-dspeve@4ae07e30 { 707 compatible = "ti,abb-v3"; 708 regulator-name = "abb_dspeve"; 709 #address-cells = <0>; 710 #size-cells = <0>; 711 clocks = <&sys_clkin1>; 712 ti,settling-time = <50>; 713 ti,clock-cycles = <16>; 714 715 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 716 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 717 <0x4a00246c 0x4>; 718 reg-names = "setup-address", "control-address", 719 "int-address", "efuse-address", 720 "ldo-address"; 721 ti,tranxdone-status-mask = <0x20000000>; 722 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 723 ti,ldovbb-override-mask = <0x400>; 724 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 725 ti,ldovbb-vset-mask = <0x1F>; 726 727 /* 728 * NOTE: only FBB mode used but actual vset will 729 * determine final biasing 730 */ 731 ti,abb_info = < 732 /*uV ABB efuse rbb_m fbb_m vset_m*/ 733 1055000 0 0x0 0 0x02000000 0x01F00000 734 1150000 0 0x4 0 0x02000000 0x01F00000 735 1250000 0 0x8 0 0x02000000 0x01F00000 736 >; 737 }; 738 739 abb_gpu: regulator-abb-gpu@4ae07de4 { 740 compatible = "ti,abb-v3"; 741 regulator-name = "abb_gpu"; 742 #address-cells = <0>; 743 #size-cells = <0>; 744 clocks = <&sys_clkin1>; 745 ti,settling-time = <50>; 746 ti,clock-cycles = <16>; 747 748 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 749 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 750 <0x4ae0c154 0x4>; 751 reg-names = "setup-address", "control-address", 752 "int-address", "efuse-address", 753 "ldo-address"; 754 ti,tranxdone-status-mask = <0x10000000>; 755 /* LDOVBBGPU_FBB_MUX_CTRL */ 756 ti,ldovbb-override-mask = <0x400>; 757 /* LDOVBBGPU_FBB_VSET_OUT */ 758 ti,ldovbb-vset-mask = <0x1F>; 759 760 /* 761 * NOTE: only FBB mode used but actual vset will 762 * determine final biasing 763 */ 764 ti,abb_info = < 765 /*uV ABB efuse rbb_m fbb_m vset_m*/ 766 1090000 0 0x0 0 0x02000000 0x01F00000 767 1210000 0 0x4 0 0x02000000 0x01F00000 768 1280000 0 0x8 0 0x02000000 0x01F00000 769 >; 770 }; 771 772 target-module@4b300000 { 773 compatible = "ti,sysc-omap4", "ti,sysc"; 774 reg = <0x4b300000 0x4>, 775 <0x4b300010 0x4>; 776 reg-names = "rev", "sysc"; 777 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 778 <SYSC_IDLE_NO>, 779 <SYSC_IDLE_SMART>, 780 <SYSC_IDLE_SMART_WKUP>; 781 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>; 782 clock-names = "fck"; 783 #address-cells = <1>; 784 #size-cells = <1>; 785 ranges = <0x0 0x4b300000 0x1000>, 786 <0x5c000000 0x5c000000 0x4000000>; 787 788 qspi: spi@0 { 789 compatible = "ti,dra7xxx-qspi"; 790 reg = <0 0x100>, 791 <0x5c000000 0x4000000>; 792 reg-names = "qspi_base", "qspi_mmap"; 793 syscon-chipselects = <&scm_conf 0x558>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; 797 clock-names = "fck"; 798 num-cs = <4>; 799 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 800 status = "disabled"; 801 }; 802 }; 803 804 /* OCP2SCP1 */ 805 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 806 807 target-module@50000000 { 808 compatible = "ti,sysc-omap2", "ti,sysc"; 809 reg = <0x50000000 4>, 810 <0x50000010 4>, 811 <0x50000014 4>; 812 reg-names = "rev", "sysc", "syss"; 813 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 814 <SYSC_IDLE_NO>, 815 <SYSC_IDLE_SMART>; 816 ti,syss-mask = <1>; 817 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>; 818 clock-names = "fck"; 819 #address-cells = <1>; 820 #size-cells = <1>; 821 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ 822 <0x00000000 0x00000000 0x40000000>; /* data */ 823 824 gpmc: gpmc@50000000 { 825 compatible = "ti,am3352-gpmc"; 826 reg = <0x50000000 0x37c>; /* device IO registers */ 827 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 828 dmas = <&edma_xbar 4 0>; 829 dma-names = "rxtx"; 830 gpmc,num-cs = <8>; 831 gpmc,num-waitpins = <2>; 832 #address-cells = <2>; 833 #size-cells = <1>; 834 interrupt-controller; 835 #interrupt-cells = <2>; 836 gpio-controller; 837 #gpio-cells = <2>; 838 status = "disabled"; 839 }; 840 }; 841 842 target-module@56000000 { 843 compatible = "ti,sysc-omap4", "ti,sysc"; 844 reg = <0x5600fe00 0x4>, 845 <0x5600fe10 0x4>; 846 reg-names = "rev", "sysc"; 847 ti,sysc-midle = <SYSC_IDLE_FORCE>, 848 <SYSC_IDLE_NO>, 849 <SYSC_IDLE_SMART>; 850 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 851 <SYSC_IDLE_NO>, 852 <SYSC_IDLE_SMART>, 853 <SYSC_IDLE_SMART_WKUP>; 854 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; 855 clock-names = "fck"; 856 #address-cells = <1>; 857 #size-cells = <1>; 858 ranges = <0 0x56000000 0x2000000>; 859 860 gpu@0 { 861 compatible = "ti,am5728-gpu", "img,powervr-sgx544"; 862 reg = <0x0 0x10000>; /* 64kB */ 863 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 864 }; 865 }; 866 867 crossbar_mpu: crossbar@4a002a48 { 868 compatible = "ti,irq-crossbar"; 869 reg = <0x4a002a48 0x130>; 870 interrupt-controller; 871 interrupt-parent = <&wakeupgen>; 872 #interrupt-cells = <3>; 873 ti,max-irqs = <160>; 874 ti,max-crossbar-sources = <MAX_SOURCES>; 875 ti,reg-size = <2>; 876 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 877 ti,irqs-skip = <10 133 139 140>; 878 ti,irqs-safe-map = <0>; 879 }; 880 881 target-module@58000000 { 882 compatible = "ti,sysc-omap2", "ti,sysc"; 883 reg = <0x58000000 4>, 884 <0x58000014 4>; 885 reg-names = "rev", "syss"; 886 ti,syss-mask = <1>; 887 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>, 888 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 889 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>, 890 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>; 891 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; 892 #address-cells = <1>; 893 #size-cells = <1>; 894 ranges = <0 0x58000000 0x800000>; 895 896 dss: dss@0 { 897 compatible = "ti,dra7-dss"; 898 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 899 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 900 status = "disabled"; 901 /* CTRL_CORE_DSS_PLL_CONTROL */ 902 syscon-pll-ctrl = <&scm_conf 0x538>; 903 #address-cells = <1>; 904 #size-cells = <1>; 905 ranges = <0 0 0x800000>; 906 907 target-module@1000 { 908 compatible = "ti,sysc-omap2", "ti,sysc"; 909 reg = <0x1000 0x4>, 910 <0x1010 0x4>, 911 <0x1014 0x4>; 912 reg-names = "rev", "sysc", "syss"; 913 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 914 <SYSC_IDLE_NO>, 915 <SYSC_IDLE_SMART>; 916 ti,sysc-midle = <SYSC_IDLE_FORCE>, 917 <SYSC_IDLE_NO>, 918 <SYSC_IDLE_SMART>; 919 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 920 SYSC_OMAP2_ENAWAKEUP | 921 SYSC_OMAP2_SOFTRESET | 922 SYSC_OMAP2_AUTOIDLE)>; 923 ti,syss-mask = <1>; 924 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 925 clock-names = "fck"; 926 #address-cells = <1>; 927 #size-cells = <1>; 928 ranges = <0 0x1000 0x1000>; 929 930 dispc@0 { 931 compatible = "ti,dra7-dispc"; 932 reg = <0 0x1000>; 933 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 935 clock-names = "fck"; 936 /* CTRL_CORE_SMA_SW_1 */ 937 syscon-pol = <&scm_conf 0x534>; 938 }; 939 }; 940 941 target-module@40000 { 942 compatible = "ti,sysc-omap4", "ti,sysc"; 943 reg = <0x40000 0x4>, 944 <0x40010 0x4>; 945 reg-names = "rev", "sysc"; 946 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 947 <SYSC_IDLE_NO>, 948 <SYSC_IDLE_SMART>, 949 <SYSC_IDLE_SMART_WKUP>; 950 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; 951 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 952 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 953 clock-names = "fck", "dss_clk"; 954 #address-cells = <1>; 955 #size-cells = <1>; 956 ranges = <0 0x40000 0x40000>; 957 958 hdmi: encoder@0 { 959 compatible = "ti,dra7-hdmi"; 960 reg = <0 0x200>, 961 <0x200 0x80>, 962 <0x300 0x80>, 963 <0x20000 0x19000>; 964 reg-names = "wp", "pll", "phy", "core"; 965 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 966 status = "disabled"; 967 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 968 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; 969 clock-names = "fck", "sys_clk"; 970 dmas = <&sdma_xbar 76>; 971 dma-names = "audio_tx"; 972 }; 973 }; 974 }; 975 }; 976 977 target-module@59000000 { 978 compatible = "ti,sysc-omap4", "ti,sysc"; 979 reg = <0x59000020 0x4>; 980 reg-names = "rev"; 981 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; 982 clock-names = "fck"; 983 #address-cells = <1>; 984 #size-cells = <1>; 985 ranges = <0x0 0x59000000 0x1000>; 986 987 bb2d: gpu@0 { 988 compatible = "vivante,gc"; 989 reg = <0x0 0x700>; 990 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; 992 clock-names = "core"; 993 }; 994 }; 995 996 aes1_target: target-module@4b500000 { 997 compatible = "ti,sysc-omap2", "ti,sysc"; 998 reg = <0x4b500080 0x4>, 999 <0x4b500084 0x4>, 1000 <0x4b500088 0x4>; 1001 reg-names = "rev", "sysc", "syss"; 1002 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 1003 SYSC_OMAP2_AUTOIDLE)>; 1004 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1005 <SYSC_IDLE_NO>, 1006 <SYSC_IDLE_SMART>, 1007 <SYSC_IDLE_SMART_WKUP>; 1008 ti,syss-mask = <1>; 1009 /* Domains (P, C): per_pwrdm, l4sec_clkdm */ 1010 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>; 1011 clock-names = "fck"; 1012 #address-cells = <1>; 1013 #size-cells = <1>; 1014 ranges = <0x0 0x4b500000 0x1000>; 1015 1016 aes1: aes@0 { 1017 compatible = "ti,omap4-aes"; 1018 reg = <0 0xa0>; 1019 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1020 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; 1021 dma-names = "tx", "rx"; 1022 clocks = <&l3_iclk_div>; 1023 clock-names = "fck"; 1024 }; 1025 }; 1026 1027 aes2_target: target-module@4b700000 { 1028 compatible = "ti,sysc-omap2", "ti,sysc"; 1029 reg = <0x4b700080 0x4>, 1030 <0x4b700084 0x4>, 1031 <0x4b700088 0x4>; 1032 reg-names = "rev", "sysc", "syss"; 1033 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 1034 SYSC_OMAP2_AUTOIDLE)>; 1035 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1036 <SYSC_IDLE_NO>, 1037 <SYSC_IDLE_SMART>, 1038 <SYSC_IDLE_SMART_WKUP>; 1039 ti,syss-mask = <1>; 1040 /* Domains (P, C): per_pwrdm, l4sec_clkdm */ 1041 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>; 1042 clock-names = "fck"; 1043 #address-cells = <1>; 1044 #size-cells = <1>; 1045 ranges = <0x0 0x4b700000 0x1000>; 1046 1047 aes2: aes@0 { 1048 compatible = "ti,omap4-aes"; 1049 reg = <0 0xa0>; 1050 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1051 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; 1052 dma-names = "tx", "rx"; 1053 clocks = <&l3_iclk_div>; 1054 clock-names = "fck"; 1055 }; 1056 }; 1057 1058 sham1_target: target-module@4b101000 { 1059 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 1060 reg = <0x4b101100 0x4>, 1061 <0x4b101110 0x4>, 1062 <0x4b101114 0x4>; 1063 reg-names = "rev", "sysc", "syss"; 1064 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 1065 SYSC_OMAP2_AUTOIDLE)>; 1066 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1067 <SYSC_IDLE_NO>, 1068 <SYSC_IDLE_SMART>; 1069 ti,syss-mask = <1>; 1070 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 1071 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; 1072 clock-names = "fck"; 1073 #address-cells = <1>; 1074 #size-cells = <1>; 1075 ranges = <0x0 0x4b101000 0x1000>; 1076 1077 sham1: sham@0 { 1078 compatible = "ti,omap5-sham"; 1079 reg = <0 0x300>; 1080 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1081 dmas = <&edma_xbar 119 0>; 1082 dma-names = "rx"; 1083 clocks = <&l3_iclk_div>; 1084 clock-names = "fck"; 1085 }; 1086 }; 1087 1088 sham2_target: target-module@42701000 { 1089 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 1090 reg = <0x42701100 0x4>, 1091 <0x42701110 0x4>, 1092 <0x42701114 0x4>; 1093 reg-names = "rev", "sysc", "syss"; 1094 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 1095 SYSC_OMAP2_AUTOIDLE)>; 1096 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1097 <SYSC_IDLE_NO>, 1098 <SYSC_IDLE_SMART>; 1099 ti,syss-mask = <1>; 1100 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 1101 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>; 1102 clock-names = "fck"; 1103 #address-cells = <1>; 1104 #size-cells = <1>; 1105 ranges = <0x0 0x42701000 0x1000>; 1106 1107 sham2: sham@0 { 1108 compatible = "ti,omap5-sham"; 1109 reg = <0 0x300>; 1110 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 1111 dmas = <&edma_xbar 165 0>; 1112 dma-names = "rx"; 1113 clocks = <&l3_iclk_div>; 1114 clock-names = "fck"; 1115 }; 1116 }; 1117 1118 iva_hd_target: target-module@5a000000 { 1119 compatible = "ti,sysc-omap4", "ti,sysc"; 1120 reg = <0x5a05a400 0x4>, 1121 <0x5a05a410 0x4>; 1122 reg-names = "rev", "sysc"; 1123 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1124 <SYSC_IDLE_NO>, 1125 <SYSC_IDLE_SMART>; 1126 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1127 <SYSC_IDLE_NO>, 1128 <SYSC_IDLE_SMART>; 1129 power-domains = <&prm_iva>; 1130 resets = <&prm_iva 2>; 1131 reset-names = "rstctrl"; 1132 clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>; 1133 clock-names = "fck"; 1134 #address-cells = <1>; 1135 #size-cells = <1>; 1136 ranges = <0x5a000000 0x5a000000 0x1000000>, 1137 <0x5b000000 0x5b000000 0x1000000>; 1138 1139 iva { 1140 compatible = "ti,ivahd"; 1141 }; 1142 }; 1143 1144 opp_supply_mpu: opp-supply@4a003b20 { 1145 compatible = "ti,omap5-opp-supply"; 1146 reg = <0x4a003b20 0xc>; 1147 ti,efuse-settings = < 1148 /* uV offset */ 1149 1060000 0x0 1150 1160000 0x4 1151 1210000 0x8 1152 >; 1153 ti,absolute-max-voltage-uv = <1500000>; 1154 }; 1155 1156 }; 1157 1158 thermal_zones: thermal-zones { 1159 #include "omap4-cpu-thermal.dtsi" 1160 #include "omap5-gpu-thermal.dtsi" 1161 #include "omap5-core-thermal.dtsi" 1162 #include "dra7-dspeve-thermal.dtsi" 1163 #include "dra7-iva-thermal.dtsi" 1164 }; 1165 1166}; 1167 1168&cpu_thermal { 1169 polling-delay = <500>; /* milliseconds */ 1170 coefficients = <0 2000>; 1171}; 1172 1173&gpu_thermal { 1174 coefficients = <0 2000>; 1175}; 1176 1177&core_thermal { 1178 coefficients = <0 2000>; 1179}; 1180 1181&dspeve_thermal { 1182 coefficients = <0 2000>; 1183}; 1184 1185&iva_thermal { 1186 coefficients = <0 2000>; 1187}; 1188 1189&cpu_crit { 1190 temperature = <120000>; /* milli Celsius */ 1191}; 1192 1193&core_crit { 1194 temperature = <120000>; /* milli Celsius */ 1195}; 1196 1197&gpu_crit { 1198 temperature = <120000>; /* milli Celsius */ 1199}; 1200 1201&dspeve_crit { 1202 temperature = <120000>; /* milli Celsius */ 1203}; 1204 1205&iva_crit { 1206 temperature = <120000>; /* milli Celsius */ 1207}; 1208 1209#include "dra7-l4.dtsi" 1210#include "dra7xx-clocks.dtsi" 1211 1212&prm { 1213 prm_mpu: prm@300 { 1214 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1215 reg = <0x300 0x100>; 1216 #power-domain-cells = <0>; 1217 }; 1218 1219 prm_dsp1: prm@400 { 1220 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1221 reg = <0x400 0x100>; 1222 #reset-cells = <1>; 1223 #power-domain-cells = <0>; 1224 }; 1225 1226 prm_ipu: prm@500 { 1227 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1228 reg = <0x500 0x100>; 1229 #reset-cells = <1>; 1230 #power-domain-cells = <0>; 1231 }; 1232 1233 prm_coreaon: prm@628 { 1234 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1235 reg = <0x628 0xd8>; 1236 #power-domain-cells = <0>; 1237 }; 1238 1239 prm_core: prm@700 { 1240 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1241 reg = <0x700 0x100>; 1242 #reset-cells = <1>; 1243 #power-domain-cells = <0>; 1244 }; 1245 1246 prm_iva: prm@f00 { 1247 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1248 reg = <0xf00 0x100>; 1249 #reset-cells = <1>; 1250 #power-domain-cells = <0>; 1251 }; 1252 1253 prm_cam: prm@1000 { 1254 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1255 reg = <0x1000 0x100>; 1256 #power-domain-cells = <0>; 1257 }; 1258 1259 prm_dss: prm@1100 { 1260 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1261 reg = <0x1100 0x100>; 1262 #power-domain-cells = <0>; 1263 }; 1264 1265 prm_gpu: prm@1200 { 1266 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1267 reg = <0x1200 0x100>; 1268 #power-domain-cells = <0>; 1269 }; 1270 1271 prm_l3init: prm@1300 { 1272 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1273 reg = <0x1300 0x100>; 1274 #reset-cells = <1>; 1275 #power-domain-cells = <0>; 1276 }; 1277 1278 prm_l4per: prm@1400 { 1279 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1280 reg = <0x1400 0x100>; 1281 #power-domain-cells = <0>; 1282 }; 1283 1284 prm_custefuse: prm@1600 { 1285 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1286 reg = <0x1600 0x100>; 1287 #power-domain-cells = <0>; 1288 }; 1289 1290 prm_wkupaon: prm@1724 { 1291 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1292 reg = <0x1724 0x100>; 1293 #power-domain-cells = <0>; 1294 }; 1295 1296 prm_dsp2: prm@1b00 { 1297 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1298 reg = <0x1b00 0x40>; 1299 #reset-cells = <1>; 1300 #power-domain-cells = <0>; 1301 }; 1302 1303 prm_eve1: prm@1b40 { 1304 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1305 reg = <0x1b40 0x40>; 1306 #power-domain-cells = <0>; 1307 }; 1308 1309 prm_eve2: prm@1b80 { 1310 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1311 reg = <0x1b80 0x40>; 1312 #power-domain-cells = <0>; 1313 }; 1314 1315 prm_eve3: prm@1bc0 { 1316 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1317 reg = <0x1bc0 0x40>; 1318 #power-domain-cells = <0>; 1319 }; 1320 1321 prm_eve4: prm@1c00 { 1322 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1323 reg = <0x1c00 0x60>; 1324 #power-domain-cells = <0>; 1325 }; 1326 1327 prm_rtc: prm@1c60 { 1328 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1329 reg = <0x1c60 0x20>; 1330 #power-domain-cells = <0>; 1331 }; 1332 1333 prm_vpe: prm@1c80 { 1334 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; 1335 reg = <0x1c80 0x80>; 1336 #power-domain-cells = <0>; 1337 }; 1338}; 1339 1340/* Preferred always-on timer for clockevent */ 1341&timer1_target { 1342 ti,no-reset-on-init; 1343 ti,no-idle; 1344 timer@0 { 1345 assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; 1346 assigned-clock-parents = <&sys_32k_ck>; 1347 }; 1348}; 1349 1350/* Local timers, see ARM architected timer wrap erratum i940 */ 1351&timer15_target { 1352 ti,no-reset-on-init; 1353 ti,no-idle; 1354 timer@0 { 1355 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; 1356 assigned-clock-parents = <&timer_sys_clk_div>; 1357 }; 1358}; 1359 1360&timer16_target { 1361 ti,no-reset-on-init; 1362 ti,no-idle; 1363 timer@0 { 1364 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; 1365 assigned-clock-parents = <&timer_sys_clk_div>; 1366 }; 1367}; 1368