1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Device Tree Source for am3517 SoC 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include "omap3.dtsi" 9 10/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */ 11/delete-node/ &aes1_target; 12/delete-node/ &aes2_target; 13 14/ { 15 aliases { 16 serial3 = &uart4; 17 can = &hecc; 18 ethernet = &davinci_emac; 19 }; 20 21 cpus { 22 cpu: cpu@0 { 23 /* Based on OMAP3630 variants OPP50 and OPP100 */ 24 operating-points-v2 = <&cpu0_opp_table>; 25 26 clock-latency = <300000>; /* From legacy driver */ 27 }; 28 }; 29 30 cpu0_opp_table: opp-table { 31 compatible = "operating-points-v2-ti-cpu"; 32 syscon = <&scm_conf>; 33 /* 34 * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx 35 * appear to operate at 300MHz as well. Since AM3517 only 36 * lists one operating voltage, it will remain fixed at 1.2V 37 */ 38 opp-50-300000000 { 39 /* OPP50 */ 40 opp-hz = /bits/ 64 <300000000>; 41 opp-microvolt = <1200000>; 42 opp-supported-hw = <0xffffffff 0xffffffff>; 43 opp-suspend; 44 }; 45 46 opp-100-600000000 { 47 /* OPP100 */ 48 opp-hz = /bits/ 64 <600000000>; 49 opp-microvolt = <1200000>; 50 opp-supported-hw = <0xffffffff 0xffffffff>; 51 }; 52 }; 53 54 ocp@68000000 { 55 target-module@5c040000 { 56 compatible = "ti,sysc-omap2", "ti,sysc"; 57 reg = <0x5c040400 0x4>, 58 <0x5c040404 0x4>, 59 <0x5c040408 0x4>; 60 reg-names = "rev", "sysc", "syss"; 61 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 62 SYSC_OMAP2_SOFTRESET | 63 SYSC_OMAP2_AUTOIDLE)>; 64 ti,sysc-midle = <SYSC_IDLE_FORCE>, 65 <SYSC_IDLE_NO>, 66 <SYSC_IDLE_SMART>; 67 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 68 <SYSC_IDLE_NO>, 69 <SYSC_IDLE_SMART>; 70 ti,syss-mask = <1>; 71 clocks = <&hsotgusb_ick_am35xx>; 72 clock-names = "fck"; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges = <0x0 0x5c040000 0x1000>; 76 77 am35x_otg_hs: am35x_otg_hs@0 { 78 compatible = "ti,omap3-musb"; 79 status = "disabled"; 80 reg = <0 0x1000>; 81 interrupts = <71>; 82 interrupt-names = "mc"; 83 }; 84 }; 85 86 davinci_emac: ethernet@5c000000 { 87 compatible = "ti,am3517-emac"; 88 ti,hwmods = "davinci_emac"; 89 status = "disabled"; 90 reg = <0x5c000000 0x30000>; 91 interrupts = <67 68 69 70>; 92 syscon = <&scm_conf>; 93 ti,davinci-ctrl-reg-offset = <0x10000>; 94 ti,davinci-ctrl-mod-reg-offset = <0>; 95 ti,davinci-ctrl-ram-offset = <0x20000>; 96 ti,davinci-ctrl-ram-size = <0x2000>; 97 ti,davinci-rmii-en = /bits/ 8 <1>; 98 local-mac-address = [ 00 00 00 00 00 00 ]; 99 clocks = <&emac_ick>; 100 clock-names = "ick"; 101 }; 102 103 davinci_mdio: mdio@5c030000 { 104 compatible = "ti,davinci_mdio"; 105 ti,hwmods = "davinci_mdio"; 106 status = "disabled"; 107 reg = <0x5c030000 0x1000>; 108 bus_freq = <1000000>; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 clocks = <&emac_fck>; 112 clock-names = "fck"; 113 }; 114 115 uart4: serial@4809e000 { 116 compatible = "ti,omap3-uart"; 117 ti,hwmods = "uart4"; 118 status = "disabled"; 119 reg = <0x4809e000 0x400>; 120 interrupts = <84>; 121 dmas = <&sdma 55 &sdma 54>; 122 dma-names = "tx", "rx"; 123 clock-frequency = <48000000>; 124 }; 125 126 omap3_pmx_core2: pinmux@480025d8 { 127 compatible = "ti,omap3-padconf", "pinctrl-single"; 128 reg = <0x480025d8 0x24>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 #pinctrl-cells = <1>; 132 #interrupt-cells = <1>; 133 interrupt-controller; 134 pinctrl-single,register-width = <16>; 135 pinctrl-single,function-mask = <0xff1f>; 136 }; 137 138 hecc: can@5c050000 { 139 compatible = "ti,am3517-hecc"; 140 status = "disabled"; 141 reg = <0x5c050000 0x80>, 142 <0x5c053000 0x180>, 143 <0x5c052000 0x200>; 144 reg-names = "hecc", "hecc-ram", "mbx"; 145 interrupts = <24>; 146 clocks = <&hecc_ck>; 147 }; 148 149 /* 150 * On am3517 the OCP registers do not seem to be accessible 151 * similar to the omap34xx. Maybe SGX is permanently set to 152 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is 153 * write-only at 0x50000e10. We detect SGX based on the SGX 154 * revision register instead of the unreadable OCP revision 155 * register. 156 */ 157 sgx_module: target-module@50000000 { 158 compatible = "ti,sysc-omap2", "ti,sysc"; 159 reg = <0x50000014 0x4>; 160 reg-names = "rev"; 161 clocks = <&sgx_fck>, <&sgx_ick>; 162 clock-names = "fck", "ick"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges = <0 0x50000000 0x10000>; 166 167 gpu@0 { 168 compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; 169 reg = <0x0 0x10000>; /* 64kB */ 170 interrupts = <21>; 171 }; 172 }; 173 }; 174}; 175 176/* Not currently working, probably needs at least different clocks */ 177&rng_target { 178 status = "disabled"; 179 /delete-property/ clocks; 180}; 181 182/* Table Table 5-79 of the TRM shows 480ab000 is reserved */ 183&usb_otg_target { 184 status = "disabled"; 185}; 186 187&iva { 188 status = "disabled"; 189}; 190 191&mailbox { 192 status = "disabled"; 193}; 194 195&mmu_isp { 196 status = "disabled"; 197}; 198 199#include "am35xx-clocks.dtsi" 200#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" 201 202/* Preferred always-on timer for clocksource */ 203&timer1_target { 204 ti,no-reset-on-init; 205 ti,no-idle; 206 timer@0 { 207 assigned-clocks = <&gpt1_fck>; 208 assigned-clock-parents = <&sys_ck>; 209 }; 210}; 211 212/* Preferred timer for clockevent */ 213&timer2_target { 214 ti,no-reset-on-init; 215 ti,no-idle; 216 timer@0 { 217 assigned-clocks = <&gpt2_fck>; 218 assigned-clock-parents = <&sys_ck>; 219 }; 220}; 221