1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/* 7 * VScom OnRISC 8 * https://www.vscom.de 9 */ 10 11#include "am33xx.dtsi" 12#include <dt-bindings/pwm/pwm.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14 15/ { 16 compatible = "vscom,onrisc", "ti,am33xx"; 17 18 cpus { 19 cpu@0 { 20 cpu0-supply = <&vdd1_reg>; 21 }; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 reg = <0x80000000 0x10000000>; /* 256 MB */ 27 }; 28 29 vbat: fixedregulator0 { 30 compatible = "regulator-fixed"; 31 regulator-name = "vbat"; 32 regulator-min-microvolt = <5000000>; 33 regulator-max-microvolt = <5000000>; 34 regulator-boot-on; 35 }; 36 37 wl12xx_vmmc: fixedregulator2 { 38 pinctrl-names = "default"; 39 pinctrl-0 = <&wl12xx_gpio>; 40 compatible = "regulator-fixed"; 41 regulator-name = "vwl1271"; 42 regulator-min-microvolt = <3300000>; 43 regulator-max-microvolt = <3300000>; 44 gpio = <&gpio3 8 0>; 45 startup-delay-us = <70000>; 46 enable-active-high; 47 }; 48}; 49 50&am33xx_pinmux { 51 mmc2_pins: mmc2-pins { 52 pinctrl-single,pins = < 53 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ 54 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ 55 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ 56 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ 57 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ 58 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ 59 AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[7] */ 60 >; 61 }; 62 63 wl12xx_gpio: wl12xx-gpio-pins { 64 pinctrl-single,pins = < 65 AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ 66 >; 67 }; 68 69 tps65910_pins: tps65910-pins { 70 pinctrl-single,pins = < 71 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ 72 >; 73 }; 74 75 i2c1_pins: i2c1-pins { 76 pinctrl-single,pins = < 77 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ 78 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ 79 >; 80 }; 81 82 uart0_pins: uart0-pins { 83 pinctrl-single,pins = < 84 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 85 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 86 >; 87 }; 88 89 cpsw_default: cpsw-default-pins { 90 pinctrl-single,pins = < 91 /* Slave 1 */ 92 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ 93 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_tx_en.rmii1_txen */ 94 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 95 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 96 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 97 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 98 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ 99 100 101 /* Slave 2 */ 102 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ 103 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ 104 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ 105 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ 106 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ 107 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ 108 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ 109 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ 110 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ 111 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ 112 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ 113 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ 114 >; 115 }; 116 117 cpsw_sleep: cpsw-sleep-pins { 118 pinctrl-single,pins = < 119 /* Slave 1 reset value */ 120 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) 121 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 122 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 123 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 124 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 125 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 126 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 127 128 /* Slave 2 reset value*/ 129 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) 130 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) 131 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) 132 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) 133 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) 134 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) 135 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) 136 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) 137 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) 138 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) 139 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) 140 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) 141 >; 142 }; 143 144 davinci_mdio_default: davinci-mdio-default-pins { 145 pinctrl-single,pins = < 146 /* MDIO */ 147 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ 148 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_clk */ 149 >; 150 }; 151 152 davinci_mdio_sleep: davinci-mdio-sleep-pins { 153 pinctrl-single,pins = < 154 /* MDIO reset value */ 155 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 156 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 157 >; 158 }; 159 160 nandflash_pins_s0: nandflash-s0-pins { 161 pinctrl-single,pins = < 162 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 163 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 164 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 165 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 166 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 167 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 168 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 169 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 170 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 171 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ 172 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 173 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 174 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 175 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen.gpmc_wen */ 176 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 177 >; 178 }; 179}; 180 181&elm { 182 status = "okay"; 183}; 184 185&gpmc { 186 pinctrl-names = "default"; 187 pinctrl-0 = <&nandflash_pins_s0>; 188 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 189 status = "okay"; 190 191 nand@0,0 { 192 compatible = "ti,omap2-nand"; 193 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 194 interrupt-parent = <&gpmc>; 195 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 196 <1 IRQ_TYPE_NONE>; /* termcount */ 197 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 198 nand-bus-width = <8>; 199 ti,nand-ecc-opt = "bch8"; 200 ti,nand-xfer-type = "prefetch-dma"; 201 202 gpmc,device-nand = "true"; 203 gpmc,device-width = <1>; 204 gpmc,sync-clk-ps = <0>; 205 gpmc,cs-on-ns = <0>; 206 gpmc,cs-rd-off-ns = <44>; 207 gpmc,cs-wr-off-ns = <44>; 208 gpmc,adv-on-ns = <6>; 209 gpmc,adv-rd-off-ns = <34>; 210 gpmc,adv-wr-off-ns = <44>; 211 gpmc,we-on-ns = <0>; 212 gpmc,we-off-ns = <40>; 213 gpmc,oe-on-ns = <0>; 214 gpmc,oe-off-ns = <54>; 215 gpmc,access-ns = <64>; 216 gpmc,rd-cycle-ns = <82>; 217 gpmc,wr-cycle-ns = <82>; 218 gpmc,bus-turnaround-ns = <0>; 219 gpmc,cycle2cycle-delay-ns = <0>; 220 gpmc,clk-activation-ns = <0>; 221 gpmc,wr-access-ns = <40>; 222 gpmc,wr-data-mux-bus-ns = <0>; 223 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ti,elm-id = <&elm>; 227 }; 228}; 229 230&uart0 { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&uart0_pins>; 233 234 status = "okay"; 235}; 236 237&i2c1 { 238 pinctrl-names = "default"; 239 pinctrl-0 = <&i2c1_pins>; 240 241 status = "okay"; 242 clock-frequency = <400000>; 243 244 tps: tps@2d { 245 reg = <0x2d>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 interrupt-parent = <&gpio1>; 249 interrupts = <28 IRQ_TYPE_EDGE_RISING>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&tps65910_pins>; 252 }; 253 254 at24@50 { 255 compatible = "atmel,24c02"; 256 pagesize = <8>; 257 reg = <0x50>; 258 }; 259}; 260 261#include "../../tps65910.dtsi" 262 263&tps { 264 vcc1-supply = <&vbat>; 265 vcc2-supply = <&vbat>; 266 vcc3-supply = <&vbat>; 267 vcc4-supply = <&vbat>; 268 vcc5-supply = <&vbat>; 269 vcc6-supply = <&vbat>; 270 vcc7-supply = <&vbat>; 271 vccio-supply = <&vbat>; 272 273 ti,en-ck32k-xtal = <1>; 274 275 regulators { 276 vrtc_reg: regulator@0 { 277 regulator-always-on; 278 }; 279 280 vio_reg: regulator@1 { 281 regulator-always-on; 282 }; 283 284 vdd1_reg: regulator@2 { 285 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 286 regulator-name = "vdd_mpu"; 287 regulator-min-microvolt = <912500>; 288 regulator-max-microvolt = <1351500>; 289 regulator-boot-on; 290 regulator-always-on; 291 }; 292 293 vdd2_reg: regulator@3 { 294 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 295 regulator-name = "vdd_core"; 296 regulator-min-microvolt = <912500>; 297 regulator-max-microvolt = <1150000>; 298 regulator-boot-on; 299 regulator-always-on; 300 }; 301 302 vdd3_reg: regulator@4 { 303 regulator-always-on; 304 }; 305 306 vdig1_reg: regulator@5 { 307 regulator-always-on; 308 }; 309 310 vdig2_reg: regulator@6 { 311 regulator-always-on; 312 }; 313 314 vpll_reg: regulator@7 { 315 regulator-always-on; 316 }; 317 318 vdac_reg: regulator@8 { 319 regulator-always-on; 320 }; 321 322 vaux1_reg: regulator@9 { 323 regulator-always-on; 324 }; 325 326 vaux2_reg: regulator@10 { 327 regulator-always-on; 328 }; 329 330 vaux33_reg: regulator@11 { 331 regulator-always-on; 332 }; 333 334 vmmc_reg: regulator@12 { 335 regulator-min-microvolt = <1800000>; 336 regulator-max-microvolt = <3300000>; 337 regulator-always-on; 338 }; 339 }; 340}; 341 342&mac_sw { 343 pinctrl-names = "default", "sleep"; 344 pinctrl-0 = <&cpsw_default>; 345 pinctrl-1 = <&cpsw_sleep>; 346 347 status = "okay"; 348}; 349 350&davinci_mdio_sw { 351 status = "okay"; 352 pinctrl-names = "default", "sleep"; 353 pinctrl-0 = <&davinci_mdio_default>; 354 pinctrl-1 = <&davinci_mdio_sleep>; 355 356 phy1: ethernet-phy@1 { 357 reg = <7>; 358 eee-broken-100tx; 359 eee-broken-1000t; 360 }; 361}; 362 363&mmc1 { 364 vmmc-supply = <&vmmc_reg>; 365 status = "okay"; 366}; 367 368&mmc2 { 369 status = "okay"; 370 vmmc-supply = <&wl12xx_vmmc>; 371 non-removable; 372 bus-width = <4>; 373 cap-power-off-card; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&mmc2_pins>; 376 377 #address-cells = <1>; 378 #size-cells = <0>; 379 wlcore: wlcore@2 { 380 compatible = "ti,wl1835"; 381 reg = <2>; 382 interrupt-parent = <&gpio3>; 383 interrupts = <7 IRQ_TYPE_EDGE_RISING>; 384 }; 385}; 386 387&sham { 388 status = "okay"; 389}; 390 391&aes { 392 status = "okay"; 393}; 394 395&gpio0_target { 396 ti,no-reset-on-init; 397}; 398 399&gpio3_target { 400 ti,no-reset-on-init; 401}; 402