1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. 5 */ 6 7#include "stm32mp151.dtsi" 8 9/ { 10 cpus { 11 cpu1: cpu@1 { 12 compatible = "arm,cortex-a7"; 13 clock-frequency = <650000000>; 14 device_type = "cpu"; 15 reg = <1>; 16 }; 17 }; 18 19 arm-pmu { 20 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 22 interrupt-affinity = <&cpu0>, <&cpu1>; 23 }; 24 25 timer { 26 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 27 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 28 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 29 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 30 }; 31}; 32 33&cs_funnel { 34 in-ports { 35 port@2 { 36 reg = <2>; 37 funnel_in_port2: endpoint { 38 remote-endpoint = <&etm1_out>; 39 }; 40 }; 41 }; 42}; 43 44&dbg_bus { 45 cs_cti_cpu1: cti@500d9000 { 46 compatible = "arm,coresight-cti", "arm,primecell"; 47 reg = <0x500d9000 0x1000>; 48 clocks = <&rcc CK_DBG>; 49 clock-names = "apb_pclk"; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 access-controllers = <&dbg_bus 0>; 53 status = "disabled"; 54 55 trig-conns@0 { 56 reg = <0>; 57 arm,trig-in-sigs = <0 4 5>; 58 arm,trig-in-types = <PE_DBGTRIGGER 59 GEN_IO 60 GEN_IO>; 61 arm,trig-out-sigs = <0 7>; 62 arm,trig-out-types = <PE_EDBGREQ 63 PE_DBGRESTART>; 64 cpu = <&cpu1>; 65 }; 66 67 trig-conns@2 { 68 reg = <2>; 69 arm,trig-in-sigs = <2 3 6>; 70 arm,trig-in-types = <ETM_EXTOUT 71 ETM_EXTOUT 72 ETM_EXTOUT>; 73 arm,trig-out-sigs = <1 2 3 4>; 74 arm,trig-out-types = <ETM_EXTIN 75 ETM_EXTIN 76 ETM_EXTIN 77 ETM_EXTIN>; 78 arm,cs-dev-assoc = <&cs_etm1>; 79 }; 80 }; 81 82 cs_etm1: etm@500dd000 { 83 compatible = "arm,coresight-etm3x", "arm,primecell"; 84 reg = <0x500dd000 0x1000>; 85 cpu = <&cpu1>; 86 clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; 87 clock-names = "apb_pclk", "atclk"; 88 access-controllers = <&dbg_bus 0>; 89 status = "disabled"; 90 91 out-ports { 92 port { 93 etm1_out: endpoint { 94 remote-endpoint = <&funnel_in_port2>; 95 }; 96 }; 97 }; 98 }; 99}; 100 101&etzpc { 102 m_can1: can@4400e000 { 103 compatible = "bosch,m_can"; 104 reg = <0x4400e000 0x400>, <0x44011000 0x1400>; 105 reg-names = "m_can", "message_ram"; 106 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-names = "int0", "int1"; 109 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; 110 clock-names = "hclk", "cclk"; 111 resets = <&rcc FDCAN_R>; 112 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; 113 access-controllers = <&etzpc 62>; 114 status = "disabled"; 115 }; 116 117 m_can2: can@4400f000 { 118 compatible = "bosch,m_can"; 119 reg = <0x4400f000 0x400>, <0x44011000 0x2800>; 120 reg-names = "m_can", "message_ram"; 121 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 123 interrupt-names = "int0", "int1"; 124 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; 125 clock-names = "hclk", "cclk"; 126 resets = <&rcc FDCAN_R>; 127 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; 128 access-controllers = <&etzpc 62>; 129 status = "disabled"; 130 }; 131}; 132