1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. 5 */ 6 7#include "stm32mp151.dtsi" 8 9/ { 10 cpus { 11 cpu1: cpu@1 { 12 compatible = "arm,cortex-a7"; 13 clock-frequency = <650000000>; 14 device_type = "cpu"; 15 reg = <1>; 16 }; 17 }; 18 19 arm-pmu { 20 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 22 interrupt-affinity = <&cpu0>, <&cpu1>; 23 }; 24 25 timer { 26 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 27 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 28 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 29 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 30 }; 31}; 32 33&etzpc { 34 m_can1: can@4400e000 { 35 compatible = "bosch,m_can"; 36 reg = <0x4400e000 0x400>, <0x44011000 0x1400>; 37 reg-names = "m_can", "message_ram"; 38 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 40 interrupt-names = "int0", "int1"; 41 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; 42 clock-names = "hclk", "cclk"; 43 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; 44 access-controllers = <&etzpc 62>; 45 status = "disabled"; 46 }; 47 48 m_can2: can@4400f000 { 49 compatible = "bosch,m_can"; 50 reg = <0x4400f000 0x400>, <0x44011000 0x2800>; 51 reg-names = "m_can", "message_ram"; 52 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 54 interrupt-names = "int0", "int1"; 55 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; 56 clock-names = "hclk", "cclk"; 57 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; 58 access-controllers = <&etzpc 62>; 59 status = "disabled"; 60 }; 61}; 62