1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/stm32mp1-clks.h> 9#include <dt-bindings/reset/stm32mp1-resets.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 arm,no-tick-in-suspend; 55 }; 56 57 clocks { 58 clk_hse: clk-hse { 59 #clock-cells = <0>; 60 compatible = "fixed-clock"; 61 clock-frequency = <24000000>; 62 }; 63 64 clk_hsi: clk-hsi { 65 #clock-cells = <0>; 66 compatible = "fixed-clock"; 67 clock-frequency = <64000000>; 68 }; 69 70 clk_lse: clk-lse { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <32768>; 74 }; 75 76 clk_lsi: clk-lsi { 77 #clock-cells = <0>; 78 compatible = "fixed-clock"; 79 clock-frequency = <32000>; 80 }; 81 82 clk_csi: clk-csi { 83 #clock-cells = <0>; 84 compatible = "fixed-clock"; 85 clock-frequency = <4000000>; 86 }; 87 }; 88 89 thermal-zones { 90 cpu_thermal: cpu-thermal { 91 polling-delay-passive = <0>; 92 polling-delay = <0>; 93 thermal-sensors = <&dts>; 94 95 trips { 96 cpu_alert1: cpu-alert1 { 97 temperature = <85000>; 98 hysteresis = <0>; 99 type = "passive"; 100 }; 101 102 cpu-crit { 103 temperature = <120000>; 104 hysteresis = <0>; 105 type = "critical"; 106 }; 107 }; 108 109 cooling-maps { 110 }; 111 }; 112 }; 113 114 booster: regulator-booster { 115 compatible = "st,stm32mp1-booster"; 116 st,syscfg = <&syscfg>; 117 status = "disabled"; 118 }; 119 120 soc { 121 compatible = "simple-bus"; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 interrupt-parent = <&intc>; 125 ranges; 126 127 sram4: sram@10050000 { 128 compatible = "mmio-sram"; 129 reg = <0x10050000 0x10000>; 130 #address-cells = <1>; 131 #size-cells = <1>; 132 ranges = <0 0x10050000 0x10000>; 133 }; 134 135 ipcc: mailbox@4c001000 { 136 compatible = "st,stm32mp1-ipcc"; 137 #mbox-cells = <1>; 138 reg = <0x4c001000 0x400>; 139 st,proc-id = <0>; 140 interrupts-extended = 141 <&exti 61 IRQ_TYPE_LEVEL_HIGH>, 142 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 143 interrupt-names = "rx", "tx"; 144 clocks = <&rcc IPCC>; 145 wakeup-source; 146 status = "disabled"; 147 }; 148 149 rcc: rcc@50000000 { 150 compatible = "st,stm32mp1-rcc", "syscon"; 151 reg = <0x50000000 0x1000>; 152 #clock-cells = <1>; 153 #reset-cells = <1>; 154 }; 155 156 pwr_regulators: pwr@50001000 { 157 compatible = "st,stm32mp1,pwr-reg"; 158 reg = <0x50001000 0x10>; 159 160 reg11: reg11 { 161 regulator-name = "reg11"; 162 regulator-min-microvolt = <1100000>; 163 regulator-max-microvolt = <1100000>; 164 }; 165 166 reg18: reg18 { 167 regulator-name = "reg18"; 168 regulator-min-microvolt = <1800000>; 169 regulator-max-microvolt = <1800000>; 170 }; 171 172 usb33: usb33 { 173 regulator-name = "usb33"; 174 regulator-min-microvolt = <3300000>; 175 regulator-max-microvolt = <3300000>; 176 }; 177 }; 178 179 pwr_mcu: pwr_mcu@50001014 { 180 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 181 reg = <0x50001014 0x4>; 182 }; 183 184 exti: interrupt-controller@5000d000 { 185 compatible = "st,stm32mp1-exti", "syscon"; 186 interrupt-controller; 187 #interrupt-cells = <2>; 188 reg = <0x5000d000 0x400>; 189 interrupts-extended = 190 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 191 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 192 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 193 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 194 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 195 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 196 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 197 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 198 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 199 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 200 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 201 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 202 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 203 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 204 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 205 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 206 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 207 <0>, 208 <0>, 209 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 210 <0>, /* EXTI_20 */ 211 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 212 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 213 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 214 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 215 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 216 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 217 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 218 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 219 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 220 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 221 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 222 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 223 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 224 <0>, 225 <0>, 226 <0>, 227 <0>, 228 <0>, 229 <0>, 230 <0>, /* EXTI_40 */ 231 <0>, 232 <0>, 233 <0>, 234 <0>, 235 <0>, 236 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 237 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 238 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 239 <0>, 240 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 241 <0>, 242 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 243 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 244 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 245 <0>, 246 <0>, 247 <0>, 248 <0>, 249 <0>, 250 <0>, /* EXTI_60 */ 251 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 252 <0>, 253 <0>, 254 <0>, 255 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 256 <0>, 257 <0>, 258 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 259 <0>, 260 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 261 <0>, 262 <0>, 263 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 264 }; 265 266 syscfg: syscon@50020000 { 267 compatible = "st,stm32mp157-syscfg", "syscon"; 268 reg = <0x50020000 0x400>; 269 clocks = <&rcc SYSCFG>; 270 }; 271 272 dts: thermal@50028000 { 273 compatible = "st,stm32-thermal"; 274 reg = <0x50028000 0x100>; 275 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&rcc TMPSENS>; 277 clock-names = "pclk"; 278 #thermal-sensor-cells = <0>; 279 status = "disabled"; 280 }; 281 282 hdp: pinctrl@5002a000 { 283 compatible = "st,stm32mp151-hdp"; 284 reg = <0x5002a000 0x400>; 285 clocks = <&rcc HDP>; 286 access-controllers = <&dbg_bus 1>; 287 status = "disabled"; 288 }; 289 290 dbg_bus: bus@50080000 { 291 compatible = "st,stm32mp151-dbg-bus"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 #access-controller-cells = <1>; 295 ranges = <0x50080000 0x50080000 0x3f80000>, 296 <0x90000000 0x90000000 0x1000000>; 297 status = "disabled"; 298 299 cs_funnel: funnel@50091000 { 300 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 301 reg = <0x50091000 0x1000>; 302 clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; 303 clock-names = "apb_pclk", "atclk"; 304 access-controllers = <&dbg_bus 0>; 305 status = "disabled"; 306 307 in-ports { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 port@0 { 311 reg = <0>; 312 funnel_in_port0: endpoint { 313 remote-endpoint = <&stm_out_port>; 314 }; 315 }; 316 317 port@1 { 318 reg = <1>; 319 funnel_in_port1: endpoint { 320 remote-endpoint = <&etm0_out>; 321 }; 322 }; 323 }; 324 325 out-ports { 326 port { 327 funnel_out_port: endpoint { 328 remote-endpoint = <&etf_in_port>; 329 }; 330 }; 331 }; 332 }; 333 334 cs_etf: etf@50092000 { 335 compatible = "arm,coresight-tmc", "arm,primecell"; 336 reg = <0x50092000 0x1000>; 337 clocks = <&rcc CK_DBG>; 338 clock-names = "apb_pclk"; 339 access-controllers = <&dbg_bus 0>; 340 status = "disabled"; 341 342 in-ports { 343 port { 344 etf_in_port: endpoint { 345 remote-endpoint = <&funnel_out_port>; 346 }; 347 }; 348 }; 349 350 out-ports { 351 port { 352 etf_out_port: endpoint { 353 remote-endpoint = <&tpiu_in_port>; 354 }; 355 }; 356 }; 357 }; 358 359 cs_tpiu: tpiu@50093000 { 360 compatible = "arm,coresight-tpiu", "arm,primecell"; 361 reg = <0x50093000 0x1000>; 362 clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; 363 clock-names = "apb_pclk", "atclk"; 364 access-controllers = <&dbg_bus 0>; 365 status = "disabled"; 366 367 in-ports { 368 port { 369 tpiu_in_port: endpoint { 370 remote-endpoint = <&etf_out_port>; 371 }; 372 }; 373 }; 374 }; 375 376 cs_cti_trace: cti@50094000 { 377 compatible = "arm,coresight-cti", "arm,primecell"; 378 reg = <0x50094000 0x1000>; 379 clocks = <&rcc CK_DBG>; 380 clock-names = "apb_pclk"; 381 access-controllers = <&dbg_bus 0>; 382 status = "disabled"; 383 }; 384 385 cs_stm: stm@500a0000 { 386 compatible = "arm,coresight-stm", "arm,primecell"; 387 reg = <0x500a0000 0x00001000>, 388 <0x90000000 0x01000000>; 389 reg-names = "stm-base", "stm-stimulus-base"; 390 clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; 391 clock-names = "apb_pclk", "atclk"; 392 access-controllers = <&dbg_bus 0>; 393 status = "disabled"; 394 395 out-ports { 396 port { 397 stm_out_port: endpoint { 398 remote-endpoint = <&funnel_in_port0>; 399 }; 400 }; 401 }; 402 }; 403 404 cs_cti_cpu0: cti@500d8000 { 405 compatible = "arm,coresight-cti", "arm,primecell"; 406 reg = <0x500d8000 0x1000>; 407 clocks = <&rcc CK_DBG>; 408 clock-names = "apb_pclk"; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 access-controllers = <&dbg_bus 0>; 412 status = "disabled"; 413 414 trig-conns@0 { 415 reg = <0>; 416 arm,trig-in-sigs = <0 4 5>; 417 arm,trig-in-types = <PE_DBGTRIGGER 418 GEN_IO 419 GEN_IO>; 420 arm,trig-out-sigs = <0 7>; 421 arm,trig-out-types = <PE_EDBGREQ 422 PE_DBGRESTART>; 423 cpu = <&cpu0>; 424 }; 425 426 trig-conns@2 { 427 reg = <2>; 428 arm,trig-in-sigs = <2 3 6>; 429 arm,trig-in-types = <ETM_EXTOUT 430 ETM_EXTOUT 431 ETM_EXTOUT>; 432 arm,trig-out-sigs = <1 2 3 4>; 433 arm,trig-out-types = <ETM_EXTIN 434 ETM_EXTIN 435 ETM_EXTIN 436 ETM_EXTIN>; 437 arm,cs-dev-assoc = <&cs_etm0>; 438 }; 439 }; 440 441 cs_etm0: etm@500dc000 { 442 compatible = "arm,coresight-etm3x", "arm,primecell"; 443 reg = <0x500dc000 0x1000>; 444 cpu = <&cpu0>; 445 clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; 446 clock-names = "apb_pclk", "atclk"; 447 access-controllers = <&dbg_bus 0>; 448 status = "disabled"; 449 450 out-ports { 451 port { 452 etm0_out: endpoint { 453 remote-endpoint = <&funnel_in_port1>; 454 }; 455 }; 456 }; 457 }; 458 }; 459 460 mdma1: dma-controller@58000000 { 461 compatible = "st,stm32h7-mdma"; 462 reg = <0x58000000 0x1000>; 463 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&rcc MDMA>; 465 resets = <&rcc MDMA_R>; 466 #dma-cells = <5>; 467 dma-channels = <32>; 468 dma-requests = <48>; 469 }; 470 471 sdmmc1: mmc@58005000 { 472 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 473 arm,primecell-periphid = <0x00253180>; 474 reg = <0x58005000 0x1000>; 475 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&rcc SDMMC1_K>; 477 clock-names = "apb_pclk"; 478 resets = <&rcc SDMMC1_R>; 479 cap-sd-highspeed; 480 cap-mmc-highspeed; 481 max-frequency = <120000000>; 482 status = "disabled"; 483 }; 484 485 sdmmc2: mmc@58007000 { 486 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 487 arm,primecell-periphid = <0x00253180>; 488 reg = <0x58007000 0x1000>; 489 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&rcc SDMMC2_K>; 491 clock-names = "apb_pclk"; 492 resets = <&rcc SDMMC2_R>; 493 cap-sd-highspeed; 494 cap-mmc-highspeed; 495 max-frequency = <120000000>; 496 status = "disabled"; 497 }; 498 499 crc1: crc@58009000 { 500 compatible = "st,stm32f7-crc"; 501 reg = <0x58009000 0x400>; 502 clocks = <&rcc CRC1>; 503 status = "disabled"; 504 }; 505 506 usbh_ohci: usb@5800c000 { 507 compatible = "generic-ohci"; 508 reg = <0x5800c000 0x1000>; 509 clocks = <&usbphyc>, <&rcc USBH>; 510 resets = <&rcc USBH_R>; 511 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 512 phys = <&usbphyc_port0>; 513 phy-names = "usb"; 514 status = "disabled"; 515 }; 516 517 usbh_ehci: usb@5800d000 { 518 compatible = "generic-ehci"; 519 reg = <0x5800d000 0x1000>; 520 clocks = <&usbphyc>, <&rcc USBH>; 521 resets = <&rcc USBH_R>; 522 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 523 companion = <&usbh_ohci>; 524 phys = <&usbphyc_port0>; 525 phy-names = "usb"; 526 status = "disabled"; 527 }; 528 529 ltdc: display-controller@5a001000 { 530 compatible = "st,stm32-ltdc"; 531 reg = <0x5a001000 0x400>; 532 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&rcc LTDC_PX>; 535 clock-names = "lcd"; 536 resets = <&rcc LTDC_R>; 537 status = "disabled"; 538 }; 539 540 iwdg2: watchdog@5a002000 { 541 compatible = "st,stm32mp1-iwdg"; 542 reg = <0x5a002000 0x400>; 543 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 544 clock-names = "pclk", "lsi"; 545 interrupts-extended = <&exti 46 IRQ_TYPE_LEVEL_HIGH>; 546 wakeup-source; 547 status = "disabled"; 548 }; 549 550 usbphyc: usbphyc@5a006000 { 551 #address-cells = <1>; 552 #size-cells = <0>; 553 #clock-cells = <0>; 554 compatible = "st,stm32mp1-usbphyc"; 555 reg = <0x5a006000 0x1000>; 556 clocks = <&rcc USBPHY_K>; 557 resets = <&rcc USBPHY_R>; 558 vdda1v1-supply = <®11>; 559 vdda1v8-supply = <®18>; 560 status = "disabled"; 561 562 usbphyc_port0: usb-phy@0 { 563 #phy-cells = <0>; 564 reg = <0>; 565 }; 566 567 usbphyc_port1: usb-phy@1 { 568 #phy-cells = <1>; 569 reg = <1>; 570 }; 571 }; 572 573 rtc: rtc@5c004000 { 574 compatible = "st,stm32mp1-rtc"; 575 reg = <0x5c004000 0x400>; 576 clocks = <&rcc RTCAPB>, <&rcc RTC>; 577 clock-names = "pclk", "rtc_ck"; 578 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 579 status = "disabled"; 580 }; 581 582 bsec: efuse@5c005000 { 583 compatible = "st,stm32mp15-bsec"; 584 reg = <0x5c005000 0x400>; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 part_number_otp: part-number-otp@4 { 588 reg = <0x4 0x1>; 589 }; 590 vrefint: vrefin-cal@52 { 591 reg = <0x52 0x2>; 592 }; 593 ts_cal1: calib@5c { 594 reg = <0x5c 0x2>; 595 }; 596 ts_cal2: calib@5e { 597 reg = <0x5e 0x2>; 598 }; 599 }; 600 601 etzpc: bus@5c007000 { 602 compatible = "st,stm32-etzpc", "simple-bus"; 603 reg = <0x5c007000 0x400>; 604 #address-cells = <1>; 605 #size-cells = <1>; 606 #access-controller-cells = <1>; 607 ranges; 608 609 timers2: timer@40000000 { 610 #address-cells = <1>; 611 #size-cells = <0>; 612 compatible = "st,stm32-timers"; 613 reg = <0x40000000 0x400>; 614 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 615 interrupt-names = "global"; 616 clocks = <&rcc TIM2_K>; 617 clock-names = "int"; 618 dmas = <&dmamux1 18 0x400 0x1>, 619 <&dmamux1 19 0x400 0x1>, 620 <&dmamux1 20 0x400 0x1>, 621 <&dmamux1 21 0x400 0x1>, 622 <&dmamux1 22 0x400 0x1>; 623 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 624 access-controllers = <&etzpc 16>; 625 status = "disabled"; 626 627 pwm { 628 compatible = "st,stm32-pwm"; 629 #pwm-cells = <3>; 630 status = "disabled"; 631 }; 632 633 timer@1 { 634 compatible = "st,stm32h7-timer-trigger"; 635 reg = <1>; 636 status = "disabled"; 637 }; 638 639 counter { 640 compatible = "st,stm32-timer-counter"; 641 status = "disabled"; 642 }; 643 }; 644 645 timers3: timer@40001000 { 646 #address-cells = <1>; 647 #size-cells = <0>; 648 compatible = "st,stm32-timers"; 649 reg = <0x40001000 0x400>; 650 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "global"; 652 clocks = <&rcc TIM3_K>; 653 clock-names = "int"; 654 dmas = <&dmamux1 23 0x400 0x1>, 655 <&dmamux1 24 0x400 0x1>, 656 <&dmamux1 25 0x400 0x1>, 657 <&dmamux1 26 0x400 0x1>, 658 <&dmamux1 27 0x400 0x1>, 659 <&dmamux1 28 0x400 0x1>; 660 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 661 access-controllers = <&etzpc 17>; 662 status = "disabled"; 663 664 pwm { 665 compatible = "st,stm32-pwm"; 666 #pwm-cells = <3>; 667 status = "disabled"; 668 }; 669 670 timer@2 { 671 compatible = "st,stm32h7-timer-trigger"; 672 reg = <2>; 673 status = "disabled"; 674 }; 675 676 counter { 677 compatible = "st,stm32-timer-counter"; 678 status = "disabled"; 679 }; 680 }; 681 682 timers4: timer@40002000 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 compatible = "st,stm32-timers"; 686 reg = <0x40002000 0x400>; 687 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 688 interrupt-names = "global"; 689 clocks = <&rcc TIM4_K>; 690 clock-names = "int"; 691 dmas = <&dmamux1 29 0x400 0x1>, 692 <&dmamux1 30 0x400 0x1>, 693 <&dmamux1 31 0x400 0x1>, 694 <&dmamux1 32 0x400 0x1>; 695 dma-names = "ch1", "ch2", "ch3", "ch4"; 696 access-controllers = <&etzpc 18>; 697 status = "disabled"; 698 699 pwm { 700 compatible = "st,stm32-pwm"; 701 #pwm-cells = <3>; 702 status = "disabled"; 703 }; 704 705 timer@3 { 706 compatible = "st,stm32h7-timer-trigger"; 707 reg = <3>; 708 status = "disabled"; 709 }; 710 711 counter { 712 compatible = "st,stm32-timer-counter"; 713 status = "disabled"; 714 }; 715 }; 716 717 timers5: timer@40003000 { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 compatible = "st,stm32-timers"; 721 reg = <0x40003000 0x400>; 722 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 723 interrupt-names = "global"; 724 clocks = <&rcc TIM5_K>; 725 clock-names = "int"; 726 dmas = <&dmamux1 55 0x400 0x1>, 727 <&dmamux1 56 0x400 0x1>, 728 <&dmamux1 57 0x400 0x1>, 729 <&dmamux1 58 0x400 0x1>, 730 <&dmamux1 59 0x400 0x1>, 731 <&dmamux1 60 0x400 0x1>; 732 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 733 access-controllers = <&etzpc 19>; 734 status = "disabled"; 735 736 pwm { 737 compatible = "st,stm32-pwm"; 738 #pwm-cells = <3>; 739 status = "disabled"; 740 }; 741 742 timer@4 { 743 compatible = "st,stm32h7-timer-trigger"; 744 reg = <4>; 745 status = "disabled"; 746 }; 747 748 counter { 749 compatible = "st,stm32-timer-counter"; 750 status = "disabled"; 751 }; 752 }; 753 754 timers6: timer@40004000 { 755 #address-cells = <1>; 756 #size-cells = <0>; 757 compatible = "st,stm32-timers"; 758 reg = <0x40004000 0x400>; 759 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 760 interrupt-names = "global"; 761 clocks = <&rcc TIM6_K>; 762 clock-names = "int"; 763 dmas = <&dmamux1 69 0x400 0x1>; 764 dma-names = "up"; 765 access-controllers = <&etzpc 20>; 766 status = "disabled"; 767 768 counter { 769 compatible = "st,stm32-timer-counter"; 770 status = "disabled"; 771 }; 772 773 timer@5 { 774 compatible = "st,stm32h7-timer-trigger"; 775 reg = <5>; 776 status = "disabled"; 777 }; 778 }; 779 780 timers7: timer@40005000 { 781 #address-cells = <1>; 782 #size-cells = <0>; 783 compatible = "st,stm32-timers"; 784 reg = <0x40005000 0x400>; 785 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 786 interrupt-names = "global"; 787 clocks = <&rcc TIM7_K>; 788 clock-names = "int"; 789 dmas = <&dmamux1 70 0x400 0x1>; 790 dma-names = "up"; 791 access-controllers = <&etzpc 21>; 792 status = "disabled"; 793 794 counter { 795 compatible = "st,stm32-timer-counter"; 796 status = "disabled"; 797 }; 798 799 timer@6 { 800 compatible = "st,stm32h7-timer-trigger"; 801 reg = <6>; 802 status = "disabled"; 803 }; 804 }; 805 806 timers12: timer@40006000 { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 compatible = "st,stm32-timers"; 810 reg = <0x40006000 0x400>; 811 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 812 interrupt-names = "global"; 813 clocks = <&rcc TIM12_K>; 814 clock-names = "int"; 815 access-controllers = <&etzpc 22>; 816 status = "disabled"; 817 818 counter { 819 compatible = "st,stm32-timer-counter"; 820 status = "disabled"; 821 }; 822 823 pwm { 824 compatible = "st,stm32-pwm"; 825 #pwm-cells = <3>; 826 status = "disabled"; 827 }; 828 829 timer@11 { 830 compatible = "st,stm32h7-timer-trigger"; 831 reg = <11>; 832 status = "disabled"; 833 }; 834 }; 835 836 timers13: timer@40007000 { 837 #address-cells = <1>; 838 #size-cells = <0>; 839 compatible = "st,stm32-timers"; 840 reg = <0x40007000 0x400>; 841 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 842 interrupt-names = "global"; 843 clocks = <&rcc TIM13_K>; 844 clock-names = "int"; 845 access-controllers = <&etzpc 23>; 846 status = "disabled"; 847 848 counter { 849 compatible = "st,stm32-timer-counter"; 850 status = "disabled"; 851 }; 852 853 pwm { 854 compatible = "st,stm32-pwm"; 855 #pwm-cells = <3>; 856 status = "disabled"; 857 }; 858 859 timer@12 { 860 compatible = "st,stm32h7-timer-trigger"; 861 reg = <12>; 862 status = "disabled"; 863 }; 864 }; 865 866 timers14: timer@40008000 { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 compatible = "st,stm32-timers"; 870 reg = <0x40008000 0x400>; 871 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 872 interrupt-names = "global"; 873 clocks = <&rcc TIM14_K>; 874 clock-names = "int"; 875 access-controllers = <&etzpc 24>; 876 status = "disabled"; 877 878 counter { 879 compatible = "st,stm32-timer-counter"; 880 status = "disabled"; 881 }; 882 883 pwm { 884 compatible = "st,stm32-pwm"; 885 #pwm-cells = <3>; 886 status = "disabled"; 887 }; 888 889 timer@13 { 890 compatible = "st,stm32h7-timer-trigger"; 891 reg = <13>; 892 status = "disabled"; 893 }; 894 }; 895 896 lptimer1: timer@40009000 { 897 #address-cells = <1>; 898 #size-cells = <0>; 899 compatible = "st,stm32-lptimer"; 900 reg = <0x40009000 0x400>; 901 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&rcc LPTIM1_K>; 903 clock-names = "mux"; 904 wakeup-source; 905 access-controllers = <&etzpc 25>; 906 status = "disabled"; 907 908 pwm { 909 compatible = "st,stm32-pwm-lp"; 910 #pwm-cells = <3>; 911 status = "disabled"; 912 }; 913 914 trigger@0 { 915 compatible = "st,stm32-lptimer-trigger"; 916 reg = <0>; 917 status = "disabled"; 918 }; 919 920 counter { 921 compatible = "st,stm32-lptimer-counter"; 922 status = "disabled"; 923 }; 924 }; 925 926 i2s2: audio-controller@4000b000 { 927 compatible = "st,stm32h7-i2s"; 928 #sound-dai-cells = <0>; 929 reg = <0x4000b000 0x400>; 930 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 931 dmas = <&dmamux1 39 0x400 0x01>, 932 <&dmamux1 40 0x400 0x01>; 933 dma-names = "rx", "tx"; 934 access-controllers = <&etzpc 27>; 935 status = "disabled"; 936 }; 937 938 spi2: spi@4000b000 { 939 #address-cells = <1>; 940 #size-cells = <0>; 941 compatible = "st,stm32h7-spi"; 942 reg = <0x4000b000 0x400>; 943 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&rcc SPI2_K>; 945 resets = <&rcc SPI2_R>; 946 dmas = <&dmamux1 39 0x400 0x05>, 947 <&dmamux1 40 0x400 0x05>; 948 dma-names = "rx", "tx"; 949 access-controllers = <&etzpc 27>; 950 status = "disabled"; 951 }; 952 953 i2s3: audio-controller@4000c000 { 954 compatible = "st,stm32h7-i2s"; 955 #sound-dai-cells = <0>; 956 reg = <0x4000c000 0x400>; 957 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 958 dmas = <&dmamux1 61 0x400 0x01>, 959 <&dmamux1 62 0x400 0x01>; 960 dma-names = "rx", "tx"; 961 access-controllers = <&etzpc 28>; 962 status = "disabled"; 963 }; 964 965 spi3: spi@4000c000 { 966 #address-cells = <1>; 967 #size-cells = <0>; 968 compatible = "st,stm32h7-spi"; 969 reg = <0x4000c000 0x400>; 970 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&rcc SPI3_K>; 972 resets = <&rcc SPI3_R>; 973 dmas = <&dmamux1 61 0x400 0x05>, 974 <&dmamux1 62 0x400 0x05>; 975 dma-names = "rx", "tx"; 976 access-controllers = <&etzpc 28>; 977 status = "disabled"; 978 }; 979 980 spdifrx: audio-controller@4000d000 { 981 compatible = "st,stm32h7-spdifrx"; 982 #sound-dai-cells = <0>; 983 reg = <0x4000d000 0x400>; 984 clocks = <&rcc SPDIF_K>; 985 clock-names = "kclk"; 986 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 987 dmas = <&dmamux1 93 0x400 0x01>, 988 <&dmamux1 94 0x400 0x01>; 989 dma-names = "rx", "rx-ctrl"; 990 access-controllers = <&etzpc 29>; 991 status = "disabled"; 992 }; 993 994 usart2: serial@4000e000 { 995 compatible = "st,stm32h7-uart"; 996 reg = <0x4000e000 0x400>; 997 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&rcc USART2_K>; 999 wakeup-source; 1000 dmas = <&dmamux1 43 0x400 0x15>, 1001 <&dmamux1 44 0x400 0x11>; 1002 dma-names = "rx", "tx"; 1003 access-controllers = <&etzpc 30>; 1004 status = "disabled"; 1005 }; 1006 1007 usart3: serial@4000f000 { 1008 compatible = "st,stm32h7-uart"; 1009 reg = <0x4000f000 0x400>; 1010 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&rcc USART3_K>; 1012 wakeup-source; 1013 dmas = <&dmamux1 45 0x400 0x15>, 1014 <&dmamux1 46 0x400 0x11>; 1015 dma-names = "rx", "tx"; 1016 access-controllers = <&etzpc 31>; 1017 status = "disabled"; 1018 }; 1019 1020 uart4: serial@40010000 { 1021 compatible = "st,stm32h7-uart"; 1022 reg = <0x40010000 0x400>; 1023 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&rcc UART4_K>; 1025 wakeup-source; 1026 dmas = <&dmamux1 63 0x400 0x15>, 1027 <&dmamux1 64 0x400 0x11>; 1028 dma-names = "rx", "tx"; 1029 access-controllers = <&etzpc 32>; 1030 status = "disabled"; 1031 }; 1032 1033 uart5: serial@40011000 { 1034 compatible = "st,stm32h7-uart"; 1035 reg = <0x40011000 0x400>; 1036 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&rcc UART5_K>; 1038 wakeup-source; 1039 dmas = <&dmamux1 65 0x400 0x15>, 1040 <&dmamux1 66 0x400 0x11>; 1041 dma-names = "rx", "tx"; 1042 access-controllers = <&etzpc 33>; 1043 status = "disabled"; 1044 }; 1045 1046 i2c1: i2c@40012000 { 1047 compatible = "st,stm32mp15-i2c"; 1048 reg = <0x40012000 0x400>; 1049 interrupt-names = "event", "error"; 1050 interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>, 1051 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&rcc I2C1_K>; 1053 resets = <&rcc I2C1_R>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 dmas = <&dmamux1 33 0x400 0x1>, 1057 <&dmamux1 34 0x400 0x1>; 1058 dma-names = "rx", "tx"; 1059 st,syscfg-fmp = <&syscfg 0x4 0x1>; 1060 wakeup-source; 1061 i2c-analog-filter; 1062 access-controllers = <&etzpc 34>; 1063 status = "disabled"; 1064 }; 1065 1066 i2c2: i2c@40013000 { 1067 compatible = "st,stm32mp15-i2c"; 1068 reg = <0x40013000 0x400>; 1069 interrupt-names = "event", "error"; 1070 interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, 1071 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&rcc I2C2_K>; 1073 resets = <&rcc I2C2_R>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 dmas = <&dmamux1 35 0x400 0x1>, 1077 <&dmamux1 36 0x400 0x1>; 1078 dma-names = "rx", "tx"; 1079 st,syscfg-fmp = <&syscfg 0x4 0x2>; 1080 wakeup-source; 1081 i2c-analog-filter; 1082 access-controllers = <&etzpc 35>; 1083 status = "disabled"; 1084 }; 1085 1086 i2c3: i2c@40014000 { 1087 compatible = "st,stm32mp15-i2c"; 1088 reg = <0x40014000 0x400>; 1089 interrupt-names = "event", "error"; 1090 interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, 1091 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&rcc I2C3_K>; 1093 resets = <&rcc I2C3_R>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 dmas = <&dmamux1 73 0x400 0x1>, 1097 <&dmamux1 74 0x400 0x1>; 1098 dma-names = "rx", "tx"; 1099 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1100 wakeup-source; 1101 i2c-analog-filter; 1102 access-controllers = <&etzpc 36>; 1103 status = "disabled"; 1104 }; 1105 1106 i2c5: i2c@40015000 { 1107 compatible = "st,stm32mp15-i2c"; 1108 reg = <0x40015000 0x400>; 1109 interrupt-names = "event", "error"; 1110 interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, 1111 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&rcc I2C5_K>; 1113 resets = <&rcc I2C5_R>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 dmas = <&dmamux1 115 0x400 0x1>, 1117 <&dmamux1 116 0x400 0x1>; 1118 dma-names = "rx", "tx"; 1119 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1120 wakeup-source; 1121 i2c-analog-filter; 1122 access-controllers = <&etzpc 37>; 1123 status = "disabled"; 1124 }; 1125 1126 cec: cec@40016000 { 1127 compatible = "st,stm32-cec"; 1128 reg = <0x40016000 0x400>; 1129 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&rcc CEC_K>, <&rcc CEC>; 1131 clock-names = "cec", "hdmi-cec"; 1132 access-controllers = <&etzpc 38>; 1133 status = "disabled"; 1134 }; 1135 1136 dac: dac@40017000 { 1137 compatible = "st,stm32h7-dac-core"; 1138 reg = <0x40017000 0x400>; 1139 clocks = <&rcc DAC12>; 1140 clock-names = "pclk"; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 access-controllers = <&etzpc 39>; 1144 status = "disabled"; 1145 1146 dac1: dac@1 { 1147 compatible = "st,stm32-dac"; 1148 #io-channel-cells = <1>; 1149 reg = <1>; 1150 status = "disabled"; 1151 }; 1152 1153 dac2: dac@2 { 1154 compatible = "st,stm32-dac"; 1155 #io-channel-cells = <1>; 1156 reg = <2>; 1157 status = "disabled"; 1158 }; 1159 }; 1160 1161 uart7: serial@40018000 { 1162 compatible = "st,stm32h7-uart"; 1163 reg = <0x40018000 0x400>; 1164 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&rcc UART7_K>; 1166 wakeup-source; 1167 dmas = <&dmamux1 79 0x400 0x15>, 1168 <&dmamux1 80 0x400 0x11>; 1169 dma-names = "rx", "tx"; 1170 access-controllers = <&etzpc 40>; 1171 status = "disabled"; 1172 }; 1173 1174 uart8: serial@40019000 { 1175 compatible = "st,stm32h7-uart"; 1176 reg = <0x40019000 0x400>; 1177 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&rcc UART8_K>; 1179 wakeup-source; 1180 dmas = <&dmamux1 81 0x400 0x15>, 1181 <&dmamux1 82 0x400 0x11>; 1182 dma-names = "rx", "tx"; 1183 access-controllers = <&etzpc 41>; 1184 status = "disabled"; 1185 }; 1186 1187 timers1: timer@44000000 { 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 compatible = "st,stm32-timers"; 1191 reg = <0x44000000 0x400>; 1192 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1196 interrupt-names = "brk", "up", "trg-com", "cc"; 1197 clocks = <&rcc TIM1_K>; 1198 clock-names = "int"; 1199 dmas = <&dmamux1 11 0x400 0x1>, 1200 <&dmamux1 12 0x400 0x1>, 1201 <&dmamux1 13 0x400 0x1>, 1202 <&dmamux1 14 0x400 0x1>, 1203 <&dmamux1 15 0x400 0x1>, 1204 <&dmamux1 16 0x400 0x1>, 1205 <&dmamux1 17 0x400 0x1>; 1206 dma-names = "ch1", "ch2", "ch3", "ch4", 1207 "up", "trig", "com"; 1208 access-controllers = <&etzpc 48>; 1209 status = "disabled"; 1210 1211 pwm { 1212 compatible = "st,stm32-pwm"; 1213 #pwm-cells = <3>; 1214 status = "disabled"; 1215 }; 1216 1217 timer@0 { 1218 compatible = "st,stm32h7-timer-trigger"; 1219 reg = <0>; 1220 status = "disabled"; 1221 }; 1222 1223 counter { 1224 compatible = "st,stm32-timer-counter"; 1225 status = "disabled"; 1226 }; 1227 }; 1228 1229 timers8: timer@44001000 { 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 compatible = "st,stm32-timers"; 1233 reg = <0x44001000 0x400>; 1234 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1238 interrupt-names = "brk", "up", "trg-com", "cc"; 1239 clocks = <&rcc TIM8_K>; 1240 clock-names = "int"; 1241 dmas = <&dmamux1 47 0x400 0x1>, 1242 <&dmamux1 48 0x400 0x1>, 1243 <&dmamux1 49 0x400 0x1>, 1244 <&dmamux1 50 0x400 0x1>, 1245 <&dmamux1 51 0x400 0x1>, 1246 <&dmamux1 52 0x400 0x1>, 1247 <&dmamux1 53 0x400 0x1>; 1248 dma-names = "ch1", "ch2", "ch3", "ch4", 1249 "up", "trig", "com"; 1250 access-controllers = <&etzpc 49>; 1251 status = "disabled"; 1252 1253 pwm { 1254 compatible = "st,stm32-pwm"; 1255 #pwm-cells = <3>; 1256 status = "disabled"; 1257 }; 1258 1259 timer@7 { 1260 compatible = "st,stm32h7-timer-trigger"; 1261 reg = <7>; 1262 status = "disabled"; 1263 }; 1264 1265 counter { 1266 compatible = "st,stm32-timer-counter"; 1267 status = "disabled"; 1268 }; 1269 }; 1270 1271 usart6: serial@44003000 { 1272 compatible = "st,stm32h7-uart"; 1273 reg = <0x44003000 0x400>; 1274 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&rcc USART6_K>; 1276 wakeup-source; 1277 dmas = <&dmamux1 71 0x400 0x15>, 1278 <&dmamux1 72 0x400 0x11>; 1279 dma-names = "rx", "tx"; 1280 access-controllers = <&etzpc 51>; 1281 status = "disabled"; 1282 }; 1283 1284 i2s1: audio-controller@44004000 { 1285 compatible = "st,stm32h7-i2s"; 1286 #sound-dai-cells = <0>; 1287 reg = <0x44004000 0x400>; 1288 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1289 dmas = <&dmamux1 37 0x400 0x01>, 1290 <&dmamux1 38 0x400 0x01>; 1291 dma-names = "rx", "tx"; 1292 access-controllers = <&etzpc 52>; 1293 status = "disabled"; 1294 }; 1295 1296 spi1: spi@44004000 { 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 compatible = "st,stm32h7-spi"; 1300 reg = <0x44004000 0x400>; 1301 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1302 clocks = <&rcc SPI1_K>; 1303 resets = <&rcc SPI1_R>; 1304 dmas = <&dmamux1 37 0x400 0x05>, 1305 <&dmamux1 38 0x400 0x05>; 1306 dma-names = "rx", "tx"; 1307 access-controllers = <&etzpc 52>; 1308 status = "disabled"; 1309 }; 1310 1311 spi4: spi@44005000 { 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 compatible = "st,stm32h7-spi"; 1315 reg = <0x44005000 0x400>; 1316 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&rcc SPI4_K>; 1318 resets = <&rcc SPI4_R>; 1319 dmas = <&dmamux1 83 0x400 0x05>, 1320 <&dmamux1 84 0x400 0x05>; 1321 dma-names = "rx", "tx"; 1322 access-controllers = <&etzpc 53>; 1323 status = "disabled"; 1324 }; 1325 1326 timers15: timer@44006000 { 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 compatible = "st,stm32-timers"; 1330 reg = <0x44006000 0x400>; 1331 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1332 interrupt-names = "global"; 1333 clocks = <&rcc TIM15_K>; 1334 clock-names = "int"; 1335 dmas = <&dmamux1 105 0x400 0x1>, 1336 <&dmamux1 106 0x400 0x1>, 1337 <&dmamux1 107 0x400 0x1>, 1338 <&dmamux1 108 0x400 0x1>; 1339 dma-names = "ch1", "up", "trig", "com"; 1340 access-controllers = <&etzpc 54>; 1341 status = "disabled"; 1342 1343 counter { 1344 compatible = "st,stm32-timer-counter"; 1345 status = "disabled"; 1346 }; 1347 1348 pwm { 1349 compatible = "st,stm32-pwm"; 1350 #pwm-cells = <3>; 1351 status = "disabled"; 1352 }; 1353 1354 timer@14 { 1355 compatible = "st,stm32h7-timer-trigger"; 1356 reg = <14>; 1357 status = "disabled"; 1358 }; 1359 }; 1360 1361 timers16: timer@44007000 { 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 compatible = "st,stm32-timers"; 1365 reg = <0x44007000 0x400>; 1366 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1367 interrupt-names = "global"; 1368 clocks = <&rcc TIM16_K>; 1369 clock-names = "int"; 1370 dmas = <&dmamux1 109 0x400 0x1>, 1371 <&dmamux1 110 0x400 0x1>; 1372 dma-names = "ch1", "up"; 1373 access-controllers = <&etzpc 55>; 1374 status = "disabled"; 1375 1376 counter { 1377 compatible = "st,stm32-timer-counter"; 1378 status = "disabled"; 1379 }; 1380 1381 pwm { 1382 compatible = "st,stm32-pwm"; 1383 #pwm-cells = <3>; 1384 status = "disabled"; 1385 }; 1386 1387 timer@15 { 1388 compatible = "st,stm32h7-timer-trigger"; 1389 reg = <15>; 1390 status = "disabled"; 1391 }; 1392 }; 1393 1394 timers17: timer@44008000 { 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 compatible = "st,stm32-timers"; 1398 reg = <0x44008000 0x400>; 1399 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1400 interrupt-names = "global"; 1401 clocks = <&rcc TIM17_K>; 1402 clock-names = "int"; 1403 dmas = <&dmamux1 111 0x400 0x1>, 1404 <&dmamux1 112 0x400 0x1>; 1405 dma-names = "ch1", "up"; 1406 access-controllers = <&etzpc 56>; 1407 status = "disabled"; 1408 1409 counter { 1410 compatible = "st,stm32-timer-counter"; 1411 status = "disabled"; 1412 }; 1413 1414 pwm { 1415 compatible = "st,stm32-pwm"; 1416 #pwm-cells = <3>; 1417 status = "disabled"; 1418 }; 1419 1420 timer@16 { 1421 compatible = "st,stm32h7-timer-trigger"; 1422 reg = <16>; 1423 status = "disabled"; 1424 }; 1425 }; 1426 1427 spi5: spi@44009000 { 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 compatible = "st,stm32h7-spi"; 1431 reg = <0x44009000 0x400>; 1432 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&rcc SPI5_K>; 1434 resets = <&rcc SPI5_R>; 1435 dmas = <&dmamux1 85 0x400 0x05>, 1436 <&dmamux1 86 0x400 0x05>; 1437 dma-names = "rx", "tx"; 1438 access-controllers = <&etzpc 57>; 1439 status = "disabled"; 1440 }; 1441 1442 sai1: sai@4400a000 { 1443 compatible = "st,stm32h7-sai"; 1444 #address-cells = <1>; 1445 #size-cells = <1>; 1446 ranges = <0 0x4400a000 0x400>; 1447 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1448 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1449 resets = <&rcc SAI1_R>; 1450 access-controllers = <&etzpc 58>; 1451 status = "disabled"; 1452 1453 sai1a: audio-controller@4400a004 { 1454 #sound-dai-cells = <0>; 1455 1456 compatible = "st,stm32-sai-sub-a"; 1457 reg = <0x4 0x20>; 1458 clocks = <&rcc SAI1_K>; 1459 clock-names = "sai_ck"; 1460 dmas = <&dmamux1 87 0x400 0x01>; 1461 status = "disabled"; 1462 }; 1463 1464 sai1b: audio-controller@4400a024 { 1465 #sound-dai-cells = <0>; 1466 compatible = "st,stm32-sai-sub-b"; 1467 reg = <0x24 0x20>; 1468 clocks = <&rcc SAI1_K>; 1469 clock-names = "sai_ck"; 1470 dmas = <&dmamux1 88 0x400 0x01>; 1471 status = "disabled"; 1472 }; 1473 }; 1474 1475 sai2: sai@4400b000 { 1476 compatible = "st,stm32h7-sai"; 1477 #address-cells = <1>; 1478 #size-cells = <1>; 1479 ranges = <0 0x4400b000 0x400>; 1480 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1481 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1482 resets = <&rcc SAI2_R>; 1483 access-controllers = <&etzpc 59>; 1484 status = "disabled"; 1485 1486 sai2a: audio-controller@4400b004 { 1487 #sound-dai-cells = <0>; 1488 compatible = "st,stm32-sai-sub-a"; 1489 reg = <0x4 0x20>; 1490 clocks = <&rcc SAI2_K>; 1491 clock-names = "sai_ck"; 1492 dmas = <&dmamux1 89 0x400 0x01>; 1493 status = "disabled"; 1494 }; 1495 1496 sai2b: audio-controller@4400b024 { 1497 #sound-dai-cells = <0>; 1498 compatible = "st,stm32-sai-sub-b"; 1499 reg = <0x24 0x20>; 1500 clocks = <&rcc SAI2_K>; 1501 clock-names = "sai_ck"; 1502 dmas = <&dmamux1 90 0x400 0x01>; 1503 status = "disabled"; 1504 }; 1505 }; 1506 1507 sai3: sai@4400c000 { 1508 compatible = "st,stm32h7-sai"; 1509 #address-cells = <1>; 1510 #size-cells = <1>; 1511 ranges = <0 0x4400c000 0x400>; 1512 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1513 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1514 resets = <&rcc SAI3_R>; 1515 access-controllers = <&etzpc 60>; 1516 status = "disabled"; 1517 1518 sai3a: audio-controller@4400c004 { 1519 #sound-dai-cells = <0>; 1520 compatible = "st,stm32-sai-sub-a"; 1521 reg = <0x04 0x20>; 1522 clocks = <&rcc SAI3_K>; 1523 clock-names = "sai_ck"; 1524 dmas = <&dmamux1 113 0x400 0x01>; 1525 status = "disabled"; 1526 }; 1527 1528 sai3b: audio-controller@4400c024 { 1529 #sound-dai-cells = <0>; 1530 compatible = "st,stm32-sai-sub-b"; 1531 reg = <0x24 0x20>; 1532 clocks = <&rcc SAI3_K>; 1533 clock-names = "sai_ck"; 1534 dmas = <&dmamux1 114 0x400 0x01>; 1535 status = "disabled"; 1536 }; 1537 }; 1538 1539 dfsdm: dfsdm@4400d000 { 1540 compatible = "st,stm32mp1-dfsdm"; 1541 reg = <0x4400d000 0x800>; 1542 clocks = <&rcc DFSDM_K>; 1543 clock-names = "dfsdm"; 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 access-controllers = <&etzpc 61>; 1547 status = "disabled"; 1548 1549 dfsdm0: filter@0 { 1550 compatible = "st,stm32-dfsdm-adc"; 1551 #io-channel-cells = <1>; 1552 reg = <0>; 1553 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1554 dmas = <&dmamux1 101 0x400 0x01>; 1555 dma-names = "rx"; 1556 status = "disabled"; 1557 }; 1558 1559 dfsdm1: filter@1 { 1560 compatible = "st,stm32-dfsdm-adc"; 1561 #io-channel-cells = <1>; 1562 reg = <1>; 1563 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1564 dmas = <&dmamux1 102 0x400 0x01>; 1565 dma-names = "rx"; 1566 status = "disabled"; 1567 }; 1568 1569 dfsdm2: filter@2 { 1570 compatible = "st,stm32-dfsdm-adc"; 1571 #io-channel-cells = <1>; 1572 reg = <2>; 1573 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1574 dmas = <&dmamux1 103 0x400 0x01>; 1575 dma-names = "rx"; 1576 status = "disabled"; 1577 }; 1578 1579 dfsdm3: filter@3 { 1580 compatible = "st,stm32-dfsdm-adc"; 1581 #io-channel-cells = <1>; 1582 reg = <3>; 1583 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1584 dmas = <&dmamux1 104 0x400 0x01>; 1585 dma-names = "rx"; 1586 status = "disabled"; 1587 }; 1588 1589 dfsdm4: filter@4 { 1590 compatible = "st,stm32-dfsdm-adc"; 1591 #io-channel-cells = <1>; 1592 reg = <4>; 1593 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1594 dmas = <&dmamux1 91 0x400 0x01>; 1595 dma-names = "rx"; 1596 status = "disabled"; 1597 }; 1598 1599 dfsdm5: filter@5 { 1600 compatible = "st,stm32-dfsdm-adc"; 1601 #io-channel-cells = <1>; 1602 reg = <5>; 1603 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1604 dmas = <&dmamux1 92 0x400 0x01>; 1605 dma-names = "rx"; 1606 status = "disabled"; 1607 }; 1608 }; 1609 1610 dma1: dma-controller@48000000 { 1611 compatible = "st,stm32-dma"; 1612 reg = <0x48000000 0x400>; 1613 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1621 clocks = <&rcc DMA1>; 1622 resets = <&rcc DMA1_R>; 1623 #dma-cells = <4>; 1624 st,mem2mem; 1625 dma-requests = <8>; 1626 access-controllers = <&etzpc 88>; 1627 }; 1628 1629 dma2: dma-controller@48001000 { 1630 compatible = "st,stm32-dma"; 1631 reg = <0x48001000 0x400>; 1632 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1640 clocks = <&rcc DMA2>; 1641 resets = <&rcc DMA2_R>; 1642 #dma-cells = <4>; 1643 st,mem2mem; 1644 dma-requests = <8>; 1645 access-controllers = <&etzpc 89>; 1646 }; 1647 1648 dmamux1: dma-router@48002000 { 1649 compatible = "st,stm32h7-dmamux"; 1650 reg = <0x48002000 0x40>; 1651 #dma-cells = <3>; 1652 dma-requests = <128>; 1653 dma-masters = <&dma1 &dma2>; 1654 dma-channels = <16>; 1655 clocks = <&rcc DMAMUX>; 1656 resets = <&rcc DMAMUX_R>; 1657 access-controllers = <&etzpc 90>; 1658 }; 1659 1660 adc: adc@48003000 { 1661 compatible = "st,stm32mp1-adc-core"; 1662 reg = <0x48003000 0x400>; 1663 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1666 clock-names = "bus", "adc"; 1667 interrupt-controller; 1668 st,syscfg = <&syscfg>; 1669 #interrupt-cells = <1>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 access-controllers = <&etzpc 72>; 1673 status = "disabled"; 1674 1675 adc1: adc@0 { 1676 compatible = "st,stm32mp1-adc"; 1677 #io-channel-cells = <1>; 1678 #address-cells = <1>; 1679 #size-cells = <0>; 1680 reg = <0x0>; 1681 interrupt-parent = <&adc>; 1682 interrupts = <0>; 1683 dmas = <&dmamux1 9 0x400 0x01>; 1684 dma-names = "rx"; 1685 status = "disabled"; 1686 }; 1687 1688 adc2: adc@100 { 1689 compatible = "st,stm32mp1-adc"; 1690 #io-channel-cells = <1>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 reg = <0x100>; 1694 interrupt-parent = <&adc>; 1695 interrupts = <1>; 1696 dmas = <&dmamux1 10 0x400 0x01>; 1697 dma-names = "rx"; 1698 nvmem-cells = <&vrefint>; 1699 nvmem-cell-names = "vrefint"; 1700 status = "disabled"; 1701 channel@13 { 1702 reg = <13>; 1703 label = "vrefint"; 1704 }; 1705 channel@14 { 1706 reg = <14>; 1707 label = "vddcore"; 1708 }; 1709 }; 1710 }; 1711 1712 sdmmc3: mmc@48004000 { 1713 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1714 arm,primecell-periphid = <0x00253180>; 1715 reg = <0x48004000 0x400>; 1716 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1717 clocks = <&rcc SDMMC3_K>; 1718 clock-names = "apb_pclk"; 1719 resets = <&rcc SDMMC3_R>; 1720 cap-sd-highspeed; 1721 cap-mmc-highspeed; 1722 max-frequency = <120000000>; 1723 access-controllers = <&etzpc 86>; 1724 status = "disabled"; 1725 }; 1726 1727 usbotg_hs: usb-otg@49000000 { 1728 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1729 reg = <0x49000000 0x10000>; 1730 clocks = <&rcc USBO_K>, <&usbphyc>; 1731 clock-names = "otg", "utmi"; 1732 resets = <&rcc USBO_R>; 1733 reset-names = "dwc2"; 1734 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1735 g-rx-fifo-size = <512>; 1736 g-np-tx-fifo-size = <32>; 1737 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1738 dr_mode = "otg"; 1739 otg-rev = <0x200>; 1740 usb33d-supply = <&usb33>; 1741 access-controllers = <&etzpc 85>; 1742 status = "disabled"; 1743 }; 1744 1745 dcmi: dcmi@4c006000 { 1746 compatible = "st,stm32-dcmi"; 1747 reg = <0x4c006000 0x400>; 1748 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1749 resets = <&rcc CAMITF_R>; 1750 clocks = <&rcc DCMI>; 1751 clock-names = "mclk"; 1752 dmas = <&dmamux1 75 0x400 0x01>; 1753 dma-names = "tx"; 1754 access-controllers = <&etzpc 70>; 1755 status = "disabled"; 1756 }; 1757 1758 lptimer2: timer@50021000 { 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 compatible = "st,stm32-lptimer"; 1762 reg = <0x50021000 0x400>; 1763 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1764 clocks = <&rcc LPTIM2_K>; 1765 clock-names = "mux"; 1766 wakeup-source; 1767 access-controllers = <&etzpc 64>; 1768 status = "disabled"; 1769 1770 pwm { 1771 compatible = "st,stm32-pwm-lp"; 1772 #pwm-cells = <3>; 1773 status = "disabled"; 1774 }; 1775 1776 trigger@1 { 1777 compatible = "st,stm32-lptimer-trigger"; 1778 reg = <1>; 1779 status = "disabled"; 1780 }; 1781 1782 counter { 1783 compatible = "st,stm32-lptimer-counter"; 1784 status = "disabled"; 1785 }; 1786 }; 1787 1788 lptimer3: timer@50022000 { 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 compatible = "st,stm32-lptimer"; 1792 reg = <0x50022000 0x400>; 1793 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1794 clocks = <&rcc LPTIM3_K>; 1795 clock-names = "mux"; 1796 wakeup-source; 1797 access-controllers = <&etzpc 65>; 1798 status = "disabled"; 1799 1800 pwm { 1801 compatible = "st,stm32-pwm-lp"; 1802 #pwm-cells = <3>; 1803 status = "disabled"; 1804 }; 1805 1806 trigger@2 { 1807 compatible = "st,stm32-lptimer-trigger"; 1808 reg = <2>; 1809 status = "disabled"; 1810 }; 1811 }; 1812 1813 lptimer4: timer@50023000 { 1814 compatible = "st,stm32-lptimer"; 1815 reg = <0x50023000 0x400>; 1816 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1817 clocks = <&rcc LPTIM4_K>; 1818 clock-names = "mux"; 1819 wakeup-source; 1820 access-controllers = <&etzpc 66>; 1821 status = "disabled"; 1822 1823 pwm { 1824 compatible = "st,stm32-pwm-lp"; 1825 #pwm-cells = <3>; 1826 status = "disabled"; 1827 }; 1828 }; 1829 1830 lptimer5: timer@50024000 { 1831 compatible = "st,stm32-lptimer"; 1832 reg = <0x50024000 0x400>; 1833 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1834 clocks = <&rcc LPTIM5_K>; 1835 clock-names = "mux"; 1836 wakeup-source; 1837 access-controllers = <&etzpc 67>; 1838 status = "disabled"; 1839 1840 pwm { 1841 compatible = "st,stm32-pwm-lp"; 1842 #pwm-cells = <3>; 1843 status = "disabled"; 1844 }; 1845 }; 1846 1847 vrefbuf: vrefbuf@50025000 { 1848 compatible = "st,stm32-vrefbuf"; 1849 reg = <0x50025000 0x8>; 1850 regulator-min-microvolt = <1500000>; 1851 regulator-max-microvolt = <2500000>; 1852 clocks = <&rcc VREF>; 1853 access-controllers = <&etzpc 69>; 1854 status = "disabled"; 1855 }; 1856 1857 sai4: sai@50027000 { 1858 compatible = "st,stm32h7-sai"; 1859 #address-cells = <1>; 1860 #size-cells = <1>; 1861 ranges = <0 0x50027000 0x400>; 1862 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1863 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1864 resets = <&rcc SAI4_R>; 1865 access-controllers = <&etzpc 68>; 1866 status = "disabled"; 1867 1868 sai4a: audio-controller@50027004 { 1869 #sound-dai-cells = <0>; 1870 compatible = "st,stm32-sai-sub-a"; 1871 reg = <0x04 0x20>; 1872 clocks = <&rcc SAI4_K>; 1873 clock-names = "sai_ck"; 1874 dmas = <&dmamux1 99 0x400 0x01>; 1875 status = "disabled"; 1876 }; 1877 1878 sai4b: audio-controller@50027024 { 1879 #sound-dai-cells = <0>; 1880 compatible = "st,stm32-sai-sub-b"; 1881 reg = <0x24 0x20>; 1882 clocks = <&rcc SAI4_K>; 1883 clock-names = "sai_ck"; 1884 dmas = <&dmamux1 100 0x400 0x01>; 1885 status = "disabled"; 1886 }; 1887 }; 1888 1889 hash1: hash@54002000 { 1890 compatible = "st,stm32f756-hash"; 1891 reg = <0x54002000 0x400>; 1892 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1893 clocks = <&rcc HASH1>; 1894 resets = <&rcc HASH1_R>; 1895 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1896 dma-names = "in"; 1897 dma-maxburst = <2>; 1898 access-controllers = <&etzpc 8>; 1899 status = "disabled"; 1900 }; 1901 1902 rng1: rng@54003000 { 1903 compatible = "st,stm32-rng"; 1904 reg = <0x54003000 0x400>; 1905 clocks = <&rcc RNG1_K>; 1906 resets = <&rcc RNG1_R>; 1907 access-controllers = <&etzpc 7>; 1908 status = "disabled"; 1909 }; 1910 1911 fmc: memory-controller@58002000 { 1912 #address-cells = <2>; 1913 #size-cells = <1>; 1914 compatible = "st,stm32mp1-fmc2-ebi"; 1915 reg = <0x58002000 0x1000>; 1916 clocks = <&rcc FMC_K>; 1917 resets = <&rcc FMC_R>; 1918 access-controllers = <&etzpc 91>; 1919 status = "disabled"; 1920 1921 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1922 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1923 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1924 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1925 <4 0 0x80000000 0x10000000>; /* NAND */ 1926 1927 nand-controller@4,0 { 1928 #address-cells = <1>; 1929 #size-cells = <0>; 1930 compatible = "st,stm32mp1-fmc2-nfc"; 1931 reg = <4 0x00000000 0x1000>, 1932 <4 0x08010000 0x1000>, 1933 <4 0x08020000 0x1000>, 1934 <4 0x01000000 0x1000>, 1935 <4 0x09010000 0x1000>, 1936 <4 0x09020000 0x1000>; 1937 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1938 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1939 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1940 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1941 dma-names = "tx", "rx", "ecc"; 1942 status = "disabled"; 1943 }; 1944 }; 1945 1946 qspi: spi@58003000 { 1947 compatible = "st,stm32f469-qspi"; 1948 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1949 reg-names = "qspi", "qspi_mm"; 1950 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1951 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1952 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1953 dma-names = "tx", "rx"; 1954 clocks = <&rcc QSPI_K>; 1955 resets = <&rcc QSPI_R>; 1956 #address-cells = <1>; 1957 #size-cells = <0>; 1958 access-controllers = <&etzpc 92>; 1959 status = "disabled"; 1960 }; 1961 1962 ethernet0: ethernet@5800a000 { 1963 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1964 reg = <0x5800a000 0x2000>; 1965 reg-names = "stmmaceth"; 1966 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1967 interrupt-names = "macirq"; 1968 clock-names = "stmmaceth", 1969 "mac-clk-tx", 1970 "mac-clk-rx", 1971 "eth-ck", 1972 "ptp_ref", 1973 "ethstp"; 1974 clocks = <&rcc ETHMAC>, 1975 <&rcc ETHTX>, 1976 <&rcc ETHRX>, 1977 <&rcc ETHCK_K>, 1978 <&rcc ETHPTP_K>, 1979 <&rcc ETHSTP>; 1980 st,syscon = <&syscfg 0x4>; 1981 snps,mixed-burst; 1982 snps,pbl = <2>; 1983 snps,axi-config = <&stmmac_axi_config_0>; 1984 snps,tso; 1985 access-controllers = <&etzpc 94>; 1986 status = "disabled"; 1987 1988 stmmac_axi_config_0: stmmac-axi-config { 1989 snps,wr_osr_lmt = <0x7>; 1990 snps,rd_osr_lmt = <0x7>; 1991 snps,blen = <0 0 0 0 16 8 4>; 1992 }; 1993 }; 1994 1995 usart1: serial@5c000000 { 1996 compatible = "st,stm32h7-uart"; 1997 reg = <0x5c000000 0x400>; 1998 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1999 clocks = <&rcc USART1_K>; 2000 wakeup-source; 2001 access-controllers = <&etzpc 3>; 2002 status = "disabled"; 2003 }; 2004 2005 spi6: spi@5c001000 { 2006 #address-cells = <1>; 2007 #size-cells = <0>; 2008 compatible = "st,stm32h7-spi"; 2009 reg = <0x5c001000 0x400>; 2010 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2011 clocks = <&rcc SPI6_K>; 2012 resets = <&rcc SPI6_R>; 2013 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 2014 <&mdma1 35 0x0 0x40002 0x0 0x0>; 2015 access-controllers = <&etzpc 4>; 2016 dma-names = "rx", "tx"; 2017 status = "disabled"; 2018 }; 2019 2020 i2c4: i2c@5c002000 { 2021 compatible = "st,stm32mp15-i2c"; 2022 reg = <0x5c002000 0x400>; 2023 interrupt-names = "event", "error"; 2024 interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, 2025 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2026 clocks = <&rcc I2C4_K>; 2027 resets = <&rcc I2C4_R>; 2028 #address-cells = <1>; 2029 #size-cells = <0>; 2030 dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, 2031 <&mdma1 37 0x0 0x40002 0x0 0x0>; 2032 dma-names = "rx", "tx"; 2033 st,syscfg-fmp = <&syscfg 0x4 0x8>; 2034 wakeup-source; 2035 i2c-analog-filter; 2036 access-controllers = <&etzpc 5>; 2037 status = "disabled"; 2038 }; 2039 2040 i2c6: i2c@5c009000 { 2041 compatible = "st,stm32mp15-i2c"; 2042 reg = <0x5c009000 0x400>; 2043 interrupt-names = "event", "error"; 2044 interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>, 2045 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 2046 clocks = <&rcc I2C6_K>; 2047 resets = <&rcc I2C6_R>; 2048 #address-cells = <1>; 2049 #size-cells = <0>; 2050 dmas = <&mdma1 38 0x0 0x40008 0x0 0x0>, 2051 <&mdma1 39 0x0 0x40002 0x0 0x0>; 2052 dma-names = "rx", "tx"; 2053 st,syscfg-fmp = <&syscfg 0x4 0x20>; 2054 wakeup-source; 2055 i2c-analog-filter; 2056 access-controllers = <&etzpc 12>; 2057 status = "disabled"; 2058 }; 2059 }; 2060 2061 tamp: tamp@5c00a000 { 2062 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 2063 reg = <0x5c00a000 0x400>; 2064 }; 2065 2066 /* 2067 * Break node order to solve dependency probe issue between 2068 * pinctrl and exti. 2069 */ 2070 pinctrl: pinctrl@50002000 { 2071 #address-cells = <1>; 2072 #size-cells = <1>; 2073 compatible = "st,stm32mp157-pinctrl"; 2074 ranges = <0 0x50002000 0xa400>; 2075 interrupt-parent = <&exti>; 2076 st,syscfg = <&exti 0x60 0xff>; 2077 2078 gpioa: gpio@50002000 { 2079 gpio-controller; 2080 #gpio-cells = <2>; 2081 interrupt-controller; 2082 #interrupt-cells = <2>; 2083 reg = <0x0 0x400>; 2084 clocks = <&rcc GPIOA>; 2085 st,bank-name = "GPIOA"; 2086 status = "disabled"; 2087 }; 2088 2089 gpiob: gpio@50003000 { 2090 gpio-controller; 2091 #gpio-cells = <2>; 2092 interrupt-controller; 2093 #interrupt-cells = <2>; 2094 reg = <0x1000 0x400>; 2095 clocks = <&rcc GPIOB>; 2096 st,bank-name = "GPIOB"; 2097 status = "disabled"; 2098 }; 2099 2100 gpioc: gpio@50004000 { 2101 gpio-controller; 2102 #gpio-cells = <2>; 2103 interrupt-controller; 2104 #interrupt-cells = <2>; 2105 reg = <0x2000 0x400>; 2106 clocks = <&rcc GPIOC>; 2107 st,bank-name = "GPIOC"; 2108 status = "disabled"; 2109 }; 2110 2111 gpiod: gpio@50005000 { 2112 gpio-controller; 2113 #gpio-cells = <2>; 2114 interrupt-controller; 2115 #interrupt-cells = <2>; 2116 reg = <0x3000 0x400>; 2117 clocks = <&rcc GPIOD>; 2118 st,bank-name = "GPIOD"; 2119 status = "disabled"; 2120 }; 2121 2122 gpioe: gpio@50006000 { 2123 gpio-controller; 2124 #gpio-cells = <2>; 2125 interrupt-controller; 2126 #interrupt-cells = <2>; 2127 reg = <0x4000 0x400>; 2128 clocks = <&rcc GPIOE>; 2129 st,bank-name = "GPIOE"; 2130 status = "disabled"; 2131 }; 2132 2133 gpiof: gpio@50007000 { 2134 gpio-controller; 2135 #gpio-cells = <2>; 2136 interrupt-controller; 2137 #interrupt-cells = <2>; 2138 reg = <0x5000 0x400>; 2139 clocks = <&rcc GPIOF>; 2140 st,bank-name = "GPIOF"; 2141 status = "disabled"; 2142 }; 2143 2144 gpiog: gpio@50008000 { 2145 gpio-controller; 2146 #gpio-cells = <2>; 2147 interrupt-controller; 2148 #interrupt-cells = <2>; 2149 reg = <0x6000 0x400>; 2150 clocks = <&rcc GPIOG>; 2151 st,bank-name = "GPIOG"; 2152 status = "disabled"; 2153 }; 2154 2155 gpioh: gpio@50009000 { 2156 gpio-controller; 2157 #gpio-cells = <2>; 2158 interrupt-controller; 2159 #interrupt-cells = <2>; 2160 reg = <0x7000 0x400>; 2161 clocks = <&rcc GPIOH>; 2162 st,bank-name = "GPIOH"; 2163 status = "disabled"; 2164 }; 2165 2166 gpioi: gpio@5000a000 { 2167 gpio-controller; 2168 #gpio-cells = <2>; 2169 interrupt-controller; 2170 #interrupt-cells = <2>; 2171 reg = <0x8000 0x400>; 2172 clocks = <&rcc GPIOI>; 2173 st,bank-name = "GPIOI"; 2174 status = "disabled"; 2175 }; 2176 2177 gpioj: gpio@5000b000 { 2178 gpio-controller; 2179 #gpio-cells = <2>; 2180 interrupt-controller; 2181 #interrupt-cells = <2>; 2182 reg = <0x9000 0x400>; 2183 clocks = <&rcc GPIOJ>; 2184 st,bank-name = "GPIOJ"; 2185 status = "disabled"; 2186 }; 2187 2188 gpiok: gpio@5000c000 { 2189 gpio-controller; 2190 #gpio-cells = <2>; 2191 interrupt-controller; 2192 #interrupt-cells = <2>; 2193 reg = <0xa000 0x400>; 2194 clocks = <&rcc GPIOK>; 2195 st,bank-name = "GPIOK"; 2196 status = "disabled"; 2197 }; 2198 }; 2199 2200 pinctrl_z: pinctrl@54004000 { 2201 #address-cells = <1>; 2202 #size-cells = <1>; 2203 compatible = "st,stm32mp157-z-pinctrl"; 2204 ranges = <0 0x54004000 0x400>; 2205 interrupt-parent = <&exti>; 2206 st,syscfg = <&exti 0x60 0xff>; 2207 2208 gpioz: gpio@54004000 { 2209 gpio-controller; 2210 #gpio-cells = <2>; 2211 interrupt-controller; 2212 #interrupt-cells = <2>; 2213 reg = <0 0x400>; 2214 clocks = <&rcc GPIOZ>; 2215 st,bank-name = "GPIOZ"; 2216 st,bank-ioport = <11>; 2217 status = "disabled"; 2218 }; 2219 }; 2220 }; 2221 2222 mlahb: ahb { 2223 compatible = "st,mlahb", "simple-bus"; 2224 #address-cells = <1>; 2225 #size-cells = <1>; 2226 ranges; 2227 dma-ranges = <0x00000000 0x38000000 0x10000>, 2228 <0x10000000 0x10000000 0x60000>, 2229 <0x30000000 0x30000000 0x60000>; 2230 2231 m4_rproc: m4@10000000 { 2232 compatible = "st,stm32mp1-m4"; 2233 reg = <0x10000000 0x40000>, 2234 <0x30000000 0x40000>, 2235 <0x38000000 0x10000>; 2236 resets = <&rcc MCU_R>; 2237 reset-names = "mcu_rst"; 2238 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 2239 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 2240 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 2241 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 2242 status = "disabled"; 2243 }; 2244 }; 2245}; 2246