1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 clock-frequency = <650000000>; 21 device_type = "cpu"; 22 reg = <0>; 23 }; 24 }; 25 26 arm-pmu { 27 compatible = "arm,cortex-a7-pmu"; 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-affinity = <&cpu0>; 30 interrupt-parent = <&intc>; 31 }; 32 33 psci { 34 compatible = "arm,psci-1.0"; 35 method = "smc"; 36 }; 37 38 intc: interrupt-controller@a0021000 { 39 compatible = "arm,cortex-a7-gic"; 40 #interrupt-cells = <3>; 41 interrupt-controller; 42 reg = <0xa0021000 0x1000>, 43 <0xa0022000 0x2000>; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&intc>; 53 arm,no-tick-in-suspend; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&exti 61 1>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 134 interrupt-names = "rx", "tx"; 135 clocks = <&rcc IPCC>; 136 wakeup-source; 137 status = "disabled"; 138 }; 139 140 rcc: rcc@50000000 { 141 compatible = "st,stm32mp1-rcc", "syscon"; 142 reg = <0x50000000 0x1000>; 143 #clock-cells = <1>; 144 #reset-cells = <1>; 145 }; 146 147 pwr_regulators: pwr@50001000 { 148 compatible = "st,stm32mp1,pwr-reg"; 149 reg = <0x50001000 0x10>; 150 151 reg11: reg11 { 152 regulator-name = "reg11"; 153 regulator-min-microvolt = <1100000>; 154 regulator-max-microvolt = <1100000>; 155 }; 156 157 reg18: reg18 { 158 regulator-name = "reg18"; 159 regulator-min-microvolt = <1800000>; 160 regulator-max-microvolt = <1800000>; 161 }; 162 163 usb33: usb33 { 164 regulator-name = "usb33"; 165 regulator-min-microvolt = <3300000>; 166 regulator-max-microvolt = <3300000>; 167 }; 168 }; 169 170 pwr_mcu: pwr_mcu@50001014 { 171 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 172 reg = <0x50001014 0x4>; 173 }; 174 175 exti: interrupt-controller@5000d000 { 176 compatible = "st,stm32mp1-exti", "syscon"; 177 interrupt-controller; 178 #interrupt-cells = <2>; 179 reg = <0x5000d000 0x400>; 180 interrupts-extended = 181 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 182 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 183 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 184 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 185 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 186 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 187 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 188 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 189 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 190 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 191 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 192 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 193 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 194 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 195 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 196 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 197 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 198 <0>, 199 <0>, 200 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 201 <0>, /* EXTI_20 */ 202 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 203 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 204 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 205 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 206 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 207 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 208 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 209 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 210 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 211 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 212 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 213 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 214 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 215 <0>, 216 <0>, 217 <0>, 218 <0>, 219 <0>, 220 <0>, 221 <0>, /* EXTI_40 */ 222 <0>, 223 <0>, 224 <0>, 225 <0>, 226 <0>, 227 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 228 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 229 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 230 <0>, 231 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 232 <0>, 233 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 234 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 235 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 236 <0>, 237 <0>, 238 <0>, 239 <0>, 240 <0>, 241 <0>, /* EXTI_60 */ 242 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 243 <0>, 244 <0>, 245 <0>, 246 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 247 <0>, 248 <0>, 249 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 250 <0>, 251 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 252 <0>, 253 <0>, 254 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 255 }; 256 257 syscfg: syscon@50020000 { 258 compatible = "st,stm32mp157-syscfg", "syscon"; 259 reg = <0x50020000 0x400>; 260 clocks = <&rcc SYSCFG>; 261 }; 262 263 dts: thermal@50028000 { 264 compatible = "st,stm32-thermal"; 265 reg = <0x50028000 0x100>; 266 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&rcc TMPSENS>; 268 clock-names = "pclk"; 269 #thermal-sensor-cells = <0>; 270 status = "disabled"; 271 }; 272 273 mdma1: dma-controller@58000000 { 274 compatible = "st,stm32h7-mdma"; 275 reg = <0x58000000 0x1000>; 276 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&rcc MDMA>; 278 resets = <&rcc MDMA_R>; 279 #dma-cells = <5>; 280 dma-channels = <32>; 281 dma-requests = <48>; 282 }; 283 284 sdmmc1: mmc@58005000 { 285 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 286 arm,primecell-periphid = <0x00253180>; 287 reg = <0x58005000 0x1000>; 288 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&rcc SDMMC1_K>; 290 clock-names = "apb_pclk"; 291 resets = <&rcc SDMMC1_R>; 292 cap-sd-highspeed; 293 cap-mmc-highspeed; 294 max-frequency = <120000000>; 295 status = "disabled"; 296 }; 297 298 sdmmc2: mmc@58007000 { 299 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 300 arm,primecell-periphid = <0x00253180>; 301 reg = <0x58007000 0x1000>; 302 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&rcc SDMMC2_K>; 304 clock-names = "apb_pclk"; 305 resets = <&rcc SDMMC2_R>; 306 cap-sd-highspeed; 307 cap-mmc-highspeed; 308 max-frequency = <120000000>; 309 status = "disabled"; 310 }; 311 312 crc1: crc@58009000 { 313 compatible = "st,stm32f7-crc"; 314 reg = <0x58009000 0x400>; 315 clocks = <&rcc CRC1>; 316 status = "disabled"; 317 }; 318 319 usbh_ohci: usb@5800c000 { 320 compatible = "generic-ohci"; 321 reg = <0x5800c000 0x1000>; 322 clocks = <&usbphyc>, <&rcc USBH>; 323 resets = <&rcc USBH_R>; 324 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 325 phys = <&usbphyc_port0>; 326 phy-names = "usb"; 327 status = "disabled"; 328 }; 329 330 usbh_ehci: usb@5800d000 { 331 compatible = "generic-ehci"; 332 reg = <0x5800d000 0x1000>; 333 clocks = <&usbphyc>, <&rcc USBH>; 334 resets = <&rcc USBH_R>; 335 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 336 companion = <&usbh_ohci>; 337 phys = <&usbphyc_port0>; 338 phy-names = "usb"; 339 status = "disabled"; 340 }; 341 342 ltdc: display-controller@5a001000 { 343 compatible = "st,stm32-ltdc"; 344 reg = <0x5a001000 0x400>; 345 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&rcc LTDC_PX>; 348 clock-names = "lcd"; 349 resets = <&rcc LTDC_R>; 350 status = "disabled"; 351 }; 352 353 iwdg2: watchdog@5a002000 { 354 compatible = "st,stm32mp1-iwdg"; 355 reg = <0x5a002000 0x400>; 356 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 357 clock-names = "pclk", "lsi"; 358 interrupts-extended = <&exti 46 IRQ_TYPE_LEVEL_HIGH>; 359 wakeup-source; 360 status = "disabled"; 361 }; 362 363 usbphyc: usbphyc@5a006000 { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 #clock-cells = <0>; 367 compatible = "st,stm32mp1-usbphyc"; 368 reg = <0x5a006000 0x1000>; 369 clocks = <&rcc USBPHY_K>; 370 resets = <&rcc USBPHY_R>; 371 vdda1v1-supply = <®11>; 372 vdda1v8-supply = <®18>; 373 status = "disabled"; 374 375 usbphyc_port0: usb-phy@0 { 376 #phy-cells = <0>; 377 reg = <0>; 378 }; 379 380 usbphyc_port1: usb-phy@1 { 381 #phy-cells = <1>; 382 reg = <1>; 383 }; 384 }; 385 386 rtc: rtc@5c004000 { 387 compatible = "st,stm32mp1-rtc"; 388 reg = <0x5c004000 0x400>; 389 clocks = <&rcc RTCAPB>, <&rcc RTC>; 390 clock-names = "pclk", "rtc_ck"; 391 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 392 status = "disabled"; 393 }; 394 395 bsec: efuse@5c005000 { 396 compatible = "st,stm32mp15-bsec"; 397 reg = <0x5c005000 0x400>; 398 #address-cells = <1>; 399 #size-cells = <1>; 400 part_number_otp: part-number-otp@4 { 401 reg = <0x4 0x1>; 402 }; 403 vrefint: vrefin-cal@52 { 404 reg = <0x52 0x2>; 405 }; 406 ts_cal1: calib@5c { 407 reg = <0x5c 0x2>; 408 }; 409 ts_cal2: calib@5e { 410 reg = <0x5e 0x2>; 411 }; 412 }; 413 414 etzpc: bus@5c007000 { 415 compatible = "st,stm32-etzpc", "simple-bus"; 416 reg = <0x5c007000 0x400>; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 #access-controller-cells = <1>; 420 ranges; 421 422 timers2: timer@40000000 { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 compatible = "st,stm32-timers"; 426 reg = <0x40000000 0x400>; 427 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 428 interrupt-names = "global"; 429 clocks = <&rcc TIM2_K>; 430 clock-names = "int"; 431 dmas = <&dmamux1 18 0x400 0x1>, 432 <&dmamux1 19 0x400 0x1>, 433 <&dmamux1 20 0x400 0x1>, 434 <&dmamux1 21 0x400 0x1>, 435 <&dmamux1 22 0x400 0x1>; 436 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 437 access-controllers = <&etzpc 16>; 438 status = "disabled"; 439 440 pwm { 441 compatible = "st,stm32-pwm"; 442 #pwm-cells = <3>; 443 status = "disabled"; 444 }; 445 446 timer@1 { 447 compatible = "st,stm32h7-timer-trigger"; 448 reg = <1>; 449 status = "disabled"; 450 }; 451 452 counter { 453 compatible = "st,stm32-timer-counter"; 454 status = "disabled"; 455 }; 456 }; 457 458 timers3: timer@40001000 { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 compatible = "st,stm32-timers"; 462 reg = <0x40001000 0x400>; 463 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 464 interrupt-names = "global"; 465 clocks = <&rcc TIM3_K>; 466 clock-names = "int"; 467 dmas = <&dmamux1 23 0x400 0x1>, 468 <&dmamux1 24 0x400 0x1>, 469 <&dmamux1 25 0x400 0x1>, 470 <&dmamux1 26 0x400 0x1>, 471 <&dmamux1 27 0x400 0x1>, 472 <&dmamux1 28 0x400 0x1>; 473 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 474 access-controllers = <&etzpc 17>; 475 status = "disabled"; 476 477 pwm { 478 compatible = "st,stm32-pwm"; 479 #pwm-cells = <3>; 480 status = "disabled"; 481 }; 482 483 timer@2 { 484 compatible = "st,stm32h7-timer-trigger"; 485 reg = <2>; 486 status = "disabled"; 487 }; 488 489 counter { 490 compatible = "st,stm32-timer-counter"; 491 status = "disabled"; 492 }; 493 }; 494 495 timers4: timer@40002000 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 compatible = "st,stm32-timers"; 499 reg = <0x40002000 0x400>; 500 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 501 interrupt-names = "global"; 502 clocks = <&rcc TIM4_K>; 503 clock-names = "int"; 504 dmas = <&dmamux1 29 0x400 0x1>, 505 <&dmamux1 30 0x400 0x1>, 506 <&dmamux1 31 0x400 0x1>, 507 <&dmamux1 32 0x400 0x1>; 508 dma-names = "ch1", "ch2", "ch3", "ch4"; 509 access-controllers = <&etzpc 18>; 510 status = "disabled"; 511 512 pwm { 513 compatible = "st,stm32-pwm"; 514 #pwm-cells = <3>; 515 status = "disabled"; 516 }; 517 518 timer@3 { 519 compatible = "st,stm32h7-timer-trigger"; 520 reg = <3>; 521 status = "disabled"; 522 }; 523 524 counter { 525 compatible = "st,stm32-timer-counter"; 526 status = "disabled"; 527 }; 528 }; 529 530 timers5: timer@40003000 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 compatible = "st,stm32-timers"; 534 reg = <0x40003000 0x400>; 535 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 536 interrupt-names = "global"; 537 clocks = <&rcc TIM5_K>; 538 clock-names = "int"; 539 dmas = <&dmamux1 55 0x400 0x1>, 540 <&dmamux1 56 0x400 0x1>, 541 <&dmamux1 57 0x400 0x1>, 542 <&dmamux1 58 0x400 0x1>, 543 <&dmamux1 59 0x400 0x1>, 544 <&dmamux1 60 0x400 0x1>; 545 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 546 access-controllers = <&etzpc 19>; 547 status = "disabled"; 548 549 pwm { 550 compatible = "st,stm32-pwm"; 551 #pwm-cells = <3>; 552 status = "disabled"; 553 }; 554 555 timer@4 { 556 compatible = "st,stm32h7-timer-trigger"; 557 reg = <4>; 558 status = "disabled"; 559 }; 560 561 counter { 562 compatible = "st,stm32-timer-counter"; 563 status = "disabled"; 564 }; 565 }; 566 567 timers6: timer@40004000 { 568 #address-cells = <1>; 569 #size-cells = <0>; 570 compatible = "st,stm32-timers"; 571 reg = <0x40004000 0x400>; 572 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "global"; 574 clocks = <&rcc TIM6_K>; 575 clock-names = "int"; 576 dmas = <&dmamux1 69 0x400 0x1>; 577 dma-names = "up"; 578 access-controllers = <&etzpc 20>; 579 status = "disabled"; 580 581 timer@5 { 582 compatible = "st,stm32h7-timer-trigger"; 583 reg = <5>; 584 status = "disabled"; 585 }; 586 }; 587 588 timers7: timer@40005000 { 589 #address-cells = <1>; 590 #size-cells = <0>; 591 compatible = "st,stm32-timers"; 592 reg = <0x40005000 0x400>; 593 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 594 interrupt-names = "global"; 595 clocks = <&rcc TIM7_K>; 596 clock-names = "int"; 597 dmas = <&dmamux1 70 0x400 0x1>; 598 dma-names = "up"; 599 access-controllers = <&etzpc 21>; 600 status = "disabled"; 601 602 timer@6 { 603 compatible = "st,stm32h7-timer-trigger"; 604 reg = <6>; 605 status = "disabled"; 606 }; 607 }; 608 609 timers12: timer@40006000 { 610 #address-cells = <1>; 611 #size-cells = <0>; 612 compatible = "st,stm32-timers"; 613 reg = <0x40006000 0x400>; 614 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 615 interrupt-names = "global"; 616 clocks = <&rcc TIM12_K>; 617 clock-names = "int"; 618 access-controllers = <&etzpc 22>; 619 status = "disabled"; 620 621 pwm { 622 compatible = "st,stm32-pwm"; 623 #pwm-cells = <3>; 624 status = "disabled"; 625 }; 626 627 timer@11 { 628 compatible = "st,stm32h7-timer-trigger"; 629 reg = <11>; 630 status = "disabled"; 631 }; 632 }; 633 634 timers13: timer@40007000 { 635 #address-cells = <1>; 636 #size-cells = <0>; 637 compatible = "st,stm32-timers"; 638 reg = <0x40007000 0x400>; 639 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 640 interrupt-names = "global"; 641 clocks = <&rcc TIM13_K>; 642 clock-names = "int"; 643 access-controllers = <&etzpc 23>; 644 status = "disabled"; 645 646 pwm { 647 compatible = "st,stm32-pwm"; 648 #pwm-cells = <3>; 649 status = "disabled"; 650 }; 651 652 timer@12 { 653 compatible = "st,stm32h7-timer-trigger"; 654 reg = <12>; 655 status = "disabled"; 656 }; 657 }; 658 659 timers14: timer@40008000 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 compatible = "st,stm32-timers"; 663 reg = <0x40008000 0x400>; 664 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 665 interrupt-names = "global"; 666 clocks = <&rcc TIM14_K>; 667 clock-names = "int"; 668 access-controllers = <&etzpc 24>; 669 status = "disabled"; 670 671 pwm { 672 compatible = "st,stm32-pwm"; 673 #pwm-cells = <3>; 674 status = "disabled"; 675 }; 676 677 timer@13 { 678 compatible = "st,stm32h7-timer-trigger"; 679 reg = <13>; 680 status = "disabled"; 681 }; 682 }; 683 684 lptimer1: timer@40009000 { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 compatible = "st,stm32-lptimer"; 688 reg = <0x40009000 0x400>; 689 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&rcc LPTIM1_K>; 691 clock-names = "mux"; 692 wakeup-source; 693 access-controllers = <&etzpc 25>; 694 status = "disabled"; 695 696 pwm { 697 compatible = "st,stm32-pwm-lp"; 698 #pwm-cells = <3>; 699 status = "disabled"; 700 }; 701 702 trigger@0 { 703 compatible = "st,stm32-lptimer-trigger"; 704 reg = <0>; 705 status = "disabled"; 706 }; 707 708 counter { 709 compatible = "st,stm32-lptimer-counter"; 710 status = "disabled"; 711 }; 712 }; 713 714 i2s2: audio-controller@4000b000 { 715 compatible = "st,stm32h7-i2s"; 716 #sound-dai-cells = <0>; 717 reg = <0x4000b000 0x400>; 718 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 719 dmas = <&dmamux1 39 0x400 0x01>, 720 <&dmamux1 40 0x400 0x01>; 721 dma-names = "rx", "tx"; 722 access-controllers = <&etzpc 27>; 723 status = "disabled"; 724 }; 725 726 spi2: spi@4000b000 { 727 #address-cells = <1>; 728 #size-cells = <0>; 729 compatible = "st,stm32h7-spi"; 730 reg = <0x4000b000 0x400>; 731 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&rcc SPI2_K>; 733 resets = <&rcc SPI2_R>; 734 dmas = <&dmamux1 39 0x400 0x05>, 735 <&dmamux1 40 0x400 0x05>; 736 dma-names = "rx", "tx"; 737 access-controllers = <&etzpc 27>; 738 status = "disabled"; 739 }; 740 741 i2s3: audio-controller@4000c000 { 742 compatible = "st,stm32h7-i2s"; 743 #sound-dai-cells = <0>; 744 reg = <0x4000c000 0x400>; 745 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 746 dmas = <&dmamux1 61 0x400 0x01>, 747 <&dmamux1 62 0x400 0x01>; 748 dma-names = "rx", "tx"; 749 access-controllers = <&etzpc 28>; 750 status = "disabled"; 751 }; 752 753 spi3: spi@4000c000 { 754 #address-cells = <1>; 755 #size-cells = <0>; 756 compatible = "st,stm32h7-spi"; 757 reg = <0x4000c000 0x400>; 758 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&rcc SPI3_K>; 760 resets = <&rcc SPI3_R>; 761 dmas = <&dmamux1 61 0x400 0x05>, 762 <&dmamux1 62 0x400 0x05>; 763 dma-names = "rx", "tx"; 764 access-controllers = <&etzpc 28>; 765 status = "disabled"; 766 }; 767 768 spdifrx: audio-controller@4000d000 { 769 compatible = "st,stm32h7-spdifrx"; 770 #sound-dai-cells = <0>; 771 reg = <0x4000d000 0x400>; 772 clocks = <&rcc SPDIF_K>; 773 clock-names = "kclk"; 774 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 775 dmas = <&dmamux1 93 0x400 0x01>, 776 <&dmamux1 94 0x400 0x01>; 777 dma-names = "rx", "rx-ctrl"; 778 access-controllers = <&etzpc 29>; 779 status = "disabled"; 780 }; 781 782 usart2: serial@4000e000 { 783 compatible = "st,stm32h7-uart"; 784 reg = <0x4000e000 0x400>; 785 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&rcc USART2_K>; 787 wakeup-source; 788 dmas = <&dmamux1 43 0x400 0x15>, 789 <&dmamux1 44 0x400 0x11>; 790 dma-names = "rx", "tx"; 791 access-controllers = <&etzpc 30>; 792 status = "disabled"; 793 }; 794 795 usart3: serial@4000f000 { 796 compatible = "st,stm32h7-uart"; 797 reg = <0x4000f000 0x400>; 798 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&rcc USART3_K>; 800 wakeup-source; 801 dmas = <&dmamux1 45 0x400 0x15>, 802 <&dmamux1 46 0x400 0x11>; 803 dma-names = "rx", "tx"; 804 access-controllers = <&etzpc 31>; 805 status = "disabled"; 806 }; 807 808 uart4: serial@40010000 { 809 compatible = "st,stm32h7-uart"; 810 reg = <0x40010000 0x400>; 811 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&rcc UART4_K>; 813 wakeup-source; 814 dmas = <&dmamux1 63 0x400 0x15>, 815 <&dmamux1 64 0x400 0x11>; 816 dma-names = "rx", "tx"; 817 access-controllers = <&etzpc 32>; 818 status = "disabled"; 819 }; 820 821 uart5: serial@40011000 { 822 compatible = "st,stm32h7-uart"; 823 reg = <0x40011000 0x400>; 824 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&rcc UART5_K>; 826 wakeup-source; 827 dmas = <&dmamux1 65 0x400 0x15>, 828 <&dmamux1 66 0x400 0x11>; 829 dma-names = "rx", "tx"; 830 access-controllers = <&etzpc 33>; 831 status = "disabled"; 832 }; 833 834 i2c1: i2c@40012000 { 835 compatible = "st,stm32mp15-i2c"; 836 reg = <0x40012000 0x400>; 837 interrupt-names = "event", "error"; 838 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&rcc I2C1_K>; 841 resets = <&rcc I2C1_R>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 st,syscfg-fmp = <&syscfg 0x4 0x1>; 845 wakeup-source; 846 i2c-analog-filter; 847 access-controllers = <&etzpc 34>; 848 status = "disabled"; 849 }; 850 851 i2c2: i2c@40013000 { 852 compatible = "st,stm32mp15-i2c"; 853 reg = <0x40013000 0x400>; 854 interrupt-names = "event", "error"; 855 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&rcc I2C2_K>; 858 resets = <&rcc I2C2_R>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 st,syscfg-fmp = <&syscfg 0x4 0x2>; 862 wakeup-source; 863 i2c-analog-filter; 864 access-controllers = <&etzpc 35>; 865 status = "disabled"; 866 }; 867 868 i2c3: i2c@40014000 { 869 compatible = "st,stm32mp15-i2c"; 870 reg = <0x40014000 0x400>; 871 interrupt-names = "event", "error"; 872 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&rcc I2C3_K>; 875 resets = <&rcc I2C3_R>; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 st,syscfg-fmp = <&syscfg 0x4 0x4>; 879 wakeup-source; 880 i2c-analog-filter; 881 access-controllers = <&etzpc 36>; 882 status = "disabled"; 883 }; 884 885 i2c5: i2c@40015000 { 886 compatible = "st,stm32mp15-i2c"; 887 reg = <0x40015000 0x400>; 888 interrupt-names = "event", "error"; 889 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&rcc I2C5_K>; 892 resets = <&rcc I2C5_R>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 st,syscfg-fmp = <&syscfg 0x4 0x10>; 896 wakeup-source; 897 i2c-analog-filter; 898 access-controllers = <&etzpc 37>; 899 status = "disabled"; 900 }; 901 902 cec: cec@40016000 { 903 compatible = "st,stm32-cec"; 904 reg = <0x40016000 0x400>; 905 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&rcc CEC_K>, <&rcc CEC>; 907 clock-names = "cec", "hdmi-cec"; 908 access-controllers = <&etzpc 38>; 909 status = "disabled"; 910 }; 911 912 dac: dac@40017000 { 913 compatible = "st,stm32h7-dac-core"; 914 reg = <0x40017000 0x400>; 915 clocks = <&rcc DAC12>; 916 clock-names = "pclk"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 access-controllers = <&etzpc 39>; 920 status = "disabled"; 921 922 dac1: dac@1 { 923 compatible = "st,stm32-dac"; 924 #io-channel-cells = <1>; 925 reg = <1>; 926 status = "disabled"; 927 }; 928 929 dac2: dac@2 { 930 compatible = "st,stm32-dac"; 931 #io-channel-cells = <1>; 932 reg = <2>; 933 status = "disabled"; 934 }; 935 }; 936 937 uart7: serial@40018000 { 938 compatible = "st,stm32h7-uart"; 939 reg = <0x40018000 0x400>; 940 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&rcc UART7_K>; 942 wakeup-source; 943 dmas = <&dmamux1 79 0x400 0x15>, 944 <&dmamux1 80 0x400 0x11>; 945 dma-names = "rx", "tx"; 946 access-controllers = <&etzpc 40>; 947 status = "disabled"; 948 }; 949 950 uart8: serial@40019000 { 951 compatible = "st,stm32h7-uart"; 952 reg = <0x40019000 0x400>; 953 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&rcc UART8_K>; 955 wakeup-source; 956 dmas = <&dmamux1 81 0x400 0x15>, 957 <&dmamux1 82 0x400 0x11>; 958 dma-names = "rx", "tx"; 959 access-controllers = <&etzpc 41>; 960 status = "disabled"; 961 }; 962 963 timers1: timer@44000000 { 964 #address-cells = <1>; 965 #size-cells = <0>; 966 compatible = "st,stm32-timers"; 967 reg = <0x44000000 0x400>; 968 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 972 interrupt-names = "brk", "up", "trg-com", "cc"; 973 clocks = <&rcc TIM1_K>; 974 clock-names = "int"; 975 dmas = <&dmamux1 11 0x400 0x1>, 976 <&dmamux1 12 0x400 0x1>, 977 <&dmamux1 13 0x400 0x1>, 978 <&dmamux1 14 0x400 0x1>, 979 <&dmamux1 15 0x400 0x1>, 980 <&dmamux1 16 0x400 0x1>, 981 <&dmamux1 17 0x400 0x1>; 982 dma-names = "ch1", "ch2", "ch3", "ch4", 983 "up", "trig", "com"; 984 access-controllers = <&etzpc 48>; 985 status = "disabled"; 986 987 pwm { 988 compatible = "st,stm32-pwm"; 989 #pwm-cells = <3>; 990 status = "disabled"; 991 }; 992 993 timer@0 { 994 compatible = "st,stm32h7-timer-trigger"; 995 reg = <0>; 996 status = "disabled"; 997 }; 998 999 counter { 1000 compatible = "st,stm32-timer-counter"; 1001 status = "disabled"; 1002 }; 1003 }; 1004 1005 timers8: timer@44001000 { 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 compatible = "st,stm32-timers"; 1009 reg = <0x44001000 0x400>; 1010 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1014 interrupt-names = "brk", "up", "trg-com", "cc"; 1015 clocks = <&rcc TIM8_K>; 1016 clock-names = "int"; 1017 dmas = <&dmamux1 47 0x400 0x1>, 1018 <&dmamux1 48 0x400 0x1>, 1019 <&dmamux1 49 0x400 0x1>, 1020 <&dmamux1 50 0x400 0x1>, 1021 <&dmamux1 51 0x400 0x1>, 1022 <&dmamux1 52 0x400 0x1>, 1023 <&dmamux1 53 0x400 0x1>; 1024 dma-names = "ch1", "ch2", "ch3", "ch4", 1025 "up", "trig", "com"; 1026 access-controllers = <&etzpc 49>; 1027 status = "disabled"; 1028 1029 pwm { 1030 compatible = "st,stm32-pwm"; 1031 #pwm-cells = <3>; 1032 status = "disabled"; 1033 }; 1034 1035 timer@7 { 1036 compatible = "st,stm32h7-timer-trigger"; 1037 reg = <7>; 1038 status = "disabled"; 1039 }; 1040 1041 counter { 1042 compatible = "st,stm32-timer-counter"; 1043 status = "disabled"; 1044 }; 1045 }; 1046 1047 usart6: serial@44003000 { 1048 compatible = "st,stm32h7-uart"; 1049 reg = <0x44003000 0x400>; 1050 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&rcc USART6_K>; 1052 wakeup-source; 1053 dmas = <&dmamux1 71 0x400 0x15>, 1054 <&dmamux1 72 0x400 0x11>; 1055 dma-names = "rx", "tx"; 1056 access-controllers = <&etzpc 51>; 1057 status = "disabled"; 1058 }; 1059 1060 i2s1: audio-controller@44004000 { 1061 compatible = "st,stm32h7-i2s"; 1062 #sound-dai-cells = <0>; 1063 reg = <0x44004000 0x400>; 1064 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1065 dmas = <&dmamux1 37 0x400 0x01>, 1066 <&dmamux1 38 0x400 0x01>; 1067 dma-names = "rx", "tx"; 1068 access-controllers = <&etzpc 52>; 1069 status = "disabled"; 1070 }; 1071 1072 spi1: spi@44004000 { 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 compatible = "st,stm32h7-spi"; 1076 reg = <0x44004000 0x400>; 1077 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&rcc SPI1_K>; 1079 resets = <&rcc SPI1_R>; 1080 dmas = <&dmamux1 37 0x400 0x05>, 1081 <&dmamux1 38 0x400 0x05>; 1082 dma-names = "rx", "tx"; 1083 access-controllers = <&etzpc 52>; 1084 status = "disabled"; 1085 }; 1086 1087 spi4: spi@44005000 { 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 compatible = "st,stm32h7-spi"; 1091 reg = <0x44005000 0x400>; 1092 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&rcc SPI4_K>; 1094 resets = <&rcc SPI4_R>; 1095 dmas = <&dmamux1 83 0x400 0x05>, 1096 <&dmamux1 84 0x400 0x05>; 1097 dma-names = "rx", "tx"; 1098 access-controllers = <&etzpc 53>; 1099 status = "disabled"; 1100 }; 1101 1102 timers15: timer@44006000 { 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 compatible = "st,stm32-timers"; 1106 reg = <0x44006000 0x400>; 1107 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1108 interrupt-names = "global"; 1109 clocks = <&rcc TIM15_K>; 1110 clock-names = "int"; 1111 dmas = <&dmamux1 105 0x400 0x1>, 1112 <&dmamux1 106 0x400 0x1>, 1113 <&dmamux1 107 0x400 0x1>, 1114 <&dmamux1 108 0x400 0x1>; 1115 dma-names = "ch1", "up", "trig", "com"; 1116 access-controllers = <&etzpc 54>; 1117 status = "disabled"; 1118 1119 pwm { 1120 compatible = "st,stm32-pwm"; 1121 #pwm-cells = <3>; 1122 status = "disabled"; 1123 }; 1124 1125 timer@14 { 1126 compatible = "st,stm32h7-timer-trigger"; 1127 reg = <14>; 1128 status = "disabled"; 1129 }; 1130 }; 1131 1132 timers16: timer@44007000 { 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 compatible = "st,stm32-timers"; 1136 reg = <0x44007000 0x400>; 1137 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1138 interrupt-names = "global"; 1139 clocks = <&rcc TIM16_K>; 1140 clock-names = "int"; 1141 dmas = <&dmamux1 109 0x400 0x1>, 1142 <&dmamux1 110 0x400 0x1>; 1143 dma-names = "ch1", "up"; 1144 access-controllers = <&etzpc 55>; 1145 status = "disabled"; 1146 1147 pwm { 1148 compatible = "st,stm32-pwm"; 1149 #pwm-cells = <3>; 1150 status = "disabled"; 1151 }; 1152 timer@15 { 1153 compatible = "st,stm32h7-timer-trigger"; 1154 reg = <15>; 1155 status = "disabled"; 1156 }; 1157 }; 1158 1159 timers17: timer@44008000 { 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 compatible = "st,stm32-timers"; 1163 reg = <0x44008000 0x400>; 1164 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1165 interrupt-names = "global"; 1166 clocks = <&rcc TIM17_K>; 1167 clock-names = "int"; 1168 dmas = <&dmamux1 111 0x400 0x1>, 1169 <&dmamux1 112 0x400 0x1>; 1170 dma-names = "ch1", "up"; 1171 access-controllers = <&etzpc 56>; 1172 status = "disabled"; 1173 1174 pwm { 1175 compatible = "st,stm32-pwm"; 1176 #pwm-cells = <3>; 1177 status = "disabled"; 1178 }; 1179 1180 timer@16 { 1181 compatible = "st,stm32h7-timer-trigger"; 1182 reg = <16>; 1183 status = "disabled"; 1184 }; 1185 }; 1186 1187 spi5: spi@44009000 { 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 compatible = "st,stm32h7-spi"; 1191 reg = <0x44009000 0x400>; 1192 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&rcc SPI5_K>; 1194 resets = <&rcc SPI5_R>; 1195 dmas = <&dmamux1 85 0x400 0x05>, 1196 <&dmamux1 86 0x400 0x05>; 1197 dma-names = "rx", "tx"; 1198 access-controllers = <&etzpc 57>; 1199 status = "disabled"; 1200 }; 1201 1202 sai1: sai@4400a000 { 1203 compatible = "st,stm32h7-sai"; 1204 #address-cells = <1>; 1205 #size-cells = <1>; 1206 ranges = <0 0x4400a000 0x400>; 1207 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1208 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1209 resets = <&rcc SAI1_R>; 1210 access-controllers = <&etzpc 58>; 1211 status = "disabled"; 1212 1213 sai1a: audio-controller@4400a004 { 1214 #sound-dai-cells = <0>; 1215 1216 compatible = "st,stm32-sai-sub-a"; 1217 reg = <0x4 0x20>; 1218 clocks = <&rcc SAI1_K>; 1219 clock-names = "sai_ck"; 1220 dmas = <&dmamux1 87 0x400 0x01>; 1221 status = "disabled"; 1222 }; 1223 1224 sai1b: audio-controller@4400a024 { 1225 #sound-dai-cells = <0>; 1226 compatible = "st,stm32-sai-sub-b"; 1227 reg = <0x24 0x20>; 1228 clocks = <&rcc SAI1_K>; 1229 clock-names = "sai_ck"; 1230 dmas = <&dmamux1 88 0x400 0x01>; 1231 status = "disabled"; 1232 }; 1233 }; 1234 1235 sai2: sai@4400b000 { 1236 compatible = "st,stm32h7-sai"; 1237 #address-cells = <1>; 1238 #size-cells = <1>; 1239 ranges = <0 0x4400b000 0x400>; 1240 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1241 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1242 resets = <&rcc SAI2_R>; 1243 access-controllers = <&etzpc 59>; 1244 status = "disabled"; 1245 1246 sai2a: audio-controller@4400b004 { 1247 #sound-dai-cells = <0>; 1248 compatible = "st,stm32-sai-sub-a"; 1249 reg = <0x4 0x20>; 1250 clocks = <&rcc SAI2_K>; 1251 clock-names = "sai_ck"; 1252 dmas = <&dmamux1 89 0x400 0x01>; 1253 status = "disabled"; 1254 }; 1255 1256 sai2b: audio-controller@4400b024 { 1257 #sound-dai-cells = <0>; 1258 compatible = "st,stm32-sai-sub-b"; 1259 reg = <0x24 0x20>; 1260 clocks = <&rcc SAI2_K>; 1261 clock-names = "sai_ck"; 1262 dmas = <&dmamux1 90 0x400 0x01>; 1263 status = "disabled"; 1264 }; 1265 }; 1266 1267 sai3: sai@4400c000 { 1268 compatible = "st,stm32h7-sai"; 1269 #address-cells = <1>; 1270 #size-cells = <1>; 1271 ranges = <0 0x4400c000 0x400>; 1272 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1273 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1274 resets = <&rcc SAI3_R>; 1275 access-controllers = <&etzpc 60>; 1276 status = "disabled"; 1277 1278 sai3a: audio-controller@4400c004 { 1279 #sound-dai-cells = <0>; 1280 compatible = "st,stm32-sai-sub-a"; 1281 reg = <0x04 0x20>; 1282 clocks = <&rcc SAI3_K>; 1283 clock-names = "sai_ck"; 1284 dmas = <&dmamux1 113 0x400 0x01>; 1285 status = "disabled"; 1286 }; 1287 1288 sai3b: audio-controller@4400c024 { 1289 #sound-dai-cells = <0>; 1290 compatible = "st,stm32-sai-sub-b"; 1291 reg = <0x24 0x20>; 1292 clocks = <&rcc SAI3_K>; 1293 clock-names = "sai_ck"; 1294 dmas = <&dmamux1 114 0x400 0x01>; 1295 status = "disabled"; 1296 }; 1297 }; 1298 1299 dfsdm: dfsdm@4400d000 { 1300 compatible = "st,stm32mp1-dfsdm"; 1301 reg = <0x4400d000 0x800>; 1302 clocks = <&rcc DFSDM_K>; 1303 clock-names = "dfsdm"; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 access-controllers = <&etzpc 61>; 1307 status = "disabled"; 1308 1309 dfsdm0: filter@0 { 1310 compatible = "st,stm32-dfsdm-adc"; 1311 #io-channel-cells = <1>; 1312 reg = <0>; 1313 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1314 dmas = <&dmamux1 101 0x400 0x01>; 1315 dma-names = "rx"; 1316 status = "disabled"; 1317 }; 1318 1319 dfsdm1: filter@1 { 1320 compatible = "st,stm32-dfsdm-adc"; 1321 #io-channel-cells = <1>; 1322 reg = <1>; 1323 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1324 dmas = <&dmamux1 102 0x400 0x01>; 1325 dma-names = "rx"; 1326 status = "disabled"; 1327 }; 1328 1329 dfsdm2: filter@2 { 1330 compatible = "st,stm32-dfsdm-adc"; 1331 #io-channel-cells = <1>; 1332 reg = <2>; 1333 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1334 dmas = <&dmamux1 103 0x400 0x01>; 1335 dma-names = "rx"; 1336 status = "disabled"; 1337 }; 1338 1339 dfsdm3: filter@3 { 1340 compatible = "st,stm32-dfsdm-adc"; 1341 #io-channel-cells = <1>; 1342 reg = <3>; 1343 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1344 dmas = <&dmamux1 104 0x400 0x01>; 1345 dma-names = "rx"; 1346 status = "disabled"; 1347 }; 1348 1349 dfsdm4: filter@4 { 1350 compatible = "st,stm32-dfsdm-adc"; 1351 #io-channel-cells = <1>; 1352 reg = <4>; 1353 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1354 dmas = <&dmamux1 91 0x400 0x01>; 1355 dma-names = "rx"; 1356 status = "disabled"; 1357 }; 1358 1359 dfsdm5: filter@5 { 1360 compatible = "st,stm32-dfsdm-adc"; 1361 #io-channel-cells = <1>; 1362 reg = <5>; 1363 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1364 dmas = <&dmamux1 92 0x400 0x01>; 1365 dma-names = "rx"; 1366 status = "disabled"; 1367 }; 1368 }; 1369 1370 dma1: dma-controller@48000000 { 1371 compatible = "st,stm32-dma"; 1372 reg = <0x48000000 0x400>; 1373 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1381 clocks = <&rcc DMA1>; 1382 resets = <&rcc DMA1_R>; 1383 #dma-cells = <4>; 1384 st,mem2mem; 1385 dma-requests = <8>; 1386 access-controllers = <&etzpc 88>; 1387 }; 1388 1389 dma2: dma-controller@48001000 { 1390 compatible = "st,stm32-dma"; 1391 reg = <0x48001000 0x400>; 1392 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1400 clocks = <&rcc DMA2>; 1401 resets = <&rcc DMA2_R>; 1402 #dma-cells = <4>; 1403 st,mem2mem; 1404 dma-requests = <8>; 1405 access-controllers = <&etzpc 89>; 1406 }; 1407 1408 dmamux1: dma-router@48002000 { 1409 compatible = "st,stm32h7-dmamux"; 1410 reg = <0x48002000 0x40>; 1411 #dma-cells = <3>; 1412 dma-requests = <128>; 1413 dma-masters = <&dma1 &dma2>; 1414 dma-channels = <16>; 1415 clocks = <&rcc DMAMUX>; 1416 resets = <&rcc DMAMUX_R>; 1417 access-controllers = <&etzpc 90>; 1418 }; 1419 1420 adc: adc@48003000 { 1421 compatible = "st,stm32mp1-adc-core"; 1422 reg = <0x48003000 0x400>; 1423 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1426 clock-names = "bus", "adc"; 1427 interrupt-controller; 1428 st,syscfg = <&syscfg>; 1429 #interrupt-cells = <1>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 access-controllers = <&etzpc 72>; 1433 status = "disabled"; 1434 1435 adc1: adc@0 { 1436 compatible = "st,stm32mp1-adc"; 1437 #io-channel-cells = <1>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 reg = <0x0>; 1441 interrupt-parent = <&adc>; 1442 interrupts = <0>; 1443 dmas = <&dmamux1 9 0x400 0x01>; 1444 dma-names = "rx"; 1445 status = "disabled"; 1446 }; 1447 1448 adc2: adc@100 { 1449 compatible = "st,stm32mp1-adc"; 1450 #io-channel-cells = <1>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 reg = <0x100>; 1454 interrupt-parent = <&adc>; 1455 interrupts = <1>; 1456 dmas = <&dmamux1 10 0x400 0x01>; 1457 dma-names = "rx"; 1458 nvmem-cells = <&vrefint>; 1459 nvmem-cell-names = "vrefint"; 1460 status = "disabled"; 1461 channel@13 { 1462 reg = <13>; 1463 label = "vrefint"; 1464 }; 1465 channel@14 { 1466 reg = <14>; 1467 label = "vddcore"; 1468 }; 1469 }; 1470 }; 1471 1472 sdmmc3: mmc@48004000 { 1473 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1474 arm,primecell-periphid = <0x00253180>; 1475 reg = <0x48004000 0x400>; 1476 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&rcc SDMMC3_K>; 1478 clock-names = "apb_pclk"; 1479 resets = <&rcc SDMMC3_R>; 1480 cap-sd-highspeed; 1481 cap-mmc-highspeed; 1482 max-frequency = <120000000>; 1483 access-controllers = <&etzpc 86>; 1484 status = "disabled"; 1485 }; 1486 1487 usbotg_hs: usb-otg@49000000 { 1488 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1489 reg = <0x49000000 0x10000>; 1490 clocks = <&rcc USBO_K>, <&usbphyc>; 1491 clock-names = "otg", "utmi"; 1492 resets = <&rcc USBO_R>; 1493 reset-names = "dwc2"; 1494 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1495 g-rx-fifo-size = <512>; 1496 g-np-tx-fifo-size = <32>; 1497 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1498 dr_mode = "otg"; 1499 otg-rev = <0x200>; 1500 usb33d-supply = <&usb33>; 1501 access-controllers = <&etzpc 85>; 1502 status = "disabled"; 1503 }; 1504 1505 dcmi: dcmi@4c006000 { 1506 compatible = "st,stm32-dcmi"; 1507 reg = <0x4c006000 0x400>; 1508 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1509 resets = <&rcc CAMITF_R>; 1510 clocks = <&rcc DCMI>; 1511 clock-names = "mclk"; 1512 dmas = <&dmamux1 75 0x400 0x01>; 1513 dma-names = "tx"; 1514 access-controllers = <&etzpc 70>; 1515 status = "disabled"; 1516 }; 1517 1518 lptimer2: timer@50021000 { 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 compatible = "st,stm32-lptimer"; 1522 reg = <0x50021000 0x400>; 1523 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1524 clocks = <&rcc LPTIM2_K>; 1525 clock-names = "mux"; 1526 wakeup-source; 1527 access-controllers = <&etzpc 64>; 1528 status = "disabled"; 1529 1530 pwm { 1531 compatible = "st,stm32-pwm-lp"; 1532 #pwm-cells = <3>; 1533 status = "disabled"; 1534 }; 1535 1536 trigger@1 { 1537 compatible = "st,stm32-lptimer-trigger"; 1538 reg = <1>; 1539 status = "disabled"; 1540 }; 1541 1542 counter { 1543 compatible = "st,stm32-lptimer-counter"; 1544 status = "disabled"; 1545 }; 1546 }; 1547 1548 lptimer3: timer@50022000 { 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 compatible = "st,stm32-lptimer"; 1552 reg = <0x50022000 0x400>; 1553 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&rcc LPTIM3_K>; 1555 clock-names = "mux"; 1556 wakeup-source; 1557 access-controllers = <&etzpc 65>; 1558 status = "disabled"; 1559 1560 pwm { 1561 compatible = "st,stm32-pwm-lp"; 1562 #pwm-cells = <3>; 1563 status = "disabled"; 1564 }; 1565 1566 trigger@2 { 1567 compatible = "st,stm32-lptimer-trigger"; 1568 reg = <2>; 1569 status = "disabled"; 1570 }; 1571 }; 1572 1573 lptimer4: timer@50023000 { 1574 compatible = "st,stm32-lptimer"; 1575 reg = <0x50023000 0x400>; 1576 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1577 clocks = <&rcc LPTIM4_K>; 1578 clock-names = "mux"; 1579 wakeup-source; 1580 access-controllers = <&etzpc 66>; 1581 status = "disabled"; 1582 1583 pwm { 1584 compatible = "st,stm32-pwm-lp"; 1585 #pwm-cells = <3>; 1586 status = "disabled"; 1587 }; 1588 }; 1589 1590 lptimer5: timer@50024000 { 1591 compatible = "st,stm32-lptimer"; 1592 reg = <0x50024000 0x400>; 1593 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&rcc LPTIM5_K>; 1595 clock-names = "mux"; 1596 wakeup-source; 1597 access-controllers = <&etzpc 67>; 1598 status = "disabled"; 1599 1600 pwm { 1601 compatible = "st,stm32-pwm-lp"; 1602 #pwm-cells = <3>; 1603 status = "disabled"; 1604 }; 1605 }; 1606 1607 vrefbuf: vrefbuf@50025000 { 1608 compatible = "st,stm32-vrefbuf"; 1609 reg = <0x50025000 0x8>; 1610 regulator-min-microvolt = <1500000>; 1611 regulator-max-microvolt = <2500000>; 1612 clocks = <&rcc VREF>; 1613 access-controllers = <&etzpc 69>; 1614 status = "disabled"; 1615 }; 1616 1617 sai4: sai@50027000 { 1618 compatible = "st,stm32h7-sai"; 1619 #address-cells = <1>; 1620 #size-cells = <1>; 1621 ranges = <0 0x50027000 0x400>; 1622 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1623 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1624 resets = <&rcc SAI4_R>; 1625 access-controllers = <&etzpc 68>; 1626 status = "disabled"; 1627 1628 sai4a: audio-controller@50027004 { 1629 #sound-dai-cells = <0>; 1630 compatible = "st,stm32-sai-sub-a"; 1631 reg = <0x04 0x20>; 1632 clocks = <&rcc SAI4_K>; 1633 clock-names = "sai_ck"; 1634 dmas = <&dmamux1 99 0x400 0x01>; 1635 status = "disabled"; 1636 }; 1637 1638 sai4b: audio-controller@50027024 { 1639 #sound-dai-cells = <0>; 1640 compatible = "st,stm32-sai-sub-b"; 1641 reg = <0x24 0x20>; 1642 clocks = <&rcc SAI4_K>; 1643 clock-names = "sai_ck"; 1644 dmas = <&dmamux1 100 0x400 0x01>; 1645 status = "disabled"; 1646 }; 1647 }; 1648 1649 hash1: hash@54002000 { 1650 compatible = "st,stm32f756-hash"; 1651 reg = <0x54002000 0x400>; 1652 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1653 clocks = <&rcc HASH1>; 1654 resets = <&rcc HASH1_R>; 1655 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1656 dma-names = "in"; 1657 dma-maxburst = <2>; 1658 access-controllers = <&etzpc 8>; 1659 status = "disabled"; 1660 }; 1661 1662 rng1: rng@54003000 { 1663 compatible = "st,stm32-rng"; 1664 reg = <0x54003000 0x400>; 1665 clocks = <&rcc RNG1_K>; 1666 resets = <&rcc RNG1_R>; 1667 access-controllers = <&etzpc 7>; 1668 status = "disabled"; 1669 }; 1670 1671 fmc: memory-controller@58002000 { 1672 #address-cells = <2>; 1673 #size-cells = <1>; 1674 compatible = "st,stm32mp1-fmc2-ebi"; 1675 reg = <0x58002000 0x1000>; 1676 clocks = <&rcc FMC_K>; 1677 resets = <&rcc FMC_R>; 1678 access-controllers = <&etzpc 91>; 1679 status = "disabled"; 1680 1681 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1682 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1683 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1684 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1685 <4 0 0x80000000 0x10000000>; /* NAND */ 1686 1687 nand-controller@4,0 { 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 compatible = "st,stm32mp1-fmc2-nfc"; 1691 reg = <4 0x00000000 0x1000>, 1692 <4 0x08010000 0x1000>, 1693 <4 0x08020000 0x1000>, 1694 <4 0x01000000 0x1000>, 1695 <4 0x09010000 0x1000>, 1696 <4 0x09020000 0x1000>; 1697 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1698 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1699 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1700 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1701 dma-names = "tx", "rx", "ecc"; 1702 status = "disabled"; 1703 }; 1704 }; 1705 1706 qspi: spi@58003000 { 1707 compatible = "st,stm32f469-qspi"; 1708 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1709 reg-names = "qspi", "qspi_mm"; 1710 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1711 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1712 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1713 dma-names = "tx", "rx"; 1714 clocks = <&rcc QSPI_K>; 1715 resets = <&rcc QSPI_R>; 1716 #address-cells = <1>; 1717 #size-cells = <0>; 1718 access-controllers = <&etzpc 92>; 1719 status = "disabled"; 1720 }; 1721 1722 ethernet0: ethernet@5800a000 { 1723 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1724 reg = <0x5800a000 0x2000>; 1725 reg-names = "stmmaceth"; 1726 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1727 interrupt-names = "macirq"; 1728 clock-names = "stmmaceth", 1729 "mac-clk-tx", 1730 "mac-clk-rx", 1731 "eth-ck", 1732 "ptp_ref", 1733 "ethstp"; 1734 clocks = <&rcc ETHMAC>, 1735 <&rcc ETHTX>, 1736 <&rcc ETHRX>, 1737 <&rcc ETHCK_K>, 1738 <&rcc ETHPTP_K>, 1739 <&rcc ETHSTP>; 1740 st,syscon = <&syscfg 0x4>; 1741 snps,mixed-burst; 1742 snps,pbl = <2>; 1743 snps,en-tx-lpi-clockgating; 1744 snps,axi-config = <&stmmac_axi_config_0>; 1745 snps,tso; 1746 access-controllers = <&etzpc 94>; 1747 status = "disabled"; 1748 1749 stmmac_axi_config_0: stmmac-axi-config { 1750 snps,wr_osr_lmt = <0x7>; 1751 snps,rd_osr_lmt = <0x7>; 1752 snps,blen = <0 0 0 0 16 8 4>; 1753 }; 1754 }; 1755 1756 usart1: serial@5c000000 { 1757 compatible = "st,stm32h7-uart"; 1758 reg = <0x5c000000 0x400>; 1759 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1760 clocks = <&rcc USART1_K>; 1761 wakeup-source; 1762 access-controllers = <&etzpc 3>; 1763 status = "disabled"; 1764 }; 1765 1766 spi6: spi@5c001000 { 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 compatible = "st,stm32h7-spi"; 1770 reg = <0x5c001000 0x400>; 1771 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1772 clocks = <&rcc SPI6_K>; 1773 resets = <&rcc SPI6_R>; 1774 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1775 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1776 access-controllers = <&etzpc 4>; 1777 dma-names = "rx", "tx"; 1778 status = "disabled"; 1779 }; 1780 1781 i2c4: i2c@5c002000 { 1782 compatible = "st,stm32mp15-i2c"; 1783 reg = <0x5c002000 0x400>; 1784 interrupt-names = "event", "error"; 1785 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1787 clocks = <&rcc I2C4_K>; 1788 resets = <&rcc I2C4_R>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1792 wakeup-source; 1793 i2c-analog-filter; 1794 access-controllers = <&etzpc 5>; 1795 status = "disabled"; 1796 }; 1797 1798 i2c6: i2c@5c009000 { 1799 compatible = "st,stm32mp15-i2c"; 1800 reg = <0x5c009000 0x400>; 1801 interrupt-names = "event", "error"; 1802 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1804 clocks = <&rcc I2C6_K>; 1805 resets = <&rcc I2C6_R>; 1806 #address-cells = <1>; 1807 #size-cells = <0>; 1808 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1809 wakeup-source; 1810 i2c-analog-filter; 1811 access-controllers = <&etzpc 12>; 1812 status = "disabled"; 1813 }; 1814 }; 1815 1816 tamp: tamp@5c00a000 { 1817 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 1818 reg = <0x5c00a000 0x400>; 1819 }; 1820 1821 /* 1822 * Break node order to solve dependency probe issue between 1823 * pinctrl and exti. 1824 */ 1825 pinctrl: pinctrl@50002000 { 1826 #address-cells = <1>; 1827 #size-cells = <1>; 1828 compatible = "st,stm32mp157-pinctrl"; 1829 ranges = <0 0x50002000 0xa400>; 1830 interrupt-parent = <&exti>; 1831 st,syscfg = <&exti 0x60 0xff>; 1832 1833 gpioa: gpio@50002000 { 1834 gpio-controller; 1835 #gpio-cells = <2>; 1836 interrupt-controller; 1837 #interrupt-cells = <2>; 1838 reg = <0x0 0x400>; 1839 clocks = <&rcc GPIOA>; 1840 st,bank-name = "GPIOA"; 1841 status = "disabled"; 1842 }; 1843 1844 gpiob: gpio@50003000 { 1845 gpio-controller; 1846 #gpio-cells = <2>; 1847 interrupt-controller; 1848 #interrupt-cells = <2>; 1849 reg = <0x1000 0x400>; 1850 clocks = <&rcc GPIOB>; 1851 st,bank-name = "GPIOB"; 1852 status = "disabled"; 1853 }; 1854 1855 gpioc: gpio@50004000 { 1856 gpio-controller; 1857 #gpio-cells = <2>; 1858 interrupt-controller; 1859 #interrupt-cells = <2>; 1860 reg = <0x2000 0x400>; 1861 clocks = <&rcc GPIOC>; 1862 st,bank-name = "GPIOC"; 1863 status = "disabled"; 1864 }; 1865 1866 gpiod: gpio@50005000 { 1867 gpio-controller; 1868 #gpio-cells = <2>; 1869 interrupt-controller; 1870 #interrupt-cells = <2>; 1871 reg = <0x3000 0x400>; 1872 clocks = <&rcc GPIOD>; 1873 st,bank-name = "GPIOD"; 1874 status = "disabled"; 1875 }; 1876 1877 gpioe: gpio@50006000 { 1878 gpio-controller; 1879 #gpio-cells = <2>; 1880 interrupt-controller; 1881 #interrupt-cells = <2>; 1882 reg = <0x4000 0x400>; 1883 clocks = <&rcc GPIOE>; 1884 st,bank-name = "GPIOE"; 1885 status = "disabled"; 1886 }; 1887 1888 gpiof: gpio@50007000 { 1889 gpio-controller; 1890 #gpio-cells = <2>; 1891 interrupt-controller; 1892 #interrupt-cells = <2>; 1893 reg = <0x5000 0x400>; 1894 clocks = <&rcc GPIOF>; 1895 st,bank-name = "GPIOF"; 1896 status = "disabled"; 1897 }; 1898 1899 gpiog: gpio@50008000 { 1900 gpio-controller; 1901 #gpio-cells = <2>; 1902 interrupt-controller; 1903 #interrupt-cells = <2>; 1904 reg = <0x6000 0x400>; 1905 clocks = <&rcc GPIOG>; 1906 st,bank-name = "GPIOG"; 1907 status = "disabled"; 1908 }; 1909 1910 gpioh: gpio@50009000 { 1911 gpio-controller; 1912 #gpio-cells = <2>; 1913 interrupt-controller; 1914 #interrupt-cells = <2>; 1915 reg = <0x7000 0x400>; 1916 clocks = <&rcc GPIOH>; 1917 st,bank-name = "GPIOH"; 1918 status = "disabled"; 1919 }; 1920 1921 gpioi: gpio@5000a000 { 1922 gpio-controller; 1923 #gpio-cells = <2>; 1924 interrupt-controller; 1925 #interrupt-cells = <2>; 1926 reg = <0x8000 0x400>; 1927 clocks = <&rcc GPIOI>; 1928 st,bank-name = "GPIOI"; 1929 status = "disabled"; 1930 }; 1931 1932 gpioj: gpio@5000b000 { 1933 gpio-controller; 1934 #gpio-cells = <2>; 1935 interrupt-controller; 1936 #interrupt-cells = <2>; 1937 reg = <0x9000 0x400>; 1938 clocks = <&rcc GPIOJ>; 1939 st,bank-name = "GPIOJ"; 1940 status = "disabled"; 1941 }; 1942 1943 gpiok: gpio@5000c000 { 1944 gpio-controller; 1945 #gpio-cells = <2>; 1946 interrupt-controller; 1947 #interrupt-cells = <2>; 1948 reg = <0xa000 0x400>; 1949 clocks = <&rcc GPIOK>; 1950 st,bank-name = "GPIOK"; 1951 status = "disabled"; 1952 }; 1953 }; 1954 1955 pinctrl_z: pinctrl@54004000 { 1956 #address-cells = <1>; 1957 #size-cells = <1>; 1958 compatible = "st,stm32mp157-z-pinctrl"; 1959 ranges = <0 0x54004000 0x400>; 1960 interrupt-parent = <&exti>; 1961 st,syscfg = <&exti 0x60 0xff>; 1962 1963 gpioz: gpio@54004000 { 1964 gpio-controller; 1965 #gpio-cells = <2>; 1966 interrupt-controller; 1967 #interrupt-cells = <2>; 1968 reg = <0 0x400>; 1969 clocks = <&rcc GPIOZ>; 1970 st,bank-name = "GPIOZ"; 1971 st,bank-ioport = <11>; 1972 status = "disabled"; 1973 }; 1974 }; 1975 }; 1976 1977 mlahb: ahb { 1978 compatible = "st,mlahb", "simple-bus"; 1979 #address-cells = <1>; 1980 #size-cells = <1>; 1981 ranges; 1982 dma-ranges = <0x00000000 0x38000000 0x10000>, 1983 <0x10000000 0x10000000 0x60000>, 1984 <0x30000000 0x30000000 0x60000>; 1985 1986 m4_rproc: m4@10000000 { 1987 compatible = "st,stm32mp1-m4"; 1988 reg = <0x10000000 0x40000>, 1989 <0x30000000 0x40000>, 1990 <0x38000000 0x10000>; 1991 resets = <&rcc MCU_R>; 1992 reset-names = "mcu_rst"; 1993 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 1994 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1995 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1996 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1997 status = "disabled"; 1998 }; 1999 }; 2000}; 2001