1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 clock-frequency = <650000000>; 21 device_type = "cpu"; 22 reg = <0>; 23 }; 24 }; 25 26 arm-pmu { 27 compatible = "arm,cortex-a7-pmu"; 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-affinity = <&cpu0>; 30 interrupt-parent = <&intc>; 31 }; 32 33 psci { 34 compatible = "arm,psci-1.0"; 35 method = "smc"; 36 }; 37 38 intc: interrupt-controller@a0021000 { 39 compatible = "arm,cortex-a7-gic"; 40 #interrupt-cells = <3>; 41 interrupt-controller; 42 reg = <0xa0021000 0x1000>, 43 <0xa0022000 0x2000>; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&intc>; 53 }; 54 55 clocks { 56 clk_hse: clk-hse { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <24000000>; 60 }; 61 62 clk_hsi: clk-hsi { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <64000000>; 66 }; 67 68 clk_lse: clk-lse { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 clock-frequency = <32768>; 72 }; 73 74 clk_lsi: clk-lsi { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <32000>; 78 }; 79 80 clk_csi: clk-csi { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <4000000>; 84 }; 85 }; 86 87 thermal-zones { 88 cpu_thermal: cpu-thermal { 89 polling-delay-passive = <0>; 90 polling-delay = <0>; 91 thermal-sensors = <&dts>; 92 93 trips { 94 cpu_alert1: cpu-alert1 { 95 temperature = <85000>; 96 hysteresis = <0>; 97 type = "passive"; 98 }; 99 100 cpu-crit { 101 temperature = <120000>; 102 hysteresis = <0>; 103 type = "critical"; 104 }; 105 }; 106 107 cooling-maps { 108 }; 109 }; 110 }; 111 112 booster: regulator-booster { 113 compatible = "st,stm32mp1-booster"; 114 st,syscfg = <&syscfg>; 115 status = "disabled"; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 interrupt-parent = <&intc>; 123 ranges; 124 125 ipcc: mailbox@4c001000 { 126 compatible = "st,stm32mp1-ipcc"; 127 #mbox-cells = <1>; 128 reg = <0x4c001000 0x400>; 129 st,proc-id = <0>; 130 interrupts-extended = 131 <&exti 61 1>, 132 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 133 interrupt-names = "rx", "tx"; 134 clocks = <&rcc IPCC>; 135 wakeup-source; 136 status = "disabled"; 137 }; 138 139 rcc: rcc@50000000 { 140 compatible = "st,stm32mp1-rcc", "syscon"; 141 reg = <0x50000000 0x1000>; 142 #clock-cells = <1>; 143 #reset-cells = <1>; 144 }; 145 146 pwr_regulators: pwr@50001000 { 147 compatible = "st,stm32mp1,pwr-reg"; 148 reg = <0x50001000 0x10>; 149 150 reg11: reg11 { 151 regulator-name = "reg11"; 152 regulator-min-microvolt = <1100000>; 153 regulator-max-microvolt = <1100000>; 154 }; 155 156 reg18: reg18 { 157 regulator-name = "reg18"; 158 regulator-min-microvolt = <1800000>; 159 regulator-max-microvolt = <1800000>; 160 }; 161 162 usb33: usb33 { 163 regulator-name = "usb33"; 164 regulator-min-microvolt = <3300000>; 165 regulator-max-microvolt = <3300000>; 166 }; 167 }; 168 169 pwr_mcu: pwr_mcu@50001014 { 170 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 171 reg = <0x50001014 0x4>; 172 }; 173 174 exti: interrupt-controller@5000d000 { 175 compatible = "st,stm32mp1-exti", "syscon"; 176 interrupt-controller; 177 #interrupt-cells = <2>; 178 reg = <0x5000d000 0x400>; 179 }; 180 181 syscfg: syscon@50020000 { 182 compatible = "st,stm32mp157-syscfg", "syscon"; 183 reg = <0x50020000 0x400>; 184 clocks = <&rcc SYSCFG>; 185 }; 186 187 dts: thermal@50028000 { 188 compatible = "st,stm32-thermal"; 189 reg = <0x50028000 0x100>; 190 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&rcc TMPSENS>; 192 clock-names = "pclk"; 193 #thermal-sensor-cells = <0>; 194 status = "disabled"; 195 }; 196 197 mdma1: dma-controller@58000000 { 198 compatible = "st,stm32h7-mdma"; 199 reg = <0x58000000 0x1000>; 200 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&rcc MDMA>; 202 resets = <&rcc MDMA_R>; 203 #dma-cells = <5>; 204 dma-channels = <32>; 205 dma-requests = <48>; 206 }; 207 208 sdmmc1: mmc@58005000 { 209 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 210 arm,primecell-periphid = <0x00253180>; 211 reg = <0x58005000 0x1000>; 212 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&rcc SDMMC1_K>; 214 clock-names = "apb_pclk"; 215 resets = <&rcc SDMMC1_R>; 216 cap-sd-highspeed; 217 cap-mmc-highspeed; 218 max-frequency = <120000000>; 219 status = "disabled"; 220 }; 221 222 sdmmc2: mmc@58007000 { 223 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 224 arm,primecell-periphid = <0x00253180>; 225 reg = <0x58007000 0x1000>; 226 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&rcc SDMMC2_K>; 228 clock-names = "apb_pclk"; 229 resets = <&rcc SDMMC2_R>; 230 cap-sd-highspeed; 231 cap-mmc-highspeed; 232 max-frequency = <120000000>; 233 status = "disabled"; 234 }; 235 236 crc1: crc@58009000 { 237 compatible = "st,stm32f7-crc"; 238 reg = <0x58009000 0x400>; 239 clocks = <&rcc CRC1>; 240 status = "disabled"; 241 }; 242 243 usbh_ohci: usb@5800c000 { 244 compatible = "generic-ohci"; 245 reg = <0x5800c000 0x1000>; 246 clocks = <&usbphyc>, <&rcc USBH>; 247 resets = <&rcc USBH_R>; 248 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 249 phys = <&usbphyc_port0>; 250 phy-names = "usb"; 251 status = "disabled"; 252 }; 253 254 usbh_ehci: usb@5800d000 { 255 compatible = "generic-ehci"; 256 reg = <0x5800d000 0x1000>; 257 clocks = <&usbphyc>, <&rcc USBH>; 258 resets = <&rcc USBH_R>; 259 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 260 companion = <&usbh_ohci>; 261 phys = <&usbphyc_port0>; 262 phy-names = "usb"; 263 status = "disabled"; 264 }; 265 266 ltdc: display-controller@5a001000 { 267 compatible = "st,stm32-ltdc"; 268 reg = <0x5a001000 0x400>; 269 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&rcc LTDC_PX>; 272 clock-names = "lcd"; 273 resets = <&rcc LTDC_R>; 274 status = "disabled"; 275 }; 276 277 iwdg2: watchdog@5a002000 { 278 compatible = "st,stm32mp1-iwdg"; 279 reg = <0x5a002000 0x400>; 280 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 281 clock-names = "pclk", "lsi"; 282 status = "disabled"; 283 }; 284 285 usbphyc: usbphyc@5a006000 { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 #clock-cells = <0>; 289 compatible = "st,stm32mp1-usbphyc"; 290 reg = <0x5a006000 0x1000>; 291 clocks = <&rcc USBPHY_K>; 292 resets = <&rcc USBPHY_R>; 293 vdda1v1-supply = <®11>; 294 vdda1v8-supply = <®18>; 295 status = "disabled"; 296 297 usbphyc_port0: usb-phy@0 { 298 #phy-cells = <0>; 299 reg = <0>; 300 }; 301 302 usbphyc_port1: usb-phy@1 { 303 #phy-cells = <1>; 304 reg = <1>; 305 }; 306 }; 307 308 rtc: rtc@5c004000 { 309 compatible = "st,stm32mp1-rtc"; 310 reg = <0x5c004000 0x400>; 311 clocks = <&rcc RTCAPB>, <&rcc RTC>; 312 clock-names = "pclk", "rtc_ck"; 313 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 314 status = "disabled"; 315 }; 316 317 bsec: efuse@5c005000 { 318 compatible = "st,stm32mp15-bsec"; 319 reg = <0x5c005000 0x400>; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 part_number_otp: part-number-otp@4 { 323 reg = <0x4 0x1>; 324 }; 325 vrefint: vrefin-cal@52 { 326 reg = <0x52 0x2>; 327 }; 328 ts_cal1: calib@5c { 329 reg = <0x5c 0x2>; 330 }; 331 ts_cal2: calib@5e { 332 reg = <0x5e 0x2>; 333 }; 334 }; 335 336 etzpc: bus@5c007000 { 337 compatible = "st,stm32-etzpc", "simple-bus"; 338 reg = <0x5c007000 0x400>; 339 #address-cells = <1>; 340 #size-cells = <1>; 341 #access-controller-cells = <1>; 342 ranges; 343 344 timers2: timer@40000000 { 345 #address-cells = <1>; 346 #size-cells = <0>; 347 compatible = "st,stm32-timers"; 348 reg = <0x40000000 0x400>; 349 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 350 interrupt-names = "global"; 351 clocks = <&rcc TIM2_K>; 352 clock-names = "int"; 353 dmas = <&dmamux1 18 0x400 0x1>, 354 <&dmamux1 19 0x400 0x1>, 355 <&dmamux1 20 0x400 0x1>, 356 <&dmamux1 21 0x400 0x1>, 357 <&dmamux1 22 0x400 0x1>; 358 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 359 access-controllers = <&etzpc 16>; 360 status = "disabled"; 361 362 pwm { 363 compatible = "st,stm32-pwm"; 364 #pwm-cells = <3>; 365 status = "disabled"; 366 }; 367 368 timer@1 { 369 compatible = "st,stm32h7-timer-trigger"; 370 reg = <1>; 371 status = "disabled"; 372 }; 373 374 counter { 375 compatible = "st,stm32-timer-counter"; 376 status = "disabled"; 377 }; 378 }; 379 380 timers3: timer@40001000 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 compatible = "st,stm32-timers"; 384 reg = <0x40001000 0x400>; 385 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 386 interrupt-names = "global"; 387 clocks = <&rcc TIM3_K>; 388 clock-names = "int"; 389 dmas = <&dmamux1 23 0x400 0x1>, 390 <&dmamux1 24 0x400 0x1>, 391 <&dmamux1 25 0x400 0x1>, 392 <&dmamux1 26 0x400 0x1>, 393 <&dmamux1 27 0x400 0x1>, 394 <&dmamux1 28 0x400 0x1>; 395 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 396 access-controllers = <&etzpc 17>; 397 status = "disabled"; 398 399 pwm { 400 compatible = "st,stm32-pwm"; 401 #pwm-cells = <3>; 402 status = "disabled"; 403 }; 404 405 timer@2 { 406 compatible = "st,stm32h7-timer-trigger"; 407 reg = <2>; 408 status = "disabled"; 409 }; 410 411 counter { 412 compatible = "st,stm32-timer-counter"; 413 status = "disabled"; 414 }; 415 }; 416 417 timers4: timer@40002000 { 418 #address-cells = <1>; 419 #size-cells = <0>; 420 compatible = "st,stm32-timers"; 421 reg = <0x40002000 0x400>; 422 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 423 interrupt-names = "global"; 424 clocks = <&rcc TIM4_K>; 425 clock-names = "int"; 426 dmas = <&dmamux1 29 0x400 0x1>, 427 <&dmamux1 30 0x400 0x1>, 428 <&dmamux1 31 0x400 0x1>, 429 <&dmamux1 32 0x400 0x1>; 430 dma-names = "ch1", "ch2", "ch3", "ch4"; 431 access-controllers = <&etzpc 18>; 432 status = "disabled"; 433 434 pwm { 435 compatible = "st,stm32-pwm"; 436 #pwm-cells = <3>; 437 status = "disabled"; 438 }; 439 440 timer@3 { 441 compatible = "st,stm32h7-timer-trigger"; 442 reg = <3>; 443 status = "disabled"; 444 }; 445 446 counter { 447 compatible = "st,stm32-timer-counter"; 448 status = "disabled"; 449 }; 450 }; 451 452 timers5: timer@40003000 { 453 #address-cells = <1>; 454 #size-cells = <0>; 455 compatible = "st,stm32-timers"; 456 reg = <0x40003000 0x400>; 457 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-names = "global"; 459 clocks = <&rcc TIM5_K>; 460 clock-names = "int"; 461 dmas = <&dmamux1 55 0x400 0x1>, 462 <&dmamux1 56 0x400 0x1>, 463 <&dmamux1 57 0x400 0x1>, 464 <&dmamux1 58 0x400 0x1>, 465 <&dmamux1 59 0x400 0x1>, 466 <&dmamux1 60 0x400 0x1>; 467 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 468 access-controllers = <&etzpc 19>; 469 status = "disabled"; 470 471 pwm { 472 compatible = "st,stm32-pwm"; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 timer@4 { 478 compatible = "st,stm32h7-timer-trigger"; 479 reg = <4>; 480 status = "disabled"; 481 }; 482 483 counter { 484 compatible = "st,stm32-timer-counter"; 485 status = "disabled"; 486 }; 487 }; 488 489 timers6: timer@40004000 { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 compatible = "st,stm32-timers"; 493 reg = <0x40004000 0x400>; 494 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "global"; 496 clocks = <&rcc TIM6_K>; 497 clock-names = "int"; 498 dmas = <&dmamux1 69 0x400 0x1>; 499 dma-names = "up"; 500 access-controllers = <&etzpc 20>; 501 status = "disabled"; 502 503 timer@5 { 504 compatible = "st,stm32h7-timer-trigger"; 505 reg = <5>; 506 status = "disabled"; 507 }; 508 }; 509 510 timers7: timer@40005000 { 511 #address-cells = <1>; 512 #size-cells = <0>; 513 compatible = "st,stm32-timers"; 514 reg = <0x40005000 0x400>; 515 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 516 interrupt-names = "global"; 517 clocks = <&rcc TIM7_K>; 518 clock-names = "int"; 519 dmas = <&dmamux1 70 0x400 0x1>; 520 dma-names = "up"; 521 access-controllers = <&etzpc 21>; 522 status = "disabled"; 523 524 timer@6 { 525 compatible = "st,stm32h7-timer-trigger"; 526 reg = <6>; 527 status = "disabled"; 528 }; 529 }; 530 531 timers12: timer@40006000 { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 compatible = "st,stm32-timers"; 535 reg = <0x40006000 0x400>; 536 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 537 interrupt-names = "global"; 538 clocks = <&rcc TIM12_K>; 539 clock-names = "int"; 540 access-controllers = <&etzpc 22>; 541 status = "disabled"; 542 543 pwm { 544 compatible = "st,stm32-pwm"; 545 #pwm-cells = <3>; 546 status = "disabled"; 547 }; 548 549 timer@11 { 550 compatible = "st,stm32h7-timer-trigger"; 551 reg = <11>; 552 status = "disabled"; 553 }; 554 }; 555 556 timers13: timer@40007000 { 557 #address-cells = <1>; 558 #size-cells = <0>; 559 compatible = "st,stm32-timers"; 560 reg = <0x40007000 0x400>; 561 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "global"; 563 clocks = <&rcc TIM13_K>; 564 clock-names = "int"; 565 access-controllers = <&etzpc 23>; 566 status = "disabled"; 567 568 pwm { 569 compatible = "st,stm32-pwm"; 570 #pwm-cells = <3>; 571 status = "disabled"; 572 }; 573 574 timer@12 { 575 compatible = "st,stm32h7-timer-trigger"; 576 reg = <12>; 577 status = "disabled"; 578 }; 579 }; 580 581 timers14: timer@40008000 { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 compatible = "st,stm32-timers"; 585 reg = <0x40008000 0x400>; 586 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "global"; 588 clocks = <&rcc TIM14_K>; 589 clock-names = "int"; 590 access-controllers = <&etzpc 24>; 591 status = "disabled"; 592 593 pwm { 594 compatible = "st,stm32-pwm"; 595 #pwm-cells = <3>; 596 status = "disabled"; 597 }; 598 599 timer@13 { 600 compatible = "st,stm32h7-timer-trigger"; 601 reg = <13>; 602 status = "disabled"; 603 }; 604 }; 605 606 lptimer1: timer@40009000 { 607 #address-cells = <1>; 608 #size-cells = <0>; 609 compatible = "st,stm32-lptimer"; 610 reg = <0x40009000 0x400>; 611 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&rcc LPTIM1_K>; 613 clock-names = "mux"; 614 wakeup-source; 615 access-controllers = <&etzpc 25>; 616 status = "disabled"; 617 618 pwm { 619 compatible = "st,stm32-pwm-lp"; 620 #pwm-cells = <3>; 621 status = "disabled"; 622 }; 623 624 trigger@0 { 625 compatible = "st,stm32-lptimer-trigger"; 626 reg = <0>; 627 status = "disabled"; 628 }; 629 630 counter { 631 compatible = "st,stm32-lptimer-counter"; 632 status = "disabled"; 633 }; 634 }; 635 636 i2s2: audio-controller@4000b000 { 637 compatible = "st,stm32h7-i2s"; 638 #sound-dai-cells = <0>; 639 reg = <0x4000b000 0x400>; 640 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 641 dmas = <&dmamux1 39 0x400 0x01>, 642 <&dmamux1 40 0x400 0x01>; 643 dma-names = "rx", "tx"; 644 access-controllers = <&etzpc 27>; 645 status = "disabled"; 646 }; 647 648 spi2: spi@4000b000 { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 compatible = "st,stm32h7-spi"; 652 reg = <0x4000b000 0x400>; 653 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&rcc SPI2_K>; 655 resets = <&rcc SPI2_R>; 656 dmas = <&dmamux1 39 0x400 0x05>, 657 <&dmamux1 40 0x400 0x05>; 658 dma-names = "rx", "tx"; 659 access-controllers = <&etzpc 27>; 660 status = "disabled"; 661 }; 662 663 i2s3: audio-controller@4000c000 { 664 compatible = "st,stm32h7-i2s"; 665 #sound-dai-cells = <0>; 666 reg = <0x4000c000 0x400>; 667 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 668 dmas = <&dmamux1 61 0x400 0x01>, 669 <&dmamux1 62 0x400 0x01>; 670 dma-names = "rx", "tx"; 671 access-controllers = <&etzpc 28>; 672 status = "disabled"; 673 }; 674 675 spi3: spi@4000c000 { 676 #address-cells = <1>; 677 #size-cells = <0>; 678 compatible = "st,stm32h7-spi"; 679 reg = <0x4000c000 0x400>; 680 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&rcc SPI3_K>; 682 resets = <&rcc SPI3_R>; 683 dmas = <&dmamux1 61 0x400 0x05>, 684 <&dmamux1 62 0x400 0x05>; 685 dma-names = "rx", "tx"; 686 access-controllers = <&etzpc 28>; 687 status = "disabled"; 688 }; 689 690 spdifrx: audio-controller@4000d000 { 691 compatible = "st,stm32h7-spdifrx"; 692 #sound-dai-cells = <0>; 693 reg = <0x4000d000 0x400>; 694 clocks = <&rcc SPDIF_K>; 695 clock-names = "kclk"; 696 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 697 dmas = <&dmamux1 93 0x400 0x01>, 698 <&dmamux1 94 0x400 0x01>; 699 dma-names = "rx", "rx-ctrl"; 700 access-controllers = <&etzpc 29>; 701 status = "disabled"; 702 }; 703 704 usart2: serial@4000e000 { 705 compatible = "st,stm32h7-uart"; 706 reg = <0x4000e000 0x400>; 707 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&rcc USART2_K>; 709 wakeup-source; 710 dmas = <&dmamux1 43 0x400 0x15>, 711 <&dmamux1 44 0x400 0x11>; 712 dma-names = "rx", "tx"; 713 access-controllers = <&etzpc 30>; 714 status = "disabled"; 715 }; 716 717 usart3: serial@4000f000 { 718 compatible = "st,stm32h7-uart"; 719 reg = <0x4000f000 0x400>; 720 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&rcc USART3_K>; 722 wakeup-source; 723 dmas = <&dmamux1 45 0x400 0x15>, 724 <&dmamux1 46 0x400 0x11>; 725 dma-names = "rx", "tx"; 726 access-controllers = <&etzpc 31>; 727 status = "disabled"; 728 }; 729 730 uart4: serial@40010000 { 731 compatible = "st,stm32h7-uart"; 732 reg = <0x40010000 0x400>; 733 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&rcc UART4_K>; 735 wakeup-source; 736 dmas = <&dmamux1 63 0x400 0x15>, 737 <&dmamux1 64 0x400 0x11>; 738 dma-names = "rx", "tx"; 739 access-controllers = <&etzpc 32>; 740 status = "disabled"; 741 }; 742 743 uart5: serial@40011000 { 744 compatible = "st,stm32h7-uart"; 745 reg = <0x40011000 0x400>; 746 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&rcc UART5_K>; 748 wakeup-source; 749 dmas = <&dmamux1 65 0x400 0x15>, 750 <&dmamux1 66 0x400 0x11>; 751 dma-names = "rx", "tx"; 752 access-controllers = <&etzpc 33>; 753 status = "disabled"; 754 }; 755 756 i2c1: i2c@40012000 { 757 compatible = "st,stm32mp15-i2c"; 758 reg = <0x40012000 0x400>; 759 interrupt-names = "event", "error"; 760 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&rcc I2C1_K>; 763 resets = <&rcc I2C1_R>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 st,syscfg-fmp = <&syscfg 0x4 0x1>; 767 wakeup-source; 768 i2c-analog-filter; 769 access-controllers = <&etzpc 34>; 770 status = "disabled"; 771 }; 772 773 i2c2: i2c@40013000 { 774 compatible = "st,stm32mp15-i2c"; 775 reg = <0x40013000 0x400>; 776 interrupt-names = "event", "error"; 777 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&rcc I2C2_K>; 780 resets = <&rcc I2C2_R>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 st,syscfg-fmp = <&syscfg 0x4 0x2>; 784 wakeup-source; 785 i2c-analog-filter; 786 access-controllers = <&etzpc 35>; 787 status = "disabled"; 788 }; 789 790 i2c3: i2c@40014000 { 791 compatible = "st,stm32mp15-i2c"; 792 reg = <0x40014000 0x400>; 793 interrupt-names = "event", "error"; 794 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&rcc I2C3_K>; 797 resets = <&rcc I2C3_R>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 st,syscfg-fmp = <&syscfg 0x4 0x4>; 801 wakeup-source; 802 i2c-analog-filter; 803 access-controllers = <&etzpc 36>; 804 status = "disabled"; 805 }; 806 807 i2c5: i2c@40015000 { 808 compatible = "st,stm32mp15-i2c"; 809 reg = <0x40015000 0x400>; 810 interrupt-names = "event", "error"; 811 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&rcc I2C5_K>; 814 resets = <&rcc I2C5_R>; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 st,syscfg-fmp = <&syscfg 0x4 0x10>; 818 wakeup-source; 819 i2c-analog-filter; 820 access-controllers = <&etzpc 37>; 821 status = "disabled"; 822 }; 823 824 cec: cec@40016000 { 825 compatible = "st,stm32-cec"; 826 reg = <0x40016000 0x400>; 827 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&rcc CEC_K>, <&rcc CEC>; 829 clock-names = "cec", "hdmi-cec"; 830 access-controllers = <&etzpc 38>; 831 status = "disabled"; 832 }; 833 834 dac: dac@40017000 { 835 compatible = "st,stm32h7-dac-core"; 836 reg = <0x40017000 0x400>; 837 clocks = <&rcc DAC12>; 838 clock-names = "pclk"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 access-controllers = <&etzpc 39>; 842 status = "disabled"; 843 844 dac1: dac@1 { 845 compatible = "st,stm32-dac"; 846 #io-channel-cells = <1>; 847 reg = <1>; 848 status = "disabled"; 849 }; 850 851 dac2: dac@2 { 852 compatible = "st,stm32-dac"; 853 #io-channel-cells = <1>; 854 reg = <2>; 855 status = "disabled"; 856 }; 857 }; 858 859 uart7: serial@40018000 { 860 compatible = "st,stm32h7-uart"; 861 reg = <0x40018000 0x400>; 862 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&rcc UART7_K>; 864 wakeup-source; 865 dmas = <&dmamux1 79 0x400 0x15>, 866 <&dmamux1 80 0x400 0x11>; 867 dma-names = "rx", "tx"; 868 access-controllers = <&etzpc 40>; 869 status = "disabled"; 870 }; 871 872 uart8: serial@40019000 { 873 compatible = "st,stm32h7-uart"; 874 reg = <0x40019000 0x400>; 875 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&rcc UART8_K>; 877 wakeup-source; 878 dmas = <&dmamux1 81 0x400 0x15>, 879 <&dmamux1 82 0x400 0x11>; 880 dma-names = "rx", "tx"; 881 access-controllers = <&etzpc 41>; 882 status = "disabled"; 883 }; 884 885 timers1: timer@44000000 { 886 #address-cells = <1>; 887 #size-cells = <0>; 888 compatible = "st,stm32-timers"; 889 reg = <0x44000000 0x400>; 890 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 894 interrupt-names = "brk", "up", "trg-com", "cc"; 895 clocks = <&rcc TIM1_K>; 896 clock-names = "int"; 897 dmas = <&dmamux1 11 0x400 0x1>, 898 <&dmamux1 12 0x400 0x1>, 899 <&dmamux1 13 0x400 0x1>, 900 <&dmamux1 14 0x400 0x1>, 901 <&dmamux1 15 0x400 0x1>, 902 <&dmamux1 16 0x400 0x1>, 903 <&dmamux1 17 0x400 0x1>; 904 dma-names = "ch1", "ch2", "ch3", "ch4", 905 "up", "trig", "com"; 906 access-controllers = <&etzpc 48>; 907 status = "disabled"; 908 909 pwm { 910 compatible = "st,stm32-pwm"; 911 #pwm-cells = <3>; 912 status = "disabled"; 913 }; 914 915 timer@0 { 916 compatible = "st,stm32h7-timer-trigger"; 917 reg = <0>; 918 status = "disabled"; 919 }; 920 921 counter { 922 compatible = "st,stm32-timer-counter"; 923 status = "disabled"; 924 }; 925 }; 926 927 timers8: timer@44001000 { 928 #address-cells = <1>; 929 #size-cells = <0>; 930 compatible = "st,stm32-timers"; 931 reg = <0x44001000 0x400>; 932 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 936 interrupt-names = "brk", "up", "trg-com", "cc"; 937 clocks = <&rcc TIM8_K>; 938 clock-names = "int"; 939 dmas = <&dmamux1 47 0x400 0x1>, 940 <&dmamux1 48 0x400 0x1>, 941 <&dmamux1 49 0x400 0x1>, 942 <&dmamux1 50 0x400 0x1>, 943 <&dmamux1 51 0x400 0x1>, 944 <&dmamux1 52 0x400 0x1>, 945 <&dmamux1 53 0x400 0x1>; 946 dma-names = "ch1", "ch2", "ch3", "ch4", 947 "up", "trig", "com"; 948 access-controllers = <&etzpc 49>; 949 status = "disabled"; 950 951 pwm { 952 compatible = "st,stm32-pwm"; 953 #pwm-cells = <3>; 954 status = "disabled"; 955 }; 956 957 timer@7 { 958 compatible = "st,stm32h7-timer-trigger"; 959 reg = <7>; 960 status = "disabled"; 961 }; 962 963 counter { 964 compatible = "st,stm32-timer-counter"; 965 status = "disabled"; 966 }; 967 }; 968 969 usart6: serial@44003000 { 970 compatible = "st,stm32h7-uart"; 971 reg = <0x44003000 0x400>; 972 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&rcc USART6_K>; 974 wakeup-source; 975 dmas = <&dmamux1 71 0x400 0x15>, 976 <&dmamux1 72 0x400 0x11>; 977 dma-names = "rx", "tx"; 978 access-controllers = <&etzpc 51>; 979 status = "disabled"; 980 }; 981 982 i2s1: audio-controller@44004000 { 983 compatible = "st,stm32h7-i2s"; 984 #sound-dai-cells = <0>; 985 reg = <0x44004000 0x400>; 986 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 987 dmas = <&dmamux1 37 0x400 0x01>, 988 <&dmamux1 38 0x400 0x01>; 989 dma-names = "rx", "tx"; 990 access-controllers = <&etzpc 52>; 991 status = "disabled"; 992 }; 993 994 spi1: spi@44004000 { 995 #address-cells = <1>; 996 #size-cells = <0>; 997 compatible = "st,stm32h7-spi"; 998 reg = <0x44004000 0x400>; 999 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&rcc SPI1_K>; 1001 resets = <&rcc SPI1_R>; 1002 dmas = <&dmamux1 37 0x400 0x05>, 1003 <&dmamux1 38 0x400 0x05>; 1004 dma-names = "rx", "tx"; 1005 access-controllers = <&etzpc 52>; 1006 status = "disabled"; 1007 }; 1008 1009 spi4: spi@44005000 { 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 compatible = "st,stm32h7-spi"; 1013 reg = <0x44005000 0x400>; 1014 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&rcc SPI4_K>; 1016 resets = <&rcc SPI4_R>; 1017 dmas = <&dmamux1 83 0x400 0x05>, 1018 <&dmamux1 84 0x400 0x05>; 1019 dma-names = "rx", "tx"; 1020 access-controllers = <&etzpc 53>; 1021 status = "disabled"; 1022 }; 1023 1024 timers15: timer@44006000 { 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 compatible = "st,stm32-timers"; 1028 reg = <0x44006000 0x400>; 1029 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1030 interrupt-names = "global"; 1031 clocks = <&rcc TIM15_K>; 1032 clock-names = "int"; 1033 dmas = <&dmamux1 105 0x400 0x1>, 1034 <&dmamux1 106 0x400 0x1>, 1035 <&dmamux1 107 0x400 0x1>, 1036 <&dmamux1 108 0x400 0x1>; 1037 dma-names = "ch1", "up", "trig", "com"; 1038 access-controllers = <&etzpc 54>; 1039 status = "disabled"; 1040 1041 pwm { 1042 compatible = "st,stm32-pwm"; 1043 #pwm-cells = <3>; 1044 status = "disabled"; 1045 }; 1046 1047 timer@14 { 1048 compatible = "st,stm32h7-timer-trigger"; 1049 reg = <14>; 1050 status = "disabled"; 1051 }; 1052 }; 1053 1054 timers16: timer@44007000 { 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 compatible = "st,stm32-timers"; 1058 reg = <0x44007000 0x400>; 1059 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1060 interrupt-names = "global"; 1061 clocks = <&rcc TIM16_K>; 1062 clock-names = "int"; 1063 dmas = <&dmamux1 109 0x400 0x1>, 1064 <&dmamux1 110 0x400 0x1>; 1065 dma-names = "ch1", "up"; 1066 access-controllers = <&etzpc 55>; 1067 status = "disabled"; 1068 1069 pwm { 1070 compatible = "st,stm32-pwm"; 1071 #pwm-cells = <3>; 1072 status = "disabled"; 1073 }; 1074 timer@15 { 1075 compatible = "st,stm32h7-timer-trigger"; 1076 reg = <15>; 1077 status = "disabled"; 1078 }; 1079 }; 1080 1081 timers17: timer@44008000 { 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 compatible = "st,stm32-timers"; 1085 reg = <0x44008000 0x400>; 1086 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1087 interrupt-names = "global"; 1088 clocks = <&rcc TIM17_K>; 1089 clock-names = "int"; 1090 dmas = <&dmamux1 111 0x400 0x1>, 1091 <&dmamux1 112 0x400 0x1>; 1092 dma-names = "ch1", "up"; 1093 access-controllers = <&etzpc 56>; 1094 status = "disabled"; 1095 1096 pwm { 1097 compatible = "st,stm32-pwm"; 1098 #pwm-cells = <3>; 1099 status = "disabled"; 1100 }; 1101 1102 timer@16 { 1103 compatible = "st,stm32h7-timer-trigger"; 1104 reg = <16>; 1105 status = "disabled"; 1106 }; 1107 }; 1108 1109 spi5: spi@44009000 { 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 compatible = "st,stm32h7-spi"; 1113 reg = <0x44009000 0x400>; 1114 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&rcc SPI5_K>; 1116 resets = <&rcc SPI5_R>; 1117 dmas = <&dmamux1 85 0x400 0x05>, 1118 <&dmamux1 86 0x400 0x05>; 1119 dma-names = "rx", "tx"; 1120 access-controllers = <&etzpc 57>; 1121 status = "disabled"; 1122 }; 1123 1124 sai1: sai@4400a000 { 1125 compatible = "st,stm32h7-sai"; 1126 #address-cells = <1>; 1127 #size-cells = <1>; 1128 ranges = <0 0x4400a000 0x400>; 1129 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1130 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1131 resets = <&rcc SAI1_R>; 1132 access-controllers = <&etzpc 58>; 1133 status = "disabled"; 1134 1135 sai1a: audio-controller@4400a004 { 1136 #sound-dai-cells = <0>; 1137 1138 compatible = "st,stm32-sai-sub-a"; 1139 reg = <0x4 0x20>; 1140 clocks = <&rcc SAI1_K>; 1141 clock-names = "sai_ck"; 1142 dmas = <&dmamux1 87 0x400 0x01>; 1143 status = "disabled"; 1144 }; 1145 1146 sai1b: audio-controller@4400a024 { 1147 #sound-dai-cells = <0>; 1148 compatible = "st,stm32-sai-sub-b"; 1149 reg = <0x24 0x20>; 1150 clocks = <&rcc SAI1_K>; 1151 clock-names = "sai_ck"; 1152 dmas = <&dmamux1 88 0x400 0x01>; 1153 status = "disabled"; 1154 }; 1155 }; 1156 1157 sai2: sai@4400b000 { 1158 compatible = "st,stm32h7-sai"; 1159 #address-cells = <1>; 1160 #size-cells = <1>; 1161 ranges = <0 0x4400b000 0x400>; 1162 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1163 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1164 resets = <&rcc SAI2_R>; 1165 access-controllers = <&etzpc 59>; 1166 status = "disabled"; 1167 1168 sai2a: audio-controller@4400b004 { 1169 #sound-dai-cells = <0>; 1170 compatible = "st,stm32-sai-sub-a"; 1171 reg = <0x4 0x20>; 1172 clocks = <&rcc SAI2_K>; 1173 clock-names = "sai_ck"; 1174 dmas = <&dmamux1 89 0x400 0x01>; 1175 status = "disabled"; 1176 }; 1177 1178 sai2b: audio-controller@4400b024 { 1179 #sound-dai-cells = <0>; 1180 compatible = "st,stm32-sai-sub-b"; 1181 reg = <0x24 0x20>; 1182 clocks = <&rcc SAI2_K>; 1183 clock-names = "sai_ck"; 1184 dmas = <&dmamux1 90 0x400 0x01>; 1185 status = "disabled"; 1186 }; 1187 }; 1188 1189 sai3: sai@4400c000 { 1190 compatible = "st,stm32h7-sai"; 1191 #address-cells = <1>; 1192 #size-cells = <1>; 1193 ranges = <0 0x4400c000 0x400>; 1194 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1195 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1196 resets = <&rcc SAI3_R>; 1197 access-controllers = <&etzpc 60>; 1198 status = "disabled"; 1199 1200 sai3a: audio-controller@4400c004 { 1201 #sound-dai-cells = <0>; 1202 compatible = "st,stm32-sai-sub-a"; 1203 reg = <0x04 0x20>; 1204 clocks = <&rcc SAI3_K>; 1205 clock-names = "sai_ck"; 1206 dmas = <&dmamux1 113 0x400 0x01>; 1207 status = "disabled"; 1208 }; 1209 1210 sai3b: audio-controller@4400c024 { 1211 #sound-dai-cells = <0>; 1212 compatible = "st,stm32-sai-sub-b"; 1213 reg = <0x24 0x20>; 1214 clocks = <&rcc SAI3_K>; 1215 clock-names = "sai_ck"; 1216 dmas = <&dmamux1 114 0x400 0x01>; 1217 status = "disabled"; 1218 }; 1219 }; 1220 1221 dfsdm: dfsdm@4400d000 { 1222 compatible = "st,stm32mp1-dfsdm"; 1223 reg = <0x4400d000 0x800>; 1224 clocks = <&rcc DFSDM_K>; 1225 clock-names = "dfsdm"; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 access-controllers = <&etzpc 61>; 1229 status = "disabled"; 1230 1231 dfsdm0: filter@0 { 1232 compatible = "st,stm32-dfsdm-adc"; 1233 #io-channel-cells = <1>; 1234 reg = <0>; 1235 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1236 dmas = <&dmamux1 101 0x400 0x01>; 1237 dma-names = "rx"; 1238 status = "disabled"; 1239 }; 1240 1241 dfsdm1: filter@1 { 1242 compatible = "st,stm32-dfsdm-adc"; 1243 #io-channel-cells = <1>; 1244 reg = <1>; 1245 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1246 dmas = <&dmamux1 102 0x400 0x01>; 1247 dma-names = "rx"; 1248 status = "disabled"; 1249 }; 1250 1251 dfsdm2: filter@2 { 1252 compatible = "st,stm32-dfsdm-adc"; 1253 #io-channel-cells = <1>; 1254 reg = <2>; 1255 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1256 dmas = <&dmamux1 103 0x400 0x01>; 1257 dma-names = "rx"; 1258 status = "disabled"; 1259 }; 1260 1261 dfsdm3: filter@3 { 1262 compatible = "st,stm32-dfsdm-adc"; 1263 #io-channel-cells = <1>; 1264 reg = <3>; 1265 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1266 dmas = <&dmamux1 104 0x400 0x01>; 1267 dma-names = "rx"; 1268 status = "disabled"; 1269 }; 1270 1271 dfsdm4: filter@4 { 1272 compatible = "st,stm32-dfsdm-adc"; 1273 #io-channel-cells = <1>; 1274 reg = <4>; 1275 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1276 dmas = <&dmamux1 91 0x400 0x01>; 1277 dma-names = "rx"; 1278 status = "disabled"; 1279 }; 1280 1281 dfsdm5: filter@5 { 1282 compatible = "st,stm32-dfsdm-adc"; 1283 #io-channel-cells = <1>; 1284 reg = <5>; 1285 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1286 dmas = <&dmamux1 92 0x400 0x01>; 1287 dma-names = "rx"; 1288 status = "disabled"; 1289 }; 1290 }; 1291 1292 dma1: dma-controller@48000000 { 1293 compatible = "st,stm32-dma"; 1294 reg = <0x48000000 0x400>; 1295 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&rcc DMA1>; 1304 resets = <&rcc DMA1_R>; 1305 #dma-cells = <4>; 1306 st,mem2mem; 1307 dma-requests = <8>; 1308 access-controllers = <&etzpc 88>; 1309 }; 1310 1311 dma2: dma-controller@48001000 { 1312 compatible = "st,stm32-dma"; 1313 reg = <0x48001000 0x400>; 1314 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1322 clocks = <&rcc DMA2>; 1323 resets = <&rcc DMA2_R>; 1324 #dma-cells = <4>; 1325 st,mem2mem; 1326 dma-requests = <8>; 1327 access-controllers = <&etzpc 89>; 1328 }; 1329 1330 dmamux1: dma-router@48002000 { 1331 compatible = "st,stm32h7-dmamux"; 1332 reg = <0x48002000 0x40>; 1333 #dma-cells = <3>; 1334 dma-requests = <128>; 1335 dma-masters = <&dma1 &dma2>; 1336 dma-channels = <16>; 1337 clocks = <&rcc DMAMUX>; 1338 resets = <&rcc DMAMUX_R>; 1339 access-controllers = <&etzpc 90>; 1340 }; 1341 1342 adc: adc@48003000 { 1343 compatible = "st,stm32mp1-adc-core"; 1344 reg = <0x48003000 0x400>; 1345 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1347 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1348 clock-names = "bus", "adc"; 1349 interrupt-controller; 1350 st,syscfg = <&syscfg>; 1351 #interrupt-cells = <1>; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 access-controllers = <&etzpc 72>; 1355 status = "disabled"; 1356 1357 adc1: adc@0 { 1358 compatible = "st,stm32mp1-adc"; 1359 #io-channel-cells = <1>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 reg = <0x0>; 1363 interrupt-parent = <&adc>; 1364 interrupts = <0>; 1365 dmas = <&dmamux1 9 0x400 0x01>; 1366 dma-names = "rx"; 1367 status = "disabled"; 1368 }; 1369 1370 adc2: adc@100 { 1371 compatible = "st,stm32mp1-adc"; 1372 #io-channel-cells = <1>; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 reg = <0x100>; 1376 interrupt-parent = <&adc>; 1377 interrupts = <1>; 1378 dmas = <&dmamux1 10 0x400 0x01>; 1379 dma-names = "rx"; 1380 nvmem-cells = <&vrefint>; 1381 nvmem-cell-names = "vrefint"; 1382 status = "disabled"; 1383 channel@13 { 1384 reg = <13>; 1385 label = "vrefint"; 1386 }; 1387 channel@14 { 1388 reg = <14>; 1389 label = "vddcore"; 1390 }; 1391 }; 1392 }; 1393 1394 sdmmc3: mmc@48004000 { 1395 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1396 arm,primecell-periphid = <0x00253180>; 1397 reg = <0x48004000 0x400>; 1398 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&rcc SDMMC3_K>; 1400 clock-names = "apb_pclk"; 1401 resets = <&rcc SDMMC3_R>; 1402 cap-sd-highspeed; 1403 cap-mmc-highspeed; 1404 max-frequency = <120000000>; 1405 access-controllers = <&etzpc 86>; 1406 status = "disabled"; 1407 }; 1408 1409 usbotg_hs: usb-otg@49000000 { 1410 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1411 reg = <0x49000000 0x10000>; 1412 clocks = <&rcc USBO_K>, <&usbphyc>; 1413 clock-names = "otg", "utmi"; 1414 resets = <&rcc USBO_R>; 1415 reset-names = "dwc2"; 1416 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1417 g-rx-fifo-size = <512>; 1418 g-np-tx-fifo-size = <32>; 1419 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1420 dr_mode = "otg"; 1421 otg-rev = <0x200>; 1422 usb33d-supply = <&usb33>; 1423 access-controllers = <&etzpc 85>; 1424 status = "disabled"; 1425 }; 1426 1427 dcmi: dcmi@4c006000 { 1428 compatible = "st,stm32-dcmi"; 1429 reg = <0x4c006000 0x400>; 1430 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1431 resets = <&rcc CAMITF_R>; 1432 clocks = <&rcc DCMI>; 1433 clock-names = "mclk"; 1434 dmas = <&dmamux1 75 0x400 0x01>; 1435 dma-names = "tx"; 1436 access-controllers = <&etzpc 70>; 1437 status = "disabled"; 1438 }; 1439 1440 lptimer2: timer@50021000 { 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 compatible = "st,stm32-lptimer"; 1444 reg = <0x50021000 0x400>; 1445 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&rcc LPTIM2_K>; 1447 clock-names = "mux"; 1448 wakeup-source; 1449 access-controllers = <&etzpc 64>; 1450 status = "disabled"; 1451 1452 pwm { 1453 compatible = "st,stm32-pwm-lp"; 1454 #pwm-cells = <3>; 1455 status = "disabled"; 1456 }; 1457 1458 trigger@1 { 1459 compatible = "st,stm32-lptimer-trigger"; 1460 reg = <1>; 1461 status = "disabled"; 1462 }; 1463 1464 counter { 1465 compatible = "st,stm32-lptimer-counter"; 1466 status = "disabled"; 1467 }; 1468 }; 1469 1470 lptimer3: timer@50022000 { 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 compatible = "st,stm32-lptimer"; 1474 reg = <0x50022000 0x400>; 1475 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1476 clocks = <&rcc LPTIM3_K>; 1477 clock-names = "mux"; 1478 wakeup-source; 1479 access-controllers = <&etzpc 65>; 1480 status = "disabled"; 1481 1482 pwm { 1483 compatible = "st,stm32-pwm-lp"; 1484 #pwm-cells = <3>; 1485 status = "disabled"; 1486 }; 1487 1488 trigger@2 { 1489 compatible = "st,stm32-lptimer-trigger"; 1490 reg = <2>; 1491 status = "disabled"; 1492 }; 1493 }; 1494 1495 lptimer4: timer@50023000 { 1496 compatible = "st,stm32-lptimer"; 1497 reg = <0x50023000 0x400>; 1498 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1499 clocks = <&rcc LPTIM4_K>; 1500 clock-names = "mux"; 1501 wakeup-source; 1502 access-controllers = <&etzpc 66>; 1503 status = "disabled"; 1504 1505 pwm { 1506 compatible = "st,stm32-pwm-lp"; 1507 #pwm-cells = <3>; 1508 status = "disabled"; 1509 }; 1510 }; 1511 1512 lptimer5: timer@50024000 { 1513 compatible = "st,stm32-lptimer"; 1514 reg = <0x50024000 0x400>; 1515 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&rcc LPTIM5_K>; 1517 clock-names = "mux"; 1518 wakeup-source; 1519 access-controllers = <&etzpc 67>; 1520 status = "disabled"; 1521 1522 pwm { 1523 compatible = "st,stm32-pwm-lp"; 1524 #pwm-cells = <3>; 1525 status = "disabled"; 1526 }; 1527 }; 1528 1529 vrefbuf: vrefbuf@50025000 { 1530 compatible = "st,stm32-vrefbuf"; 1531 reg = <0x50025000 0x8>; 1532 regulator-min-microvolt = <1500000>; 1533 regulator-max-microvolt = <2500000>; 1534 clocks = <&rcc VREF>; 1535 access-controllers = <&etzpc 69>; 1536 status = "disabled"; 1537 }; 1538 1539 sai4: sai@50027000 { 1540 compatible = "st,stm32h7-sai"; 1541 #address-cells = <1>; 1542 #size-cells = <1>; 1543 ranges = <0 0x50027000 0x400>; 1544 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1545 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1546 resets = <&rcc SAI4_R>; 1547 access-controllers = <&etzpc 68>; 1548 status = "disabled"; 1549 1550 sai4a: audio-controller@50027004 { 1551 #sound-dai-cells = <0>; 1552 compatible = "st,stm32-sai-sub-a"; 1553 reg = <0x04 0x20>; 1554 clocks = <&rcc SAI4_K>; 1555 clock-names = "sai_ck"; 1556 dmas = <&dmamux1 99 0x400 0x01>; 1557 status = "disabled"; 1558 }; 1559 1560 sai4b: audio-controller@50027024 { 1561 #sound-dai-cells = <0>; 1562 compatible = "st,stm32-sai-sub-b"; 1563 reg = <0x24 0x20>; 1564 clocks = <&rcc SAI4_K>; 1565 clock-names = "sai_ck"; 1566 dmas = <&dmamux1 100 0x400 0x01>; 1567 status = "disabled"; 1568 }; 1569 }; 1570 1571 hash1: hash@54002000 { 1572 compatible = "st,stm32f756-hash"; 1573 reg = <0x54002000 0x400>; 1574 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1575 clocks = <&rcc HASH1>; 1576 resets = <&rcc HASH1_R>; 1577 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1578 dma-names = "in"; 1579 dma-maxburst = <2>; 1580 access-controllers = <&etzpc 8>; 1581 status = "disabled"; 1582 }; 1583 1584 rng1: rng@54003000 { 1585 compatible = "st,stm32-rng"; 1586 reg = <0x54003000 0x400>; 1587 clocks = <&rcc RNG1_K>; 1588 resets = <&rcc RNG1_R>; 1589 access-controllers = <&etzpc 7>; 1590 status = "disabled"; 1591 }; 1592 1593 fmc: memory-controller@58002000 { 1594 #address-cells = <2>; 1595 #size-cells = <1>; 1596 compatible = "st,stm32mp1-fmc2-ebi"; 1597 reg = <0x58002000 0x1000>; 1598 clocks = <&rcc FMC_K>; 1599 resets = <&rcc FMC_R>; 1600 access-controllers = <&etzpc 91>; 1601 status = "disabled"; 1602 1603 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1604 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1605 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1606 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1607 <4 0 0x80000000 0x10000000>; /* NAND */ 1608 1609 nand-controller@4,0 { 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 compatible = "st,stm32mp1-fmc2-nfc"; 1613 reg = <4 0x00000000 0x1000>, 1614 <4 0x08010000 0x1000>, 1615 <4 0x08020000 0x1000>, 1616 <4 0x01000000 0x1000>, 1617 <4 0x09010000 0x1000>, 1618 <4 0x09020000 0x1000>; 1619 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1620 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1621 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1622 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1623 dma-names = "tx", "rx", "ecc"; 1624 status = "disabled"; 1625 }; 1626 }; 1627 1628 qspi: spi@58003000 { 1629 compatible = "st,stm32f469-qspi"; 1630 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1631 reg-names = "qspi", "qspi_mm"; 1632 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1633 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1634 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1635 dma-names = "tx", "rx"; 1636 clocks = <&rcc QSPI_K>; 1637 resets = <&rcc QSPI_R>; 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 access-controllers = <&etzpc 92>; 1641 status = "disabled"; 1642 }; 1643 1644 ethernet0: ethernet@5800a000 { 1645 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1646 reg = <0x5800a000 0x2000>; 1647 reg-names = "stmmaceth"; 1648 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1649 interrupt-names = "macirq"; 1650 clock-names = "stmmaceth", 1651 "mac-clk-tx", 1652 "mac-clk-rx", 1653 "eth-ck", 1654 "ptp_ref", 1655 "ethstp"; 1656 clocks = <&rcc ETHMAC>, 1657 <&rcc ETHTX>, 1658 <&rcc ETHRX>, 1659 <&rcc ETHCK_K>, 1660 <&rcc ETHPTP_K>, 1661 <&rcc ETHSTP>; 1662 st,syscon = <&syscfg 0x4>; 1663 snps,mixed-burst; 1664 snps,pbl = <2>; 1665 snps,en-tx-lpi-clockgating; 1666 snps,axi-config = <&stmmac_axi_config_0>; 1667 snps,tso; 1668 access-controllers = <&etzpc 94>; 1669 status = "disabled"; 1670 1671 stmmac_axi_config_0: stmmac-axi-config { 1672 snps,wr_osr_lmt = <0x7>; 1673 snps,rd_osr_lmt = <0x7>; 1674 snps,blen = <0 0 0 0 16 8 4>; 1675 }; 1676 }; 1677 1678 usart1: serial@5c000000 { 1679 compatible = "st,stm32h7-uart"; 1680 reg = <0x5c000000 0x400>; 1681 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1682 clocks = <&rcc USART1_K>; 1683 wakeup-source; 1684 access-controllers = <&etzpc 3>; 1685 status = "disabled"; 1686 }; 1687 1688 spi6: spi@5c001000 { 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 compatible = "st,stm32h7-spi"; 1692 reg = <0x5c001000 0x400>; 1693 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1694 clocks = <&rcc SPI6_K>; 1695 resets = <&rcc SPI6_R>; 1696 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1697 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1698 access-controllers = <&etzpc 4>; 1699 dma-names = "rx", "tx"; 1700 status = "disabled"; 1701 }; 1702 1703 i2c4: i2c@5c002000 { 1704 compatible = "st,stm32mp15-i2c"; 1705 reg = <0x5c002000 0x400>; 1706 interrupt-names = "event", "error"; 1707 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1709 clocks = <&rcc I2C4_K>; 1710 resets = <&rcc I2C4_R>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1714 wakeup-source; 1715 i2c-analog-filter; 1716 access-controllers = <&etzpc 5>; 1717 status = "disabled"; 1718 }; 1719 1720 i2c6: i2c@5c009000 { 1721 compatible = "st,stm32mp15-i2c"; 1722 reg = <0x5c009000 0x400>; 1723 interrupt-names = "event", "error"; 1724 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1726 clocks = <&rcc I2C6_K>; 1727 resets = <&rcc I2C6_R>; 1728 #address-cells = <1>; 1729 #size-cells = <0>; 1730 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1731 wakeup-source; 1732 i2c-analog-filter; 1733 access-controllers = <&etzpc 12>; 1734 status = "disabled"; 1735 }; 1736 }; 1737 1738 tamp: tamp@5c00a000 { 1739 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 1740 reg = <0x5c00a000 0x400>; 1741 }; 1742 1743 /* 1744 * Break node order to solve dependency probe issue between 1745 * pinctrl and exti. 1746 */ 1747 pinctrl: pinctrl@50002000 { 1748 #address-cells = <1>; 1749 #size-cells = <1>; 1750 compatible = "st,stm32mp157-pinctrl"; 1751 ranges = <0 0x50002000 0xa400>; 1752 interrupt-parent = <&exti>; 1753 st,syscfg = <&exti 0x60 0xff>; 1754 1755 gpioa: gpio@50002000 { 1756 gpio-controller; 1757 #gpio-cells = <2>; 1758 interrupt-controller; 1759 #interrupt-cells = <2>; 1760 reg = <0x0 0x400>; 1761 clocks = <&rcc GPIOA>; 1762 st,bank-name = "GPIOA"; 1763 status = "disabled"; 1764 }; 1765 1766 gpiob: gpio@50003000 { 1767 gpio-controller; 1768 #gpio-cells = <2>; 1769 interrupt-controller; 1770 #interrupt-cells = <2>; 1771 reg = <0x1000 0x400>; 1772 clocks = <&rcc GPIOB>; 1773 st,bank-name = "GPIOB"; 1774 status = "disabled"; 1775 }; 1776 1777 gpioc: gpio@50004000 { 1778 gpio-controller; 1779 #gpio-cells = <2>; 1780 interrupt-controller; 1781 #interrupt-cells = <2>; 1782 reg = <0x2000 0x400>; 1783 clocks = <&rcc GPIOC>; 1784 st,bank-name = "GPIOC"; 1785 status = "disabled"; 1786 }; 1787 1788 gpiod: gpio@50005000 { 1789 gpio-controller; 1790 #gpio-cells = <2>; 1791 interrupt-controller; 1792 #interrupt-cells = <2>; 1793 reg = <0x3000 0x400>; 1794 clocks = <&rcc GPIOD>; 1795 st,bank-name = "GPIOD"; 1796 status = "disabled"; 1797 }; 1798 1799 gpioe: gpio@50006000 { 1800 gpio-controller; 1801 #gpio-cells = <2>; 1802 interrupt-controller; 1803 #interrupt-cells = <2>; 1804 reg = <0x4000 0x400>; 1805 clocks = <&rcc GPIOE>; 1806 st,bank-name = "GPIOE"; 1807 status = "disabled"; 1808 }; 1809 1810 gpiof: gpio@50007000 { 1811 gpio-controller; 1812 #gpio-cells = <2>; 1813 interrupt-controller; 1814 #interrupt-cells = <2>; 1815 reg = <0x5000 0x400>; 1816 clocks = <&rcc GPIOF>; 1817 st,bank-name = "GPIOF"; 1818 status = "disabled"; 1819 }; 1820 1821 gpiog: gpio@50008000 { 1822 gpio-controller; 1823 #gpio-cells = <2>; 1824 interrupt-controller; 1825 #interrupt-cells = <2>; 1826 reg = <0x6000 0x400>; 1827 clocks = <&rcc GPIOG>; 1828 st,bank-name = "GPIOG"; 1829 status = "disabled"; 1830 }; 1831 1832 gpioh: gpio@50009000 { 1833 gpio-controller; 1834 #gpio-cells = <2>; 1835 interrupt-controller; 1836 #interrupt-cells = <2>; 1837 reg = <0x7000 0x400>; 1838 clocks = <&rcc GPIOH>; 1839 st,bank-name = "GPIOH"; 1840 status = "disabled"; 1841 }; 1842 1843 gpioi: gpio@5000a000 { 1844 gpio-controller; 1845 #gpio-cells = <2>; 1846 interrupt-controller; 1847 #interrupt-cells = <2>; 1848 reg = <0x8000 0x400>; 1849 clocks = <&rcc GPIOI>; 1850 st,bank-name = "GPIOI"; 1851 status = "disabled"; 1852 }; 1853 1854 gpioj: gpio@5000b000 { 1855 gpio-controller; 1856 #gpio-cells = <2>; 1857 interrupt-controller; 1858 #interrupt-cells = <2>; 1859 reg = <0x9000 0x400>; 1860 clocks = <&rcc GPIOJ>; 1861 st,bank-name = "GPIOJ"; 1862 status = "disabled"; 1863 }; 1864 1865 gpiok: gpio@5000c000 { 1866 gpio-controller; 1867 #gpio-cells = <2>; 1868 interrupt-controller; 1869 #interrupt-cells = <2>; 1870 reg = <0xa000 0x400>; 1871 clocks = <&rcc GPIOK>; 1872 st,bank-name = "GPIOK"; 1873 status = "disabled"; 1874 }; 1875 }; 1876 1877 pinctrl_z: pinctrl@54004000 { 1878 #address-cells = <1>; 1879 #size-cells = <1>; 1880 compatible = "st,stm32mp157-z-pinctrl"; 1881 ranges = <0 0x54004000 0x400>; 1882 interrupt-parent = <&exti>; 1883 st,syscfg = <&exti 0x60 0xff>; 1884 1885 gpioz: gpio@54004000 { 1886 gpio-controller; 1887 #gpio-cells = <2>; 1888 interrupt-controller; 1889 #interrupt-cells = <2>; 1890 reg = <0 0x400>; 1891 clocks = <&rcc GPIOZ>; 1892 st,bank-name = "GPIOZ"; 1893 st,bank-ioport = <11>; 1894 status = "disabled"; 1895 }; 1896 }; 1897 }; 1898 1899 mlahb: ahb { 1900 compatible = "st,mlahb", "simple-bus"; 1901 #address-cells = <1>; 1902 #size-cells = <1>; 1903 ranges; 1904 dma-ranges = <0x00000000 0x38000000 0x10000>, 1905 <0x10000000 0x10000000 0x60000>, 1906 <0x30000000 0x30000000 0x60000>; 1907 1908 m4_rproc: m4@10000000 { 1909 compatible = "st,stm32mp1-m4"; 1910 reg = <0x10000000 0x40000>, 1911 <0x30000000 0x40000>, 1912 <0x38000000 0x10000>; 1913 resets = <&rcc MCU_R>; 1914 reset-names = "mcu_rst"; 1915 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 1916 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1917 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1918 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1919 status = "disabled"; 1920 }; 1921 }; 1922}; 1923