1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 clock-frequency = <650000000>; 21 device_type = "cpu"; 22 reg = <0>; 23 }; 24 }; 25 26 arm-pmu { 27 compatible = "arm,cortex-a7-pmu"; 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-affinity = <&cpu0>; 30 interrupt-parent = <&intc>; 31 }; 32 33 psci { 34 compatible = "arm,psci-1.0"; 35 method = "smc"; 36 }; 37 38 intc: interrupt-controller@a0021000 { 39 compatible = "arm,cortex-a7-gic"; 40 #interrupt-cells = <3>; 41 interrupt-controller; 42 reg = <0xa0021000 0x1000>, 43 <0xa0022000 0x2000>; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&intc>; 53 }; 54 55 clocks { 56 clk_hse: clk-hse { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <24000000>; 60 }; 61 62 clk_hsi: clk-hsi { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <64000000>; 66 }; 67 68 clk_lse: clk-lse { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 clock-frequency = <32768>; 72 }; 73 74 clk_lsi: clk-lsi { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <32000>; 78 }; 79 80 clk_csi: clk-csi { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <4000000>; 84 }; 85 }; 86 87 thermal-zones { 88 cpu_thermal: cpu-thermal { 89 polling-delay-passive = <0>; 90 polling-delay = <0>; 91 thermal-sensors = <&dts>; 92 93 trips { 94 cpu_alert1: cpu-alert1 { 95 temperature = <85000>; 96 hysteresis = <0>; 97 type = "passive"; 98 }; 99 100 cpu-crit { 101 temperature = <120000>; 102 hysteresis = <0>; 103 type = "critical"; 104 }; 105 }; 106 107 cooling-maps { 108 }; 109 }; 110 }; 111 112 booster: regulator-booster { 113 compatible = "st,stm32mp1-booster"; 114 st,syscfg = <&syscfg>; 115 status = "disabled"; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 interrupt-parent = <&intc>; 123 ranges; 124 125 ipcc: mailbox@4c001000 { 126 compatible = "st,stm32mp1-ipcc"; 127 #mbox-cells = <1>; 128 reg = <0x4c001000 0x400>; 129 st,proc-id = <0>; 130 interrupts-extended = 131 <&exti 61 1>, 132 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 133 interrupt-names = "rx", "tx"; 134 clocks = <&rcc IPCC>; 135 wakeup-source; 136 status = "disabled"; 137 }; 138 139 rcc: rcc@50000000 { 140 compatible = "st,stm32mp1-rcc", "syscon"; 141 reg = <0x50000000 0x1000>; 142 #clock-cells = <1>; 143 #reset-cells = <1>; 144 }; 145 146 pwr_regulators: pwr@50001000 { 147 compatible = "st,stm32mp1,pwr-reg"; 148 reg = <0x50001000 0x10>; 149 150 reg11: reg11 { 151 regulator-name = "reg11"; 152 regulator-min-microvolt = <1100000>; 153 regulator-max-microvolt = <1100000>; 154 }; 155 156 reg18: reg18 { 157 regulator-name = "reg18"; 158 regulator-min-microvolt = <1800000>; 159 regulator-max-microvolt = <1800000>; 160 }; 161 162 usb33: usb33 { 163 regulator-name = "usb33"; 164 regulator-min-microvolt = <3300000>; 165 regulator-max-microvolt = <3300000>; 166 }; 167 }; 168 169 pwr_mcu: pwr_mcu@50001014 { 170 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 171 reg = <0x50001014 0x4>; 172 }; 173 174 exti: interrupt-controller@5000d000 { 175 compatible = "st,stm32mp1-exti", "syscon"; 176 interrupt-controller; 177 #interrupt-cells = <2>; 178 reg = <0x5000d000 0x400>; 179 interrupts-extended = 180 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 181 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 182 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 183 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 184 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 185 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 186 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 187 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 188 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 189 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 190 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 191 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 192 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 193 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 194 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 195 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 196 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 197 <0>, 198 <0>, 199 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 200 <0>, /* EXTI_20 */ 201 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 202 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 203 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 204 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 205 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 206 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 207 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 208 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 209 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 210 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 211 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 212 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 213 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 214 <0>, 215 <0>, 216 <0>, 217 <0>, 218 <0>, 219 <0>, 220 <0>, /* EXTI_40 */ 221 <0>, 222 <0>, 223 <0>, 224 <0>, 225 <0>, 226 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 227 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 228 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 229 <0>, 230 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 231 <0>, 232 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 233 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 234 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 235 <0>, 236 <0>, 237 <0>, 238 <0>, 239 <0>, 240 <0>, /* EXTI_60 */ 241 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 242 <0>, 243 <0>, 244 <0>, 245 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 246 <0>, 247 <0>, 248 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 249 <0>, 250 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 251 <0>, 252 <0>, 253 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 254 }; 255 256 syscfg: syscon@50020000 { 257 compatible = "st,stm32mp157-syscfg", "syscon"; 258 reg = <0x50020000 0x400>; 259 clocks = <&rcc SYSCFG>; 260 }; 261 262 dts: thermal@50028000 { 263 compatible = "st,stm32-thermal"; 264 reg = <0x50028000 0x100>; 265 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&rcc TMPSENS>; 267 clock-names = "pclk"; 268 #thermal-sensor-cells = <0>; 269 status = "disabled"; 270 }; 271 272 mdma1: dma-controller@58000000 { 273 compatible = "st,stm32h7-mdma"; 274 reg = <0x58000000 0x1000>; 275 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&rcc MDMA>; 277 resets = <&rcc MDMA_R>; 278 #dma-cells = <5>; 279 dma-channels = <32>; 280 dma-requests = <48>; 281 }; 282 283 sdmmc1: mmc@58005000 { 284 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 285 arm,primecell-periphid = <0x00253180>; 286 reg = <0x58005000 0x1000>; 287 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&rcc SDMMC1_K>; 289 clock-names = "apb_pclk"; 290 resets = <&rcc SDMMC1_R>; 291 cap-sd-highspeed; 292 cap-mmc-highspeed; 293 max-frequency = <120000000>; 294 status = "disabled"; 295 }; 296 297 sdmmc2: mmc@58007000 { 298 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 299 arm,primecell-periphid = <0x00253180>; 300 reg = <0x58007000 0x1000>; 301 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&rcc SDMMC2_K>; 303 clock-names = "apb_pclk"; 304 resets = <&rcc SDMMC2_R>; 305 cap-sd-highspeed; 306 cap-mmc-highspeed; 307 max-frequency = <120000000>; 308 status = "disabled"; 309 }; 310 311 crc1: crc@58009000 { 312 compatible = "st,stm32f7-crc"; 313 reg = <0x58009000 0x400>; 314 clocks = <&rcc CRC1>; 315 status = "disabled"; 316 }; 317 318 usbh_ohci: usb@5800c000 { 319 compatible = "generic-ohci"; 320 reg = <0x5800c000 0x1000>; 321 clocks = <&usbphyc>, <&rcc USBH>; 322 resets = <&rcc USBH_R>; 323 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 324 phys = <&usbphyc_port0>; 325 phy-names = "usb"; 326 status = "disabled"; 327 }; 328 329 usbh_ehci: usb@5800d000 { 330 compatible = "generic-ehci"; 331 reg = <0x5800d000 0x1000>; 332 clocks = <&usbphyc>, <&rcc USBH>; 333 resets = <&rcc USBH_R>; 334 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 335 companion = <&usbh_ohci>; 336 phys = <&usbphyc_port0>; 337 phy-names = "usb"; 338 status = "disabled"; 339 }; 340 341 ltdc: display-controller@5a001000 { 342 compatible = "st,stm32-ltdc"; 343 reg = <0x5a001000 0x400>; 344 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&rcc LTDC_PX>; 347 clock-names = "lcd"; 348 resets = <&rcc LTDC_R>; 349 status = "disabled"; 350 }; 351 352 iwdg2: watchdog@5a002000 { 353 compatible = "st,stm32mp1-iwdg"; 354 reg = <0x5a002000 0x400>; 355 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 356 clock-names = "pclk", "lsi"; 357 status = "disabled"; 358 }; 359 360 usbphyc: usbphyc@5a006000 { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 #clock-cells = <0>; 364 compatible = "st,stm32mp1-usbphyc"; 365 reg = <0x5a006000 0x1000>; 366 clocks = <&rcc USBPHY_K>; 367 resets = <&rcc USBPHY_R>; 368 vdda1v1-supply = <®11>; 369 vdda1v8-supply = <®18>; 370 status = "disabled"; 371 372 usbphyc_port0: usb-phy@0 { 373 #phy-cells = <0>; 374 reg = <0>; 375 }; 376 377 usbphyc_port1: usb-phy@1 { 378 #phy-cells = <1>; 379 reg = <1>; 380 }; 381 }; 382 383 rtc: rtc@5c004000 { 384 compatible = "st,stm32mp1-rtc"; 385 reg = <0x5c004000 0x400>; 386 clocks = <&rcc RTCAPB>, <&rcc RTC>; 387 clock-names = "pclk", "rtc_ck"; 388 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 389 status = "disabled"; 390 }; 391 392 bsec: efuse@5c005000 { 393 compatible = "st,stm32mp15-bsec"; 394 reg = <0x5c005000 0x400>; 395 #address-cells = <1>; 396 #size-cells = <1>; 397 part_number_otp: part-number-otp@4 { 398 reg = <0x4 0x1>; 399 }; 400 vrefint: vrefin-cal@52 { 401 reg = <0x52 0x2>; 402 }; 403 ts_cal1: calib@5c { 404 reg = <0x5c 0x2>; 405 }; 406 ts_cal2: calib@5e { 407 reg = <0x5e 0x2>; 408 }; 409 }; 410 411 etzpc: bus@5c007000 { 412 compatible = "st,stm32-etzpc", "simple-bus"; 413 reg = <0x5c007000 0x400>; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 #access-controller-cells = <1>; 417 ranges; 418 419 timers2: timer@40000000 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 compatible = "st,stm32-timers"; 423 reg = <0x40000000 0x400>; 424 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 425 interrupt-names = "global"; 426 clocks = <&rcc TIM2_K>; 427 clock-names = "int"; 428 dmas = <&dmamux1 18 0x400 0x1>, 429 <&dmamux1 19 0x400 0x1>, 430 <&dmamux1 20 0x400 0x1>, 431 <&dmamux1 21 0x400 0x1>, 432 <&dmamux1 22 0x400 0x1>; 433 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 434 access-controllers = <&etzpc 16>; 435 status = "disabled"; 436 437 pwm { 438 compatible = "st,stm32-pwm"; 439 #pwm-cells = <3>; 440 status = "disabled"; 441 }; 442 443 timer@1 { 444 compatible = "st,stm32h7-timer-trigger"; 445 reg = <1>; 446 status = "disabled"; 447 }; 448 449 counter { 450 compatible = "st,stm32-timer-counter"; 451 status = "disabled"; 452 }; 453 }; 454 455 timers3: timer@40001000 { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 compatible = "st,stm32-timers"; 459 reg = <0x40001000 0x400>; 460 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "global"; 462 clocks = <&rcc TIM3_K>; 463 clock-names = "int"; 464 dmas = <&dmamux1 23 0x400 0x1>, 465 <&dmamux1 24 0x400 0x1>, 466 <&dmamux1 25 0x400 0x1>, 467 <&dmamux1 26 0x400 0x1>, 468 <&dmamux1 27 0x400 0x1>, 469 <&dmamux1 28 0x400 0x1>; 470 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 471 access-controllers = <&etzpc 17>; 472 status = "disabled"; 473 474 pwm { 475 compatible = "st,stm32-pwm"; 476 #pwm-cells = <3>; 477 status = "disabled"; 478 }; 479 480 timer@2 { 481 compatible = "st,stm32h7-timer-trigger"; 482 reg = <2>; 483 status = "disabled"; 484 }; 485 486 counter { 487 compatible = "st,stm32-timer-counter"; 488 status = "disabled"; 489 }; 490 }; 491 492 timers4: timer@40002000 { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 compatible = "st,stm32-timers"; 496 reg = <0x40002000 0x400>; 497 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 498 interrupt-names = "global"; 499 clocks = <&rcc TIM4_K>; 500 clock-names = "int"; 501 dmas = <&dmamux1 29 0x400 0x1>, 502 <&dmamux1 30 0x400 0x1>, 503 <&dmamux1 31 0x400 0x1>, 504 <&dmamux1 32 0x400 0x1>; 505 dma-names = "ch1", "ch2", "ch3", "ch4"; 506 access-controllers = <&etzpc 18>; 507 status = "disabled"; 508 509 pwm { 510 compatible = "st,stm32-pwm"; 511 #pwm-cells = <3>; 512 status = "disabled"; 513 }; 514 515 timer@3 { 516 compatible = "st,stm32h7-timer-trigger"; 517 reg = <3>; 518 status = "disabled"; 519 }; 520 521 counter { 522 compatible = "st,stm32-timer-counter"; 523 status = "disabled"; 524 }; 525 }; 526 527 timers5: timer@40003000 { 528 #address-cells = <1>; 529 #size-cells = <0>; 530 compatible = "st,stm32-timers"; 531 reg = <0x40003000 0x400>; 532 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 533 interrupt-names = "global"; 534 clocks = <&rcc TIM5_K>; 535 clock-names = "int"; 536 dmas = <&dmamux1 55 0x400 0x1>, 537 <&dmamux1 56 0x400 0x1>, 538 <&dmamux1 57 0x400 0x1>, 539 <&dmamux1 58 0x400 0x1>, 540 <&dmamux1 59 0x400 0x1>, 541 <&dmamux1 60 0x400 0x1>; 542 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 543 access-controllers = <&etzpc 19>; 544 status = "disabled"; 545 546 pwm { 547 compatible = "st,stm32-pwm"; 548 #pwm-cells = <3>; 549 status = "disabled"; 550 }; 551 552 timer@4 { 553 compatible = "st,stm32h7-timer-trigger"; 554 reg = <4>; 555 status = "disabled"; 556 }; 557 558 counter { 559 compatible = "st,stm32-timer-counter"; 560 status = "disabled"; 561 }; 562 }; 563 564 timers6: timer@40004000 { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 compatible = "st,stm32-timers"; 568 reg = <0x40004000 0x400>; 569 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 570 interrupt-names = "global"; 571 clocks = <&rcc TIM6_K>; 572 clock-names = "int"; 573 dmas = <&dmamux1 69 0x400 0x1>; 574 dma-names = "up"; 575 access-controllers = <&etzpc 20>; 576 status = "disabled"; 577 578 timer@5 { 579 compatible = "st,stm32h7-timer-trigger"; 580 reg = <5>; 581 status = "disabled"; 582 }; 583 }; 584 585 timers7: timer@40005000 { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 compatible = "st,stm32-timers"; 589 reg = <0x40005000 0x400>; 590 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "global"; 592 clocks = <&rcc TIM7_K>; 593 clock-names = "int"; 594 dmas = <&dmamux1 70 0x400 0x1>; 595 dma-names = "up"; 596 access-controllers = <&etzpc 21>; 597 status = "disabled"; 598 599 timer@6 { 600 compatible = "st,stm32h7-timer-trigger"; 601 reg = <6>; 602 status = "disabled"; 603 }; 604 }; 605 606 timers12: timer@40006000 { 607 #address-cells = <1>; 608 #size-cells = <0>; 609 compatible = "st,stm32-timers"; 610 reg = <0x40006000 0x400>; 611 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 612 interrupt-names = "global"; 613 clocks = <&rcc TIM12_K>; 614 clock-names = "int"; 615 access-controllers = <&etzpc 22>; 616 status = "disabled"; 617 618 pwm { 619 compatible = "st,stm32-pwm"; 620 #pwm-cells = <3>; 621 status = "disabled"; 622 }; 623 624 timer@11 { 625 compatible = "st,stm32h7-timer-trigger"; 626 reg = <11>; 627 status = "disabled"; 628 }; 629 }; 630 631 timers13: timer@40007000 { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 compatible = "st,stm32-timers"; 635 reg = <0x40007000 0x400>; 636 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 637 interrupt-names = "global"; 638 clocks = <&rcc TIM13_K>; 639 clock-names = "int"; 640 access-controllers = <&etzpc 23>; 641 status = "disabled"; 642 643 pwm { 644 compatible = "st,stm32-pwm"; 645 #pwm-cells = <3>; 646 status = "disabled"; 647 }; 648 649 timer@12 { 650 compatible = "st,stm32h7-timer-trigger"; 651 reg = <12>; 652 status = "disabled"; 653 }; 654 }; 655 656 timers14: timer@40008000 { 657 #address-cells = <1>; 658 #size-cells = <0>; 659 compatible = "st,stm32-timers"; 660 reg = <0x40008000 0x400>; 661 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 662 interrupt-names = "global"; 663 clocks = <&rcc TIM14_K>; 664 clock-names = "int"; 665 access-controllers = <&etzpc 24>; 666 status = "disabled"; 667 668 pwm { 669 compatible = "st,stm32-pwm"; 670 #pwm-cells = <3>; 671 status = "disabled"; 672 }; 673 674 timer@13 { 675 compatible = "st,stm32h7-timer-trigger"; 676 reg = <13>; 677 status = "disabled"; 678 }; 679 }; 680 681 lptimer1: timer@40009000 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 compatible = "st,stm32-lptimer"; 685 reg = <0x40009000 0x400>; 686 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&rcc LPTIM1_K>; 688 clock-names = "mux"; 689 wakeup-source; 690 access-controllers = <&etzpc 25>; 691 status = "disabled"; 692 693 pwm { 694 compatible = "st,stm32-pwm-lp"; 695 #pwm-cells = <3>; 696 status = "disabled"; 697 }; 698 699 trigger@0 { 700 compatible = "st,stm32-lptimer-trigger"; 701 reg = <0>; 702 status = "disabled"; 703 }; 704 705 counter { 706 compatible = "st,stm32-lptimer-counter"; 707 status = "disabled"; 708 }; 709 }; 710 711 i2s2: audio-controller@4000b000 { 712 compatible = "st,stm32h7-i2s"; 713 #sound-dai-cells = <0>; 714 reg = <0x4000b000 0x400>; 715 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 716 dmas = <&dmamux1 39 0x400 0x01>, 717 <&dmamux1 40 0x400 0x01>; 718 dma-names = "rx", "tx"; 719 access-controllers = <&etzpc 27>; 720 status = "disabled"; 721 }; 722 723 spi2: spi@4000b000 { 724 #address-cells = <1>; 725 #size-cells = <0>; 726 compatible = "st,stm32h7-spi"; 727 reg = <0x4000b000 0x400>; 728 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&rcc SPI2_K>; 730 resets = <&rcc SPI2_R>; 731 dmas = <&dmamux1 39 0x400 0x05>, 732 <&dmamux1 40 0x400 0x05>; 733 dma-names = "rx", "tx"; 734 access-controllers = <&etzpc 27>; 735 status = "disabled"; 736 }; 737 738 i2s3: audio-controller@4000c000 { 739 compatible = "st,stm32h7-i2s"; 740 #sound-dai-cells = <0>; 741 reg = <0x4000c000 0x400>; 742 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 743 dmas = <&dmamux1 61 0x400 0x01>, 744 <&dmamux1 62 0x400 0x01>; 745 dma-names = "rx", "tx"; 746 access-controllers = <&etzpc 28>; 747 status = "disabled"; 748 }; 749 750 spi3: spi@4000c000 { 751 #address-cells = <1>; 752 #size-cells = <0>; 753 compatible = "st,stm32h7-spi"; 754 reg = <0x4000c000 0x400>; 755 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&rcc SPI3_K>; 757 resets = <&rcc SPI3_R>; 758 dmas = <&dmamux1 61 0x400 0x05>, 759 <&dmamux1 62 0x400 0x05>; 760 dma-names = "rx", "tx"; 761 access-controllers = <&etzpc 28>; 762 status = "disabled"; 763 }; 764 765 spdifrx: audio-controller@4000d000 { 766 compatible = "st,stm32h7-spdifrx"; 767 #sound-dai-cells = <0>; 768 reg = <0x4000d000 0x400>; 769 clocks = <&rcc SPDIF_K>; 770 clock-names = "kclk"; 771 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 772 dmas = <&dmamux1 93 0x400 0x01>, 773 <&dmamux1 94 0x400 0x01>; 774 dma-names = "rx", "rx-ctrl"; 775 access-controllers = <&etzpc 29>; 776 status = "disabled"; 777 }; 778 779 usart2: serial@4000e000 { 780 compatible = "st,stm32h7-uart"; 781 reg = <0x4000e000 0x400>; 782 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&rcc USART2_K>; 784 wakeup-source; 785 dmas = <&dmamux1 43 0x400 0x15>, 786 <&dmamux1 44 0x400 0x11>; 787 dma-names = "rx", "tx"; 788 access-controllers = <&etzpc 30>; 789 status = "disabled"; 790 }; 791 792 usart3: serial@4000f000 { 793 compatible = "st,stm32h7-uart"; 794 reg = <0x4000f000 0x400>; 795 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&rcc USART3_K>; 797 wakeup-source; 798 dmas = <&dmamux1 45 0x400 0x15>, 799 <&dmamux1 46 0x400 0x11>; 800 dma-names = "rx", "tx"; 801 access-controllers = <&etzpc 31>; 802 status = "disabled"; 803 }; 804 805 uart4: serial@40010000 { 806 compatible = "st,stm32h7-uart"; 807 reg = <0x40010000 0x400>; 808 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&rcc UART4_K>; 810 wakeup-source; 811 dmas = <&dmamux1 63 0x400 0x15>, 812 <&dmamux1 64 0x400 0x11>; 813 dma-names = "rx", "tx"; 814 access-controllers = <&etzpc 32>; 815 status = "disabled"; 816 }; 817 818 uart5: serial@40011000 { 819 compatible = "st,stm32h7-uart"; 820 reg = <0x40011000 0x400>; 821 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&rcc UART5_K>; 823 wakeup-source; 824 dmas = <&dmamux1 65 0x400 0x15>, 825 <&dmamux1 66 0x400 0x11>; 826 dma-names = "rx", "tx"; 827 access-controllers = <&etzpc 33>; 828 status = "disabled"; 829 }; 830 831 i2c1: i2c@40012000 { 832 compatible = "st,stm32mp15-i2c"; 833 reg = <0x40012000 0x400>; 834 interrupt-names = "event", "error"; 835 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&rcc I2C1_K>; 838 resets = <&rcc I2C1_R>; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 st,syscfg-fmp = <&syscfg 0x4 0x1>; 842 wakeup-source; 843 i2c-analog-filter; 844 access-controllers = <&etzpc 34>; 845 status = "disabled"; 846 }; 847 848 i2c2: i2c@40013000 { 849 compatible = "st,stm32mp15-i2c"; 850 reg = <0x40013000 0x400>; 851 interrupt-names = "event", "error"; 852 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&rcc I2C2_K>; 855 resets = <&rcc I2C2_R>; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 st,syscfg-fmp = <&syscfg 0x4 0x2>; 859 wakeup-source; 860 i2c-analog-filter; 861 access-controllers = <&etzpc 35>; 862 status = "disabled"; 863 }; 864 865 i2c3: i2c@40014000 { 866 compatible = "st,stm32mp15-i2c"; 867 reg = <0x40014000 0x400>; 868 interrupt-names = "event", "error"; 869 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&rcc I2C3_K>; 872 resets = <&rcc I2C3_R>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 st,syscfg-fmp = <&syscfg 0x4 0x4>; 876 wakeup-source; 877 i2c-analog-filter; 878 access-controllers = <&etzpc 36>; 879 status = "disabled"; 880 }; 881 882 i2c5: i2c@40015000 { 883 compatible = "st,stm32mp15-i2c"; 884 reg = <0x40015000 0x400>; 885 interrupt-names = "event", "error"; 886 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&rcc I2C5_K>; 889 resets = <&rcc I2C5_R>; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 st,syscfg-fmp = <&syscfg 0x4 0x10>; 893 wakeup-source; 894 i2c-analog-filter; 895 access-controllers = <&etzpc 37>; 896 status = "disabled"; 897 }; 898 899 cec: cec@40016000 { 900 compatible = "st,stm32-cec"; 901 reg = <0x40016000 0x400>; 902 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&rcc CEC_K>, <&rcc CEC>; 904 clock-names = "cec", "hdmi-cec"; 905 access-controllers = <&etzpc 38>; 906 status = "disabled"; 907 }; 908 909 dac: dac@40017000 { 910 compatible = "st,stm32h7-dac-core"; 911 reg = <0x40017000 0x400>; 912 clocks = <&rcc DAC12>; 913 clock-names = "pclk"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 access-controllers = <&etzpc 39>; 917 status = "disabled"; 918 919 dac1: dac@1 { 920 compatible = "st,stm32-dac"; 921 #io-channel-cells = <1>; 922 reg = <1>; 923 status = "disabled"; 924 }; 925 926 dac2: dac@2 { 927 compatible = "st,stm32-dac"; 928 #io-channel-cells = <1>; 929 reg = <2>; 930 status = "disabled"; 931 }; 932 }; 933 934 uart7: serial@40018000 { 935 compatible = "st,stm32h7-uart"; 936 reg = <0x40018000 0x400>; 937 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&rcc UART7_K>; 939 wakeup-source; 940 dmas = <&dmamux1 79 0x400 0x15>, 941 <&dmamux1 80 0x400 0x11>; 942 dma-names = "rx", "tx"; 943 access-controllers = <&etzpc 40>; 944 status = "disabled"; 945 }; 946 947 uart8: serial@40019000 { 948 compatible = "st,stm32h7-uart"; 949 reg = <0x40019000 0x400>; 950 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&rcc UART8_K>; 952 wakeup-source; 953 dmas = <&dmamux1 81 0x400 0x15>, 954 <&dmamux1 82 0x400 0x11>; 955 dma-names = "rx", "tx"; 956 access-controllers = <&etzpc 41>; 957 status = "disabled"; 958 }; 959 960 timers1: timer@44000000 { 961 #address-cells = <1>; 962 #size-cells = <0>; 963 compatible = "st,stm32-timers"; 964 reg = <0x44000000 0x400>; 965 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 969 interrupt-names = "brk", "up", "trg-com", "cc"; 970 clocks = <&rcc TIM1_K>; 971 clock-names = "int"; 972 dmas = <&dmamux1 11 0x400 0x1>, 973 <&dmamux1 12 0x400 0x1>, 974 <&dmamux1 13 0x400 0x1>, 975 <&dmamux1 14 0x400 0x1>, 976 <&dmamux1 15 0x400 0x1>, 977 <&dmamux1 16 0x400 0x1>, 978 <&dmamux1 17 0x400 0x1>; 979 dma-names = "ch1", "ch2", "ch3", "ch4", 980 "up", "trig", "com"; 981 access-controllers = <&etzpc 48>; 982 status = "disabled"; 983 984 pwm { 985 compatible = "st,stm32-pwm"; 986 #pwm-cells = <3>; 987 status = "disabled"; 988 }; 989 990 timer@0 { 991 compatible = "st,stm32h7-timer-trigger"; 992 reg = <0>; 993 status = "disabled"; 994 }; 995 996 counter { 997 compatible = "st,stm32-timer-counter"; 998 status = "disabled"; 999 }; 1000 }; 1001 1002 timers8: timer@44001000 { 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 compatible = "st,stm32-timers"; 1006 reg = <0x44001000 0x400>; 1007 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1011 interrupt-names = "brk", "up", "trg-com", "cc"; 1012 clocks = <&rcc TIM8_K>; 1013 clock-names = "int"; 1014 dmas = <&dmamux1 47 0x400 0x1>, 1015 <&dmamux1 48 0x400 0x1>, 1016 <&dmamux1 49 0x400 0x1>, 1017 <&dmamux1 50 0x400 0x1>, 1018 <&dmamux1 51 0x400 0x1>, 1019 <&dmamux1 52 0x400 0x1>, 1020 <&dmamux1 53 0x400 0x1>; 1021 dma-names = "ch1", "ch2", "ch3", "ch4", 1022 "up", "trig", "com"; 1023 access-controllers = <&etzpc 49>; 1024 status = "disabled"; 1025 1026 pwm { 1027 compatible = "st,stm32-pwm"; 1028 #pwm-cells = <3>; 1029 status = "disabled"; 1030 }; 1031 1032 timer@7 { 1033 compatible = "st,stm32h7-timer-trigger"; 1034 reg = <7>; 1035 status = "disabled"; 1036 }; 1037 1038 counter { 1039 compatible = "st,stm32-timer-counter"; 1040 status = "disabled"; 1041 }; 1042 }; 1043 1044 usart6: serial@44003000 { 1045 compatible = "st,stm32h7-uart"; 1046 reg = <0x44003000 0x400>; 1047 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&rcc USART6_K>; 1049 wakeup-source; 1050 dmas = <&dmamux1 71 0x400 0x15>, 1051 <&dmamux1 72 0x400 0x11>; 1052 dma-names = "rx", "tx"; 1053 access-controllers = <&etzpc 51>; 1054 status = "disabled"; 1055 }; 1056 1057 i2s1: audio-controller@44004000 { 1058 compatible = "st,stm32h7-i2s"; 1059 #sound-dai-cells = <0>; 1060 reg = <0x44004000 0x400>; 1061 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1062 dmas = <&dmamux1 37 0x400 0x01>, 1063 <&dmamux1 38 0x400 0x01>; 1064 dma-names = "rx", "tx"; 1065 access-controllers = <&etzpc 52>; 1066 status = "disabled"; 1067 }; 1068 1069 spi1: spi@44004000 { 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 compatible = "st,stm32h7-spi"; 1073 reg = <0x44004000 0x400>; 1074 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&rcc SPI1_K>; 1076 resets = <&rcc SPI1_R>; 1077 dmas = <&dmamux1 37 0x400 0x05>, 1078 <&dmamux1 38 0x400 0x05>; 1079 dma-names = "rx", "tx"; 1080 access-controllers = <&etzpc 52>; 1081 status = "disabled"; 1082 }; 1083 1084 spi4: spi@44005000 { 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 compatible = "st,stm32h7-spi"; 1088 reg = <0x44005000 0x400>; 1089 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&rcc SPI4_K>; 1091 resets = <&rcc SPI4_R>; 1092 dmas = <&dmamux1 83 0x400 0x05>, 1093 <&dmamux1 84 0x400 0x05>; 1094 dma-names = "rx", "tx"; 1095 access-controllers = <&etzpc 53>; 1096 status = "disabled"; 1097 }; 1098 1099 timers15: timer@44006000 { 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 compatible = "st,stm32-timers"; 1103 reg = <0x44006000 0x400>; 1104 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1105 interrupt-names = "global"; 1106 clocks = <&rcc TIM15_K>; 1107 clock-names = "int"; 1108 dmas = <&dmamux1 105 0x400 0x1>, 1109 <&dmamux1 106 0x400 0x1>, 1110 <&dmamux1 107 0x400 0x1>, 1111 <&dmamux1 108 0x400 0x1>; 1112 dma-names = "ch1", "up", "trig", "com"; 1113 access-controllers = <&etzpc 54>; 1114 status = "disabled"; 1115 1116 pwm { 1117 compatible = "st,stm32-pwm"; 1118 #pwm-cells = <3>; 1119 status = "disabled"; 1120 }; 1121 1122 timer@14 { 1123 compatible = "st,stm32h7-timer-trigger"; 1124 reg = <14>; 1125 status = "disabled"; 1126 }; 1127 }; 1128 1129 timers16: timer@44007000 { 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 compatible = "st,stm32-timers"; 1133 reg = <0x44007000 0x400>; 1134 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1135 interrupt-names = "global"; 1136 clocks = <&rcc TIM16_K>; 1137 clock-names = "int"; 1138 dmas = <&dmamux1 109 0x400 0x1>, 1139 <&dmamux1 110 0x400 0x1>; 1140 dma-names = "ch1", "up"; 1141 access-controllers = <&etzpc 55>; 1142 status = "disabled"; 1143 1144 pwm { 1145 compatible = "st,stm32-pwm"; 1146 #pwm-cells = <3>; 1147 status = "disabled"; 1148 }; 1149 timer@15 { 1150 compatible = "st,stm32h7-timer-trigger"; 1151 reg = <15>; 1152 status = "disabled"; 1153 }; 1154 }; 1155 1156 timers17: timer@44008000 { 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 compatible = "st,stm32-timers"; 1160 reg = <0x44008000 0x400>; 1161 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1162 interrupt-names = "global"; 1163 clocks = <&rcc TIM17_K>; 1164 clock-names = "int"; 1165 dmas = <&dmamux1 111 0x400 0x1>, 1166 <&dmamux1 112 0x400 0x1>; 1167 dma-names = "ch1", "up"; 1168 access-controllers = <&etzpc 56>; 1169 status = "disabled"; 1170 1171 pwm { 1172 compatible = "st,stm32-pwm"; 1173 #pwm-cells = <3>; 1174 status = "disabled"; 1175 }; 1176 1177 timer@16 { 1178 compatible = "st,stm32h7-timer-trigger"; 1179 reg = <16>; 1180 status = "disabled"; 1181 }; 1182 }; 1183 1184 spi5: spi@44009000 { 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 compatible = "st,stm32h7-spi"; 1188 reg = <0x44009000 0x400>; 1189 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&rcc SPI5_K>; 1191 resets = <&rcc SPI5_R>; 1192 dmas = <&dmamux1 85 0x400 0x05>, 1193 <&dmamux1 86 0x400 0x05>; 1194 dma-names = "rx", "tx"; 1195 access-controllers = <&etzpc 57>; 1196 status = "disabled"; 1197 }; 1198 1199 sai1: sai@4400a000 { 1200 compatible = "st,stm32h7-sai"; 1201 #address-cells = <1>; 1202 #size-cells = <1>; 1203 ranges = <0 0x4400a000 0x400>; 1204 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1205 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1206 resets = <&rcc SAI1_R>; 1207 access-controllers = <&etzpc 58>; 1208 status = "disabled"; 1209 1210 sai1a: audio-controller@4400a004 { 1211 #sound-dai-cells = <0>; 1212 1213 compatible = "st,stm32-sai-sub-a"; 1214 reg = <0x4 0x20>; 1215 clocks = <&rcc SAI1_K>; 1216 clock-names = "sai_ck"; 1217 dmas = <&dmamux1 87 0x400 0x01>; 1218 status = "disabled"; 1219 }; 1220 1221 sai1b: audio-controller@4400a024 { 1222 #sound-dai-cells = <0>; 1223 compatible = "st,stm32-sai-sub-b"; 1224 reg = <0x24 0x20>; 1225 clocks = <&rcc SAI1_K>; 1226 clock-names = "sai_ck"; 1227 dmas = <&dmamux1 88 0x400 0x01>; 1228 status = "disabled"; 1229 }; 1230 }; 1231 1232 sai2: sai@4400b000 { 1233 compatible = "st,stm32h7-sai"; 1234 #address-cells = <1>; 1235 #size-cells = <1>; 1236 ranges = <0 0x4400b000 0x400>; 1237 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1238 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1239 resets = <&rcc SAI2_R>; 1240 access-controllers = <&etzpc 59>; 1241 status = "disabled"; 1242 1243 sai2a: audio-controller@4400b004 { 1244 #sound-dai-cells = <0>; 1245 compatible = "st,stm32-sai-sub-a"; 1246 reg = <0x4 0x20>; 1247 clocks = <&rcc SAI2_K>; 1248 clock-names = "sai_ck"; 1249 dmas = <&dmamux1 89 0x400 0x01>; 1250 status = "disabled"; 1251 }; 1252 1253 sai2b: audio-controller@4400b024 { 1254 #sound-dai-cells = <0>; 1255 compatible = "st,stm32-sai-sub-b"; 1256 reg = <0x24 0x20>; 1257 clocks = <&rcc SAI2_K>; 1258 clock-names = "sai_ck"; 1259 dmas = <&dmamux1 90 0x400 0x01>; 1260 status = "disabled"; 1261 }; 1262 }; 1263 1264 sai3: sai@4400c000 { 1265 compatible = "st,stm32h7-sai"; 1266 #address-cells = <1>; 1267 #size-cells = <1>; 1268 ranges = <0 0x4400c000 0x400>; 1269 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1270 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1271 resets = <&rcc SAI3_R>; 1272 access-controllers = <&etzpc 60>; 1273 status = "disabled"; 1274 1275 sai3a: audio-controller@4400c004 { 1276 #sound-dai-cells = <0>; 1277 compatible = "st,stm32-sai-sub-a"; 1278 reg = <0x04 0x20>; 1279 clocks = <&rcc SAI3_K>; 1280 clock-names = "sai_ck"; 1281 dmas = <&dmamux1 113 0x400 0x01>; 1282 status = "disabled"; 1283 }; 1284 1285 sai3b: audio-controller@4400c024 { 1286 #sound-dai-cells = <0>; 1287 compatible = "st,stm32-sai-sub-b"; 1288 reg = <0x24 0x20>; 1289 clocks = <&rcc SAI3_K>; 1290 clock-names = "sai_ck"; 1291 dmas = <&dmamux1 114 0x400 0x01>; 1292 status = "disabled"; 1293 }; 1294 }; 1295 1296 dfsdm: dfsdm@4400d000 { 1297 compatible = "st,stm32mp1-dfsdm"; 1298 reg = <0x4400d000 0x800>; 1299 clocks = <&rcc DFSDM_K>; 1300 clock-names = "dfsdm"; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 access-controllers = <&etzpc 61>; 1304 status = "disabled"; 1305 1306 dfsdm0: filter@0 { 1307 compatible = "st,stm32-dfsdm-adc"; 1308 #io-channel-cells = <1>; 1309 reg = <0>; 1310 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&dmamux1 101 0x400 0x01>; 1312 dma-names = "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 dfsdm1: filter@1 { 1317 compatible = "st,stm32-dfsdm-adc"; 1318 #io-channel-cells = <1>; 1319 reg = <1>; 1320 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1321 dmas = <&dmamux1 102 0x400 0x01>; 1322 dma-names = "rx"; 1323 status = "disabled"; 1324 }; 1325 1326 dfsdm2: filter@2 { 1327 compatible = "st,stm32-dfsdm-adc"; 1328 #io-channel-cells = <1>; 1329 reg = <2>; 1330 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1331 dmas = <&dmamux1 103 0x400 0x01>; 1332 dma-names = "rx"; 1333 status = "disabled"; 1334 }; 1335 1336 dfsdm3: filter@3 { 1337 compatible = "st,stm32-dfsdm-adc"; 1338 #io-channel-cells = <1>; 1339 reg = <3>; 1340 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1341 dmas = <&dmamux1 104 0x400 0x01>; 1342 dma-names = "rx"; 1343 status = "disabled"; 1344 }; 1345 1346 dfsdm4: filter@4 { 1347 compatible = "st,stm32-dfsdm-adc"; 1348 #io-channel-cells = <1>; 1349 reg = <4>; 1350 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1351 dmas = <&dmamux1 91 0x400 0x01>; 1352 dma-names = "rx"; 1353 status = "disabled"; 1354 }; 1355 1356 dfsdm5: filter@5 { 1357 compatible = "st,stm32-dfsdm-adc"; 1358 #io-channel-cells = <1>; 1359 reg = <5>; 1360 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1361 dmas = <&dmamux1 92 0x400 0x01>; 1362 dma-names = "rx"; 1363 status = "disabled"; 1364 }; 1365 }; 1366 1367 dma1: dma-controller@48000000 { 1368 compatible = "st,stm32-dma"; 1369 reg = <0x48000000 0x400>; 1370 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&rcc DMA1>; 1379 resets = <&rcc DMA1_R>; 1380 #dma-cells = <4>; 1381 st,mem2mem; 1382 dma-requests = <8>; 1383 access-controllers = <&etzpc 88>; 1384 }; 1385 1386 dma2: dma-controller@48001000 { 1387 compatible = "st,stm32-dma"; 1388 reg = <0x48001000 0x400>; 1389 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1397 clocks = <&rcc DMA2>; 1398 resets = <&rcc DMA2_R>; 1399 #dma-cells = <4>; 1400 st,mem2mem; 1401 dma-requests = <8>; 1402 access-controllers = <&etzpc 89>; 1403 }; 1404 1405 dmamux1: dma-router@48002000 { 1406 compatible = "st,stm32h7-dmamux"; 1407 reg = <0x48002000 0x40>; 1408 #dma-cells = <3>; 1409 dma-requests = <128>; 1410 dma-masters = <&dma1 &dma2>; 1411 dma-channels = <16>; 1412 clocks = <&rcc DMAMUX>; 1413 resets = <&rcc DMAMUX_R>; 1414 access-controllers = <&etzpc 90>; 1415 }; 1416 1417 adc: adc@48003000 { 1418 compatible = "st,stm32mp1-adc-core"; 1419 reg = <0x48003000 0x400>; 1420 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1422 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1423 clock-names = "bus", "adc"; 1424 interrupt-controller; 1425 st,syscfg = <&syscfg>; 1426 #interrupt-cells = <1>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 access-controllers = <&etzpc 72>; 1430 status = "disabled"; 1431 1432 adc1: adc@0 { 1433 compatible = "st,stm32mp1-adc"; 1434 #io-channel-cells = <1>; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 reg = <0x0>; 1438 interrupt-parent = <&adc>; 1439 interrupts = <0>; 1440 dmas = <&dmamux1 9 0x400 0x01>; 1441 dma-names = "rx"; 1442 status = "disabled"; 1443 }; 1444 1445 adc2: adc@100 { 1446 compatible = "st,stm32mp1-adc"; 1447 #io-channel-cells = <1>; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 reg = <0x100>; 1451 interrupt-parent = <&adc>; 1452 interrupts = <1>; 1453 dmas = <&dmamux1 10 0x400 0x01>; 1454 dma-names = "rx"; 1455 nvmem-cells = <&vrefint>; 1456 nvmem-cell-names = "vrefint"; 1457 status = "disabled"; 1458 channel@13 { 1459 reg = <13>; 1460 label = "vrefint"; 1461 }; 1462 channel@14 { 1463 reg = <14>; 1464 label = "vddcore"; 1465 }; 1466 }; 1467 }; 1468 1469 sdmmc3: mmc@48004000 { 1470 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1471 arm,primecell-periphid = <0x00253180>; 1472 reg = <0x48004000 0x400>; 1473 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1474 clocks = <&rcc SDMMC3_K>; 1475 clock-names = "apb_pclk"; 1476 resets = <&rcc SDMMC3_R>; 1477 cap-sd-highspeed; 1478 cap-mmc-highspeed; 1479 max-frequency = <120000000>; 1480 access-controllers = <&etzpc 86>; 1481 status = "disabled"; 1482 }; 1483 1484 usbotg_hs: usb-otg@49000000 { 1485 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1486 reg = <0x49000000 0x10000>; 1487 clocks = <&rcc USBO_K>, <&usbphyc>; 1488 clock-names = "otg", "utmi"; 1489 resets = <&rcc USBO_R>; 1490 reset-names = "dwc2"; 1491 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1492 g-rx-fifo-size = <512>; 1493 g-np-tx-fifo-size = <32>; 1494 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1495 dr_mode = "otg"; 1496 otg-rev = <0x200>; 1497 usb33d-supply = <&usb33>; 1498 access-controllers = <&etzpc 85>; 1499 status = "disabled"; 1500 }; 1501 1502 dcmi: dcmi@4c006000 { 1503 compatible = "st,stm32-dcmi"; 1504 reg = <0x4c006000 0x400>; 1505 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1506 resets = <&rcc CAMITF_R>; 1507 clocks = <&rcc DCMI>; 1508 clock-names = "mclk"; 1509 dmas = <&dmamux1 75 0x400 0x01>; 1510 dma-names = "tx"; 1511 access-controllers = <&etzpc 70>; 1512 status = "disabled"; 1513 }; 1514 1515 lptimer2: timer@50021000 { 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 compatible = "st,stm32-lptimer"; 1519 reg = <0x50021000 0x400>; 1520 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1521 clocks = <&rcc LPTIM2_K>; 1522 clock-names = "mux"; 1523 wakeup-source; 1524 access-controllers = <&etzpc 64>; 1525 status = "disabled"; 1526 1527 pwm { 1528 compatible = "st,stm32-pwm-lp"; 1529 #pwm-cells = <3>; 1530 status = "disabled"; 1531 }; 1532 1533 trigger@1 { 1534 compatible = "st,stm32-lptimer-trigger"; 1535 reg = <1>; 1536 status = "disabled"; 1537 }; 1538 1539 counter { 1540 compatible = "st,stm32-lptimer-counter"; 1541 status = "disabled"; 1542 }; 1543 }; 1544 1545 lptimer3: timer@50022000 { 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 compatible = "st,stm32-lptimer"; 1549 reg = <0x50022000 0x400>; 1550 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1551 clocks = <&rcc LPTIM3_K>; 1552 clock-names = "mux"; 1553 wakeup-source; 1554 access-controllers = <&etzpc 65>; 1555 status = "disabled"; 1556 1557 pwm { 1558 compatible = "st,stm32-pwm-lp"; 1559 #pwm-cells = <3>; 1560 status = "disabled"; 1561 }; 1562 1563 trigger@2 { 1564 compatible = "st,stm32-lptimer-trigger"; 1565 reg = <2>; 1566 status = "disabled"; 1567 }; 1568 }; 1569 1570 lptimer4: timer@50023000 { 1571 compatible = "st,stm32-lptimer"; 1572 reg = <0x50023000 0x400>; 1573 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1574 clocks = <&rcc LPTIM4_K>; 1575 clock-names = "mux"; 1576 wakeup-source; 1577 access-controllers = <&etzpc 66>; 1578 status = "disabled"; 1579 1580 pwm { 1581 compatible = "st,stm32-pwm-lp"; 1582 #pwm-cells = <3>; 1583 status = "disabled"; 1584 }; 1585 }; 1586 1587 lptimer5: timer@50024000 { 1588 compatible = "st,stm32-lptimer"; 1589 reg = <0x50024000 0x400>; 1590 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1591 clocks = <&rcc LPTIM5_K>; 1592 clock-names = "mux"; 1593 wakeup-source; 1594 access-controllers = <&etzpc 67>; 1595 status = "disabled"; 1596 1597 pwm { 1598 compatible = "st,stm32-pwm-lp"; 1599 #pwm-cells = <3>; 1600 status = "disabled"; 1601 }; 1602 }; 1603 1604 vrefbuf: vrefbuf@50025000 { 1605 compatible = "st,stm32-vrefbuf"; 1606 reg = <0x50025000 0x8>; 1607 regulator-min-microvolt = <1500000>; 1608 regulator-max-microvolt = <2500000>; 1609 clocks = <&rcc VREF>; 1610 access-controllers = <&etzpc 69>; 1611 status = "disabled"; 1612 }; 1613 1614 sai4: sai@50027000 { 1615 compatible = "st,stm32h7-sai"; 1616 #address-cells = <1>; 1617 #size-cells = <1>; 1618 ranges = <0 0x50027000 0x400>; 1619 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1620 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1621 resets = <&rcc SAI4_R>; 1622 access-controllers = <&etzpc 68>; 1623 status = "disabled"; 1624 1625 sai4a: audio-controller@50027004 { 1626 #sound-dai-cells = <0>; 1627 compatible = "st,stm32-sai-sub-a"; 1628 reg = <0x04 0x20>; 1629 clocks = <&rcc SAI4_K>; 1630 clock-names = "sai_ck"; 1631 dmas = <&dmamux1 99 0x400 0x01>; 1632 status = "disabled"; 1633 }; 1634 1635 sai4b: audio-controller@50027024 { 1636 #sound-dai-cells = <0>; 1637 compatible = "st,stm32-sai-sub-b"; 1638 reg = <0x24 0x20>; 1639 clocks = <&rcc SAI4_K>; 1640 clock-names = "sai_ck"; 1641 dmas = <&dmamux1 100 0x400 0x01>; 1642 status = "disabled"; 1643 }; 1644 }; 1645 1646 hash1: hash@54002000 { 1647 compatible = "st,stm32f756-hash"; 1648 reg = <0x54002000 0x400>; 1649 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&rcc HASH1>; 1651 resets = <&rcc HASH1_R>; 1652 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1653 dma-names = "in"; 1654 dma-maxburst = <2>; 1655 access-controllers = <&etzpc 8>; 1656 status = "disabled"; 1657 }; 1658 1659 rng1: rng@54003000 { 1660 compatible = "st,stm32-rng"; 1661 reg = <0x54003000 0x400>; 1662 clocks = <&rcc RNG1_K>; 1663 resets = <&rcc RNG1_R>; 1664 access-controllers = <&etzpc 7>; 1665 status = "disabled"; 1666 }; 1667 1668 fmc: memory-controller@58002000 { 1669 #address-cells = <2>; 1670 #size-cells = <1>; 1671 compatible = "st,stm32mp1-fmc2-ebi"; 1672 reg = <0x58002000 0x1000>; 1673 clocks = <&rcc FMC_K>; 1674 resets = <&rcc FMC_R>; 1675 access-controllers = <&etzpc 91>; 1676 status = "disabled"; 1677 1678 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1679 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1680 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1681 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1682 <4 0 0x80000000 0x10000000>; /* NAND */ 1683 1684 nand-controller@4,0 { 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 compatible = "st,stm32mp1-fmc2-nfc"; 1688 reg = <4 0x00000000 0x1000>, 1689 <4 0x08010000 0x1000>, 1690 <4 0x08020000 0x1000>, 1691 <4 0x01000000 0x1000>, 1692 <4 0x09010000 0x1000>, 1693 <4 0x09020000 0x1000>; 1694 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1695 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1696 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1697 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1698 dma-names = "tx", "rx", "ecc"; 1699 status = "disabled"; 1700 }; 1701 }; 1702 1703 qspi: spi@58003000 { 1704 compatible = "st,stm32f469-qspi"; 1705 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1706 reg-names = "qspi", "qspi_mm"; 1707 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1708 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1709 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1710 dma-names = "tx", "rx"; 1711 clocks = <&rcc QSPI_K>; 1712 resets = <&rcc QSPI_R>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 access-controllers = <&etzpc 92>; 1716 status = "disabled"; 1717 }; 1718 1719 ethernet0: ethernet@5800a000 { 1720 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1721 reg = <0x5800a000 0x2000>; 1722 reg-names = "stmmaceth"; 1723 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1724 interrupt-names = "macirq"; 1725 clock-names = "stmmaceth", 1726 "mac-clk-tx", 1727 "mac-clk-rx", 1728 "eth-ck", 1729 "ptp_ref", 1730 "ethstp"; 1731 clocks = <&rcc ETHMAC>, 1732 <&rcc ETHTX>, 1733 <&rcc ETHRX>, 1734 <&rcc ETHCK_K>, 1735 <&rcc ETHPTP_K>, 1736 <&rcc ETHSTP>; 1737 st,syscon = <&syscfg 0x4>; 1738 snps,mixed-burst; 1739 snps,pbl = <2>; 1740 snps,en-tx-lpi-clockgating; 1741 snps,axi-config = <&stmmac_axi_config_0>; 1742 snps,tso; 1743 access-controllers = <&etzpc 94>; 1744 status = "disabled"; 1745 1746 stmmac_axi_config_0: stmmac-axi-config { 1747 snps,wr_osr_lmt = <0x7>; 1748 snps,rd_osr_lmt = <0x7>; 1749 snps,blen = <0 0 0 0 16 8 4>; 1750 }; 1751 }; 1752 1753 usart1: serial@5c000000 { 1754 compatible = "st,stm32h7-uart"; 1755 reg = <0x5c000000 0x400>; 1756 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1757 clocks = <&rcc USART1_K>; 1758 wakeup-source; 1759 access-controllers = <&etzpc 3>; 1760 status = "disabled"; 1761 }; 1762 1763 spi6: spi@5c001000 { 1764 #address-cells = <1>; 1765 #size-cells = <0>; 1766 compatible = "st,stm32h7-spi"; 1767 reg = <0x5c001000 0x400>; 1768 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1769 clocks = <&rcc SPI6_K>; 1770 resets = <&rcc SPI6_R>; 1771 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1772 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1773 access-controllers = <&etzpc 4>; 1774 dma-names = "rx", "tx"; 1775 status = "disabled"; 1776 }; 1777 1778 i2c4: i2c@5c002000 { 1779 compatible = "st,stm32mp15-i2c"; 1780 reg = <0x5c002000 0x400>; 1781 interrupt-names = "event", "error"; 1782 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1784 clocks = <&rcc I2C4_K>; 1785 resets = <&rcc I2C4_R>; 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1789 wakeup-source; 1790 i2c-analog-filter; 1791 access-controllers = <&etzpc 5>; 1792 status = "disabled"; 1793 }; 1794 1795 i2c6: i2c@5c009000 { 1796 compatible = "st,stm32mp15-i2c"; 1797 reg = <0x5c009000 0x400>; 1798 interrupt-names = "event", "error"; 1799 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&rcc I2C6_K>; 1802 resets = <&rcc I2C6_R>; 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1806 wakeup-source; 1807 i2c-analog-filter; 1808 access-controllers = <&etzpc 12>; 1809 status = "disabled"; 1810 }; 1811 }; 1812 1813 tamp: tamp@5c00a000 { 1814 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 1815 reg = <0x5c00a000 0x400>; 1816 }; 1817 1818 /* 1819 * Break node order to solve dependency probe issue between 1820 * pinctrl and exti. 1821 */ 1822 pinctrl: pinctrl@50002000 { 1823 #address-cells = <1>; 1824 #size-cells = <1>; 1825 compatible = "st,stm32mp157-pinctrl"; 1826 ranges = <0 0x50002000 0xa400>; 1827 interrupt-parent = <&exti>; 1828 st,syscfg = <&exti 0x60 0xff>; 1829 1830 gpioa: gpio@50002000 { 1831 gpio-controller; 1832 #gpio-cells = <2>; 1833 interrupt-controller; 1834 #interrupt-cells = <2>; 1835 reg = <0x0 0x400>; 1836 clocks = <&rcc GPIOA>; 1837 st,bank-name = "GPIOA"; 1838 status = "disabled"; 1839 }; 1840 1841 gpiob: gpio@50003000 { 1842 gpio-controller; 1843 #gpio-cells = <2>; 1844 interrupt-controller; 1845 #interrupt-cells = <2>; 1846 reg = <0x1000 0x400>; 1847 clocks = <&rcc GPIOB>; 1848 st,bank-name = "GPIOB"; 1849 status = "disabled"; 1850 }; 1851 1852 gpioc: gpio@50004000 { 1853 gpio-controller; 1854 #gpio-cells = <2>; 1855 interrupt-controller; 1856 #interrupt-cells = <2>; 1857 reg = <0x2000 0x400>; 1858 clocks = <&rcc GPIOC>; 1859 st,bank-name = "GPIOC"; 1860 status = "disabled"; 1861 }; 1862 1863 gpiod: gpio@50005000 { 1864 gpio-controller; 1865 #gpio-cells = <2>; 1866 interrupt-controller; 1867 #interrupt-cells = <2>; 1868 reg = <0x3000 0x400>; 1869 clocks = <&rcc GPIOD>; 1870 st,bank-name = "GPIOD"; 1871 status = "disabled"; 1872 }; 1873 1874 gpioe: gpio@50006000 { 1875 gpio-controller; 1876 #gpio-cells = <2>; 1877 interrupt-controller; 1878 #interrupt-cells = <2>; 1879 reg = <0x4000 0x400>; 1880 clocks = <&rcc GPIOE>; 1881 st,bank-name = "GPIOE"; 1882 status = "disabled"; 1883 }; 1884 1885 gpiof: gpio@50007000 { 1886 gpio-controller; 1887 #gpio-cells = <2>; 1888 interrupt-controller; 1889 #interrupt-cells = <2>; 1890 reg = <0x5000 0x400>; 1891 clocks = <&rcc GPIOF>; 1892 st,bank-name = "GPIOF"; 1893 status = "disabled"; 1894 }; 1895 1896 gpiog: gpio@50008000 { 1897 gpio-controller; 1898 #gpio-cells = <2>; 1899 interrupt-controller; 1900 #interrupt-cells = <2>; 1901 reg = <0x6000 0x400>; 1902 clocks = <&rcc GPIOG>; 1903 st,bank-name = "GPIOG"; 1904 status = "disabled"; 1905 }; 1906 1907 gpioh: gpio@50009000 { 1908 gpio-controller; 1909 #gpio-cells = <2>; 1910 interrupt-controller; 1911 #interrupt-cells = <2>; 1912 reg = <0x7000 0x400>; 1913 clocks = <&rcc GPIOH>; 1914 st,bank-name = "GPIOH"; 1915 status = "disabled"; 1916 }; 1917 1918 gpioi: gpio@5000a000 { 1919 gpio-controller; 1920 #gpio-cells = <2>; 1921 interrupt-controller; 1922 #interrupt-cells = <2>; 1923 reg = <0x8000 0x400>; 1924 clocks = <&rcc GPIOI>; 1925 st,bank-name = "GPIOI"; 1926 status = "disabled"; 1927 }; 1928 1929 gpioj: gpio@5000b000 { 1930 gpio-controller; 1931 #gpio-cells = <2>; 1932 interrupt-controller; 1933 #interrupt-cells = <2>; 1934 reg = <0x9000 0x400>; 1935 clocks = <&rcc GPIOJ>; 1936 st,bank-name = "GPIOJ"; 1937 status = "disabled"; 1938 }; 1939 1940 gpiok: gpio@5000c000 { 1941 gpio-controller; 1942 #gpio-cells = <2>; 1943 interrupt-controller; 1944 #interrupt-cells = <2>; 1945 reg = <0xa000 0x400>; 1946 clocks = <&rcc GPIOK>; 1947 st,bank-name = "GPIOK"; 1948 status = "disabled"; 1949 }; 1950 }; 1951 1952 pinctrl_z: pinctrl@54004000 { 1953 #address-cells = <1>; 1954 #size-cells = <1>; 1955 compatible = "st,stm32mp157-z-pinctrl"; 1956 ranges = <0 0x54004000 0x400>; 1957 interrupt-parent = <&exti>; 1958 st,syscfg = <&exti 0x60 0xff>; 1959 1960 gpioz: gpio@54004000 { 1961 gpio-controller; 1962 #gpio-cells = <2>; 1963 interrupt-controller; 1964 #interrupt-cells = <2>; 1965 reg = <0 0x400>; 1966 clocks = <&rcc GPIOZ>; 1967 st,bank-name = "GPIOZ"; 1968 st,bank-ioport = <11>; 1969 status = "disabled"; 1970 }; 1971 }; 1972 }; 1973 1974 mlahb: ahb { 1975 compatible = "st,mlahb", "simple-bus"; 1976 #address-cells = <1>; 1977 #size-cells = <1>; 1978 ranges; 1979 dma-ranges = <0x00000000 0x38000000 0x10000>, 1980 <0x10000000 0x10000000 0x60000>, 1981 <0x30000000 0x30000000 0x60000>; 1982 1983 m4_rproc: m4@10000000 { 1984 compatible = "st,stm32mp1-m4"; 1985 reg = <0x10000000 0x40000>, 1986 <0x30000000 0x40000>, 1987 <0x38000000 0x10000>; 1988 resets = <&rcc MCU_R>; 1989 reset-names = "mcu_rst"; 1990 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 1991 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1992 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1993 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1994 status = "disabled"; 1995 }; 1996 }; 1997}; 1998