1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/reset/stm32mp13-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 device_type = "cpu"; 21 reg = <0>; 22 }; 23 }; 24 25 arm-pmu { 26 compatible = "arm,cortex-a7-pmu"; 27 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 28 interrupt-affinity = <&cpu0>; 29 interrupt-parent = <&intc>; 30 }; 31 32 firmware { 33 optee { 34 method = "smc"; 35 compatible = "linaro,optee-tz"; 36 interrupt-parent = <&intc>; 37 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 38 }; 39 40 scmi: scmi { 41 compatible = "linaro,scmi-optee"; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 linaro,optee-channel-id = <0>; 45 46 scmi_clk: protocol@14 { 47 reg = <0x14>; 48 #clock-cells = <1>; 49 }; 50 51 scmi_reset: protocol@16 { 52 reg = <0x16>; 53 #reset-cells = <1>; 54 }; 55 56 scmi_voltd: protocol@17 { 57 reg = <0x17>; 58 59 scmi_regu: regulators { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 scmi_reg11: regulator@0 { 64 reg = <VOLTD_SCMI_REG11>; 65 regulator-name = "reg11"; 66 }; 67 scmi_reg18: regulator@1 { 68 reg = <VOLTD_SCMI_REG18>; 69 regulator-name = "reg18"; 70 }; 71 scmi_usb33: regulator@2 { 72 reg = <VOLTD_SCMI_USB33>; 73 regulator-name = "usb33"; 74 }; 75 }; 76 }; 77 }; 78 }; 79 80 intc: interrupt-controller@a0021000 { 81 compatible = "arm,cortex-a7-gic"; 82 #interrupt-cells = <3>; 83 interrupt-controller; 84 reg = <0xa0021000 0x1000>, 85 <0xa0022000 0x2000>; 86 }; 87 88 psci { 89 compatible = "arm,psci-1.0"; 90 method = "smc"; 91 }; 92 93 timer { 94 compatible = "arm,armv7-timer"; 95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 99 interrupt-parent = <&intc>; 100 always-on; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 interrupt-parent = <&intc>; 108 ranges; 109 110 timers2: timer@40000000 { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 compatible = "st,stm32-timers"; 114 reg = <0x40000000 0x400>; 115 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-names = "global"; 117 clocks = <&rcc TIM2_K>; 118 clock-names = "int"; 119 dmas = <&dmamux1 18 0x400 0x1>, 120 <&dmamux1 19 0x400 0x1>, 121 <&dmamux1 20 0x400 0x1>, 122 <&dmamux1 21 0x400 0x1>, 123 <&dmamux1 22 0x400 0x1>; 124 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 125 status = "disabled"; 126 127 pwm { 128 compatible = "st,stm32-pwm"; 129 #pwm-cells = <3>; 130 status = "disabled"; 131 }; 132 133 timer@1 { 134 compatible = "st,stm32h7-timer-trigger"; 135 reg = <1>; 136 status = "disabled"; 137 }; 138 139 counter { 140 compatible = "st,stm32-timer-counter"; 141 status = "disabled"; 142 }; 143 }; 144 145 timers3: timer@40001000 { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 compatible = "st,stm32-timers"; 149 reg = <0x40001000 0x400>; 150 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-names = "global"; 152 clocks = <&rcc TIM3_K>; 153 clock-names = "int"; 154 dmas = <&dmamux1 23 0x400 0x1>, 155 <&dmamux1 24 0x400 0x1>, 156 <&dmamux1 25 0x400 0x1>, 157 <&dmamux1 26 0x400 0x1>, 158 <&dmamux1 27 0x400 0x1>, 159 <&dmamux1 28 0x400 0x1>; 160 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 161 status = "disabled"; 162 163 pwm { 164 compatible = "st,stm32-pwm"; 165 #pwm-cells = <3>; 166 status = "disabled"; 167 }; 168 169 timer@2 { 170 compatible = "st,stm32h7-timer-trigger"; 171 reg = <2>; 172 status = "disabled"; 173 }; 174 175 counter { 176 compatible = "st,stm32-timer-counter"; 177 status = "disabled"; 178 }; 179 }; 180 181 timers4: timer@40002000 { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 compatible = "st,stm32-timers"; 185 reg = <0x40002000 0x400>; 186 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 187 interrupt-names = "global"; 188 clocks = <&rcc TIM4_K>; 189 clock-names = "int"; 190 dmas = <&dmamux1 29 0x400 0x1>, 191 <&dmamux1 30 0x400 0x1>, 192 <&dmamux1 31 0x400 0x1>, 193 <&dmamux1 32 0x400 0x1>; 194 dma-names = "ch1", "ch2", "ch3", "up"; 195 status = "disabled"; 196 197 pwm { 198 compatible = "st,stm32-pwm"; 199 #pwm-cells = <3>; 200 status = "disabled"; 201 }; 202 203 timer@3 { 204 compatible = "st,stm32h7-timer-trigger"; 205 reg = <3>; 206 status = "disabled"; 207 }; 208 209 counter { 210 compatible = "st,stm32-timer-counter"; 211 status = "disabled"; 212 }; 213 }; 214 215 timers5: timer@40003000 { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 compatible = "st,stm32-timers"; 219 reg = <0x40003000 0x400>; 220 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 221 interrupt-names = "global"; 222 clocks = <&rcc TIM5_K>; 223 clock-names = "int"; 224 dmas = <&dmamux1 55 0x400 0x1>, 225 <&dmamux1 56 0x400 0x1>, 226 <&dmamux1 57 0x400 0x1>, 227 <&dmamux1 58 0x400 0x1>, 228 <&dmamux1 59 0x400 0x1>, 229 <&dmamux1 60 0x400 0x1>; 230 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 231 status = "disabled"; 232 233 pwm { 234 compatible = "st,stm32-pwm"; 235 #pwm-cells = <3>; 236 status = "disabled"; 237 }; 238 239 timer@4 { 240 compatible = "st,stm32h7-timer-trigger"; 241 reg = <4>; 242 status = "disabled"; 243 }; 244 245 counter { 246 compatible = "st,stm32-timer-counter"; 247 status = "disabled"; 248 }; 249 }; 250 251 timers6: timer@40004000 { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 compatible = "st,stm32-timers"; 255 reg = <0x40004000 0x400>; 256 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 257 interrupt-names = "global"; 258 clocks = <&rcc TIM6_K>; 259 clock-names = "int"; 260 dmas = <&dmamux1 69 0x400 0x1>; 261 dma-names = "up"; 262 status = "disabled"; 263 264 timer@5 { 265 compatible = "st,stm32h7-timer-trigger"; 266 reg = <5>; 267 status = "disabled"; 268 }; 269 }; 270 271 timers7: timer@40005000 { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 compatible = "st,stm32-timers"; 275 reg = <0x40005000 0x400>; 276 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "global"; 278 clocks = <&rcc TIM7_K>; 279 clock-names = "int"; 280 dmas = <&dmamux1 70 0x400 0x1>; 281 dma-names = "up"; 282 status = "disabled"; 283 284 timer@6 { 285 compatible = "st,stm32h7-timer-trigger"; 286 reg = <6>; 287 status = "disabled"; 288 }; 289 }; 290 291 lptimer1: timer@40009000 { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 compatible = "st,stm32-lptimer"; 295 reg = <0x40009000 0x400>; 296 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&rcc LPTIM1_K>; 298 clock-names = "mux"; 299 wakeup-source; 300 status = "disabled"; 301 302 pwm { 303 compatible = "st,stm32-pwm-lp"; 304 #pwm-cells = <3>; 305 status = "disabled"; 306 }; 307 308 trigger@0 { 309 compatible = "st,stm32-lptimer-trigger"; 310 reg = <0>; 311 status = "disabled"; 312 }; 313 314 counter { 315 compatible = "st,stm32-lptimer-counter"; 316 status = "disabled"; 317 }; 318 319 timer { 320 compatible = "st,stm32-lptimer-timer"; 321 status = "disabled"; 322 }; 323 }; 324 325 i2s2: audio-controller@4000b000 { 326 compatible = "st,stm32h7-i2s"; 327 reg = <0x4000b000 0x400>; 328 #sound-dai-cells = <0>; 329 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 330 dmas = <&dmamux1 39 0x400 0x01>, 331 <&dmamux1 40 0x400 0x01>; 332 dma-names = "rx", "tx"; 333 status = "disabled"; 334 }; 335 336 spi2: spi@4000b000 { 337 compatible = "st,stm32h7-spi"; 338 reg = <0x4000b000 0x400>; 339 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&rcc SPI2_K>; 341 resets = <&rcc SPI2_R>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 dmas = <&dmamux1 39 0x400 0x01>, 345 <&dmamux1 40 0x400 0x01>; 346 dma-names = "rx", "tx"; 347 status = "disabled"; 348 }; 349 350 i2s3: audio-controller@4000c000 { 351 compatible = "st,stm32h7-i2s"; 352 reg = <0x4000c000 0x400>; 353 #sound-dai-cells = <0>; 354 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 355 dmas = <&dmamux1 61 0x400 0x01>, 356 <&dmamux1 62 0x400 0x01>; 357 dma-names = "rx", "tx"; 358 status = "disabled"; 359 }; 360 361 spi3: spi@4000c000 { 362 compatible = "st,stm32h7-spi"; 363 reg = <0x4000c000 0x400>; 364 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&rcc SPI3_K>; 366 resets = <&rcc SPI3_R>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 dmas = <&dmamux1 61 0x400 0x01>, 370 <&dmamux1 62 0x400 0x01>; 371 dma-names = "rx", "tx"; 372 status = "disabled"; 373 }; 374 375 spdifrx: audio-controller@4000d000 { 376 compatible = "st,stm32h7-spdifrx"; 377 reg = <0x4000d000 0x400>; 378 #sound-dai-cells = <0>; 379 clocks = <&rcc SPDIF_K>; 380 clock-names = "kclk"; 381 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 382 dmas = <&dmamux1 93 0x400 0x01>, 383 <&dmamux1 94 0x400 0x01>; 384 dma-names = "rx", "rx-ctrl"; 385 status = "disabled"; 386 }; 387 388 usart3: serial@4000f000 { 389 compatible = "st,stm32h7-uart"; 390 reg = <0x4000f000 0x400>; 391 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&rcc USART3_K>; 393 resets = <&rcc USART3_R>; 394 wakeup-source; 395 dmas = <&dmamux1 45 0x400 0x5>, 396 <&dmamux1 46 0x400 0x1>; 397 dma-names = "rx", "tx"; 398 status = "disabled"; 399 }; 400 401 uart4: serial@40010000 { 402 compatible = "st,stm32h7-uart"; 403 reg = <0x40010000 0x400>; 404 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&rcc UART4_K>; 406 resets = <&rcc UART4_R>; 407 wakeup-source; 408 dmas = <&dmamux1 63 0x400 0x5>, 409 <&dmamux1 64 0x400 0x1>; 410 dma-names = "rx", "tx"; 411 status = "disabled"; 412 }; 413 414 uart5: serial@40011000 { 415 compatible = "st,stm32h7-uart"; 416 reg = <0x40011000 0x400>; 417 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&rcc UART5_K>; 419 resets = <&rcc UART5_R>; 420 wakeup-source; 421 dmas = <&dmamux1 65 0x400 0x5>, 422 <&dmamux1 66 0x400 0x1>; 423 dma-names = "rx", "tx"; 424 status = "disabled"; 425 }; 426 427 i2c1: i2c@40012000 { 428 compatible = "st,stm32mp13-i2c"; 429 reg = <0x40012000 0x400>; 430 interrupt-names = "event", "error"; 431 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&rcc I2C1_K>; 434 resets = <&rcc I2C1_R>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 dmas = <&dmamux1 33 0x400 0x1>, 438 <&dmamux1 34 0x400 0x1>; 439 dma-names = "rx", "tx"; 440 st,syscfg-fmp = <&syscfg 0x4 0x1>; 441 i2c-analog-filter; 442 status = "disabled"; 443 }; 444 445 i2c2: i2c@40013000 { 446 compatible = "st,stm32mp13-i2c"; 447 reg = <0x40013000 0x400>; 448 interrupt-names = "event", "error"; 449 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&rcc I2C2_K>; 452 resets = <&rcc I2C2_R>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 dmas = <&dmamux1 35 0x400 0x1>, 456 <&dmamux1 36 0x400 0x1>; 457 dma-names = "rx", "tx"; 458 st,syscfg-fmp = <&syscfg 0x4 0x2>; 459 i2c-analog-filter; 460 status = "disabled"; 461 }; 462 463 uart7: serial@40018000 { 464 compatible = "st,stm32h7-uart"; 465 reg = <0x40018000 0x400>; 466 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&rcc UART7_K>; 468 resets = <&rcc UART7_R>; 469 wakeup-source; 470 dmas = <&dmamux1 79 0x400 0x5>, 471 <&dmamux1 80 0x400 0x1>; 472 dma-names = "rx", "tx"; 473 status = "disabled"; 474 }; 475 476 uart8: serial@40019000 { 477 compatible = "st,stm32h7-uart"; 478 reg = <0x40019000 0x400>; 479 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&rcc UART8_K>; 481 resets = <&rcc UART8_R>; 482 wakeup-source; 483 dmas = <&dmamux1 81 0x400 0x5>, 484 <&dmamux1 82 0x400 0x1>; 485 dma-names = "rx", "tx"; 486 status = "disabled"; 487 }; 488 489 timers1: timer@44000000 { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 compatible = "st,stm32-timers"; 493 reg = <0x44000000 0x400>; 494 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 498 interrupt-names = "brk", "up", "trg-com", "cc"; 499 clocks = <&rcc TIM1_K>; 500 clock-names = "int"; 501 dmas = <&dmamux1 11 0x400 0x1>, 502 <&dmamux1 12 0x400 0x1>, 503 <&dmamux1 13 0x400 0x1>, 504 <&dmamux1 14 0x400 0x1>, 505 <&dmamux1 15 0x400 0x1>, 506 <&dmamux1 16 0x400 0x1>, 507 <&dmamux1 17 0x400 0x1>; 508 dma-names = "ch1", "ch2", "ch3", "ch4", 509 "up", "trig", "com"; 510 status = "disabled"; 511 512 pwm { 513 compatible = "st,stm32-pwm"; 514 #pwm-cells = <3>; 515 status = "disabled"; 516 }; 517 518 timer@0 { 519 compatible = "st,stm32h7-timer-trigger"; 520 reg = <0>; 521 status = "disabled"; 522 }; 523 524 counter { 525 compatible = "st,stm32-timer-counter"; 526 status = "disabled"; 527 }; 528 }; 529 530 timers8: timer@44001000 { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 compatible = "st,stm32-timers"; 534 reg = <0x44001000 0x400>; 535 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 539 interrupt-names = "brk", "up", "trg-com", "cc"; 540 clocks = <&rcc TIM8_K>; 541 clock-names = "int"; 542 dmas = <&dmamux1 47 0x400 0x1>, 543 <&dmamux1 48 0x400 0x1>, 544 <&dmamux1 49 0x400 0x1>, 545 <&dmamux1 50 0x400 0x1>, 546 <&dmamux1 51 0x400 0x1>, 547 <&dmamux1 52 0x400 0x1>, 548 <&dmamux1 53 0x400 0x1>; 549 dma-names = "ch1", "ch2", "ch3", "ch4", 550 "up", "trig", "com"; 551 status = "disabled"; 552 553 pwm { 554 compatible = "st,stm32-pwm"; 555 #pwm-cells = <3>; 556 status = "disabled"; 557 }; 558 559 timer@7 { 560 compatible = "st,stm32h7-timer-trigger"; 561 reg = <7>; 562 status = "disabled"; 563 }; 564 565 counter { 566 compatible = "st,stm32-timer-counter"; 567 status = "disabled"; 568 }; 569 }; 570 571 usart6: serial@44003000 { 572 compatible = "st,stm32h7-uart"; 573 reg = <0x44003000 0x400>; 574 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&rcc USART6_K>; 576 resets = <&rcc USART6_R>; 577 wakeup-source; 578 dmas = <&dmamux1 71 0x400 0x5>, 579 <&dmamux1 72 0x400 0x1>; 580 dma-names = "rx", "tx"; 581 status = "disabled"; 582 }; 583 584 i2s1: audio-controller@44004000 { 585 compatible = "st,stm32h7-i2s"; 586 reg = <0x44004000 0x400>; 587 #sound-dai-cells = <0>; 588 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 589 dmas = <&dmamux1 37 0x400 0x01>, 590 <&dmamux1 38 0x400 0x01>; 591 dma-names = "rx", "tx"; 592 status = "disabled"; 593 }; 594 595 spi1: spi@44004000 { 596 compatible = "st,stm32h7-spi"; 597 reg = <0x44004000 0x400>; 598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&rcc SPI1_K>; 600 resets = <&rcc SPI1_R>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 dmas = <&dmamux1 37 0x400 0x01>, 604 <&dmamux1 38 0x400 0x01>; 605 dma-names = "rx", "tx"; 606 status = "disabled"; 607 }; 608 609 sai1: sai@4400a000 { 610 compatible = "st,stm32h7-sai"; 611 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 612 ranges = <0 0x4400a000 0x400>; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 616 resets = <&rcc SAI1_R>; 617 status = "disabled"; 618 619 sai1a: audio-controller@4400a004 { 620 compatible = "st,stm32-sai-sub-a"; 621 reg = <0x4 0x20>; 622 #sound-dai-cells = <0>; 623 clocks = <&rcc SAI1_K>; 624 clock-names = "sai_ck"; 625 dmas = <&dmamux1 87 0x400 0x01>; 626 status = "disabled"; 627 }; 628 629 sai1b: audio-controller@4400a024 { 630 compatible = "st,stm32-sai-sub-b"; 631 reg = <0x24 0x20>; 632 #sound-dai-cells = <0>; 633 clocks = <&rcc SAI1_K>; 634 clock-names = "sai_ck"; 635 dmas = <&dmamux1 88 0x400 0x01>; 636 status = "disabled"; 637 }; 638 }; 639 640 sai2: sai@4400b000 { 641 compatible = "st,stm32h7-sai"; 642 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 643 ranges = <0 0x4400b000 0x400>; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 647 resets = <&rcc SAI2_R>; 648 status = "disabled"; 649 650 sai2a: audio-controller@4400b004 { 651 compatible = "st,stm32-sai-sub-a"; 652 reg = <0x4 0x20>; 653 #sound-dai-cells = <0>; 654 clocks = <&rcc SAI2_K>; 655 clock-names = "sai_ck"; 656 dmas = <&dmamux1 89 0x400 0x01>; 657 status = "disabled"; 658 }; 659 660 sai2b: audio-controller@4400b024 { 661 compatible = "st,stm32-sai-sub-b"; 662 reg = <0x24 0x20>; 663 #sound-dai-cells = <0>; 664 clocks = <&rcc SAI2_K>; 665 clock-names = "sai_ck"; 666 dmas = <&dmamux1 90 0x400 0x01>; 667 status = "disabled"; 668 }; 669 }; 670 671 dfsdm: dfsdm@4400d000 { 672 compatible = "st,stm32mp1-dfsdm"; 673 reg = <0x4400d000 0x800>; 674 clocks = <&rcc DFSDM_K>; 675 clock-names = "dfsdm"; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 status = "disabled"; 679 680 dfsdm0: filter@0 { 681 compatible = "st,stm32-dfsdm-adc"; 682 reg = <0>; 683 #io-channel-cells = <1>; 684 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 685 dmas = <&dmamux1 101 0x400 0x01>; 686 dma-names = "rx"; 687 status = "disabled"; 688 }; 689 690 dfsdm1: filter@1 { 691 compatible = "st,stm32-dfsdm-adc"; 692 reg = <1>; 693 #io-channel-cells = <1>; 694 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 695 dmas = <&dmamux1 102 0x400 0x01>; 696 dma-names = "rx"; 697 status = "disabled"; 698 }; 699 }; 700 701 dma1: dma-controller@48000000 { 702 compatible = "st,stm32-dma"; 703 reg = <0x48000000 0x400>; 704 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&rcc DMA1>; 713 resets = <&rcc DMA1_R>; 714 #dma-cells = <4>; 715 st,mem2mem; 716 dma-requests = <8>; 717 }; 718 719 dma2: dma-controller@48001000 { 720 compatible = "st,stm32-dma"; 721 reg = <0x48001000 0x400>; 722 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&rcc DMA2>; 731 resets = <&rcc DMA2_R>; 732 #dma-cells = <4>; 733 st,mem2mem; 734 dma-requests = <8>; 735 }; 736 737 dmamux1: dma-router@48002000 { 738 compatible = "st,stm32h7-dmamux"; 739 reg = <0x48002000 0x40>; 740 clocks = <&rcc DMAMUX1>; 741 resets = <&rcc DMAMUX1_R>; 742 #dma-cells = <3>; 743 dma-masters = <&dma1 &dma2>; 744 dma-requests = <128>; 745 dma-channels = <16>; 746 }; 747 748 rcc: rcc@50000000 { 749 compatible = "st,stm32mp13-rcc", "syscon"; 750 reg = <0x50000000 0x1000>; 751 #clock-cells = <1>; 752 #reset-cells = <1>; 753 clock-names = "hse", "hsi", "csi", "lse", "lsi"; 754 clocks = <&scmi_clk CK_SCMI_HSE>, 755 <&scmi_clk CK_SCMI_HSI>, 756 <&scmi_clk CK_SCMI_CSI>, 757 <&scmi_clk CK_SCMI_LSE>, 758 <&scmi_clk CK_SCMI_LSI>; 759 }; 760 761 pwr_regulators: pwr@50001000 { 762 compatible = "st,stm32mp1,pwr-reg"; 763 reg = <0x50001000 0x10>; 764 status = "disabled"; 765 766 reg11: reg11 { 767 regulator-name = "reg11"; 768 regulator-min-microvolt = <1100000>; 769 regulator-max-microvolt = <1100000>; 770 }; 771 772 reg18: reg18 { 773 regulator-name = "reg18"; 774 regulator-min-microvolt = <1800000>; 775 regulator-max-microvolt = <1800000>; 776 }; 777 778 usb33: usb33 { 779 regulator-name = "usb33"; 780 regulator-min-microvolt = <3300000>; 781 regulator-max-microvolt = <3300000>; 782 }; 783 }; 784 785 exti: interrupt-controller@5000d000 { 786 compatible = "st,stm32mp1-exti", "syscon"; 787 interrupt-controller; 788 #interrupt-cells = <2>; 789 reg = <0x5000d000 0x400>; 790 interrupts-extended = 791 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 792 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 793 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 794 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 795 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 796 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 797 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 798 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 799 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 800 <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 801 <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 802 <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 803 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 804 <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 805 <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 806 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 807 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 808 <0>, 809 <0>, 810 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 811 <0>, /* EXTI_20 */ 812 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 813 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 814 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 815 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 816 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 817 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 818 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 819 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 820 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 821 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 822 <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 823 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 824 <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 825 <0>, 826 <0>, 827 <0>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, /* EXTI_40 */ 832 <0>, 833 <0>, 834 <0>, 835 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 836 <0>, 837 <0>, 838 <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 839 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 840 <0>, 841 <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 842 <0>, 843 <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 844 <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 845 <0>, 846 <0>, 847 <0>, 848 <0>, 849 <0>, 850 <0>, 851 <0>, /* EXTI_60 */ 852 <0>, 853 <0>, 854 <0>, 855 <0>, 856 <0>, 857 <0>, 858 <0>, 859 <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 860 <0>, 861 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 862 }; 863 864 syscfg: syscon@50020000 { 865 compatible = "st,stm32mp157-syscfg", "syscon"; 866 reg = <0x50020000 0x400>; 867 clocks = <&rcc SYSCFG>; 868 }; 869 870 lptimer4: timer@50023000 { 871 compatible = "st,stm32-lptimer"; 872 reg = <0x50023000 0x400>; 873 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&rcc LPTIM4_K>; 875 clock-names = "mux"; 876 wakeup-source; 877 status = "disabled"; 878 879 pwm { 880 compatible = "st,stm32-pwm-lp"; 881 #pwm-cells = <3>; 882 status = "disabled"; 883 }; 884 885 timer { 886 compatible = "st,stm32-lptimer-timer"; 887 status = "disabled"; 888 }; 889 }; 890 891 lptimer5: timer@50024000 { 892 compatible = "st,stm32-lptimer"; 893 reg = <0x50024000 0x400>; 894 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&rcc LPTIM5_K>; 896 clock-names = "mux"; 897 wakeup-source; 898 status = "disabled"; 899 900 pwm { 901 compatible = "st,stm32-pwm-lp"; 902 #pwm-cells = <3>; 903 status = "disabled"; 904 }; 905 906 timer { 907 compatible = "st,stm32-lptimer-timer"; 908 status = "disabled"; 909 }; 910 }; 911 912 mdma: dma-controller@58000000 { 913 compatible = "st,stm32h7-mdma"; 914 reg = <0x58000000 0x1000>; 915 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&rcc MDMA>; 917 #dma-cells = <5>; 918 dma-channels = <32>; 919 dma-requests = <48>; 920 }; 921 922 crc1: crc@58009000 { 923 compatible = "st,stm32f7-crc"; 924 reg = <0x58009000 0x400>; 925 clocks = <&rcc CRC1>; 926 status = "disabled"; 927 }; 928 929 usbh_ohci: usb@5800c000 { 930 compatible = "generic-ohci"; 931 reg = <0x5800c000 0x1000>; 932 clocks = <&usbphyc>, <&rcc USBH>; 933 resets = <&rcc USBH_R>; 934 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 935 status = "disabled"; 936 }; 937 938 usbh_ehci: usb@5800d000 { 939 compatible = "generic-ehci"; 940 reg = <0x5800d000 0x1000>; 941 clocks = <&usbphyc>, <&rcc USBH>; 942 resets = <&rcc USBH_R>; 943 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 944 companion = <&usbh_ohci>; 945 status = "disabled"; 946 }; 947 948 iwdg2: watchdog@5a002000 { 949 compatible = "st,stm32mp1-iwdg"; 950 reg = <0x5a002000 0x400>; 951 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; 952 clock-names = "pclk", "lsi"; 953 status = "disabled"; 954 }; 955 956 rtc: rtc@5c004000 { 957 compatible = "st,stm32mp1-rtc"; 958 reg = <0x5c004000 0x400>; 959 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&scmi_clk CK_SCMI_RTCAPB>, 961 <&scmi_clk CK_SCMI_RTC>; 962 clock-names = "pclk", "rtc_ck"; 963 status = "disabled"; 964 }; 965 966 bsec: efuse@5c005000 { 967 compatible = "st,stm32mp13-bsec"; 968 reg = <0x5c005000 0x400>; 969 #address-cells = <1>; 970 #size-cells = <1>; 971 972 part_number_otp: part_number_otp@4 { 973 reg = <0x4 0x2>; 974 bits = <0 12>; 975 }; 976 ts_cal1: calib@5c { 977 reg = <0x5c 0x2>; 978 }; 979 ts_cal2: calib@5e { 980 reg = <0x5e 0x2>; 981 }; 982 }; 983 984 etzpc: bus@5c007000 { 985 compatible = "st,stm32-etzpc", "simple-bus"; 986 reg = <0x5c007000 0x400>; 987 #address-cells = <1>; 988 #size-cells = <1>; 989 #access-controller-cells = <1>; 990 ranges; 991 992 adc_2: adc@48004000 { 993 compatible = "st,stm32mp13-adc-core"; 994 reg = <0x48004000 0x400>; 995 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 997 clock-names = "bus", "adc"; 998 interrupt-controller; 999 #interrupt-cells = <1>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 access-controllers = <&etzpc 33>; 1003 status = "disabled"; 1004 1005 adc2: adc@0 { 1006 compatible = "st,stm32mp13-adc"; 1007 #io-channel-cells = <1>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 reg = <0x0>; 1011 interrupt-parent = <&adc_2>; 1012 interrupts = <0>; 1013 dmas = <&dmamux1 10 0x400 0x80000001>; 1014 dma-names = "rx"; 1015 status = "disabled"; 1016 1017 channel@13 { 1018 reg = <13>; 1019 label = "vrefint"; 1020 }; 1021 channel@14 { 1022 reg = <14>; 1023 label = "vddcore"; 1024 }; 1025 channel@16 { 1026 reg = <16>; 1027 label = "vddcpu"; 1028 }; 1029 channel@17 { 1030 reg = <17>; 1031 label = "vddq_ddr"; 1032 }; 1033 }; 1034 }; 1035 1036 usbotg_hs: usb@49000000 { 1037 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1038 reg = <0x49000000 0x40000>; 1039 clocks = <&rcc USBO_K>; 1040 clock-names = "otg"; 1041 resets = <&rcc USBO_R>; 1042 reset-names = "dwc2"; 1043 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1044 g-rx-fifo-size = <512>; 1045 g-np-tx-fifo-size = <32>; 1046 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1047 dr_mode = "otg"; 1048 otg-rev = <0x200>; 1049 usb33d-supply = <&scmi_usb33>; 1050 access-controllers = <&etzpc 34>; 1051 status = "disabled"; 1052 }; 1053 1054 usart1: serial@4c000000 { 1055 compatible = "st,stm32h7-uart"; 1056 reg = <0x4c000000 0x400>; 1057 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&rcc USART1_K>; 1059 resets = <&rcc USART1_R>; 1060 wakeup-source; 1061 dmas = <&dmamux1 41 0x400 0x5>, 1062 <&dmamux1 42 0x400 0x1>; 1063 dma-names = "rx", "tx"; 1064 access-controllers = <&etzpc 16>; 1065 status = "disabled"; 1066 }; 1067 1068 usart2: serial@4c001000 { 1069 compatible = "st,stm32h7-uart"; 1070 reg = <0x4c001000 0x400>; 1071 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&rcc USART2_K>; 1073 resets = <&rcc USART2_R>; 1074 wakeup-source; 1075 dmas = <&dmamux1 43 0x400 0x5>, 1076 <&dmamux1 44 0x400 0x1>; 1077 dma-names = "rx", "tx"; 1078 access-controllers = <&etzpc 17>; 1079 status = "disabled"; 1080 }; 1081 1082 i2s4: audio-controller@4c002000 { 1083 compatible = "st,stm32h7-i2s"; 1084 reg = <0x4c002000 0x400>; 1085 #sound-dai-cells = <0>; 1086 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1087 dmas = <&dmamux1 83 0x400 0x01>, 1088 <&dmamux1 84 0x400 0x01>; 1089 dma-names = "rx", "tx"; 1090 access-controllers = <&etzpc 13>; 1091 status = "disabled"; 1092 }; 1093 1094 spi4: spi@4c002000 { 1095 compatible = "st,stm32h7-spi"; 1096 reg = <0x4c002000 0x400>; 1097 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&rcc SPI4_K>; 1099 resets = <&rcc SPI4_R>; 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 dmas = <&dmamux1 83 0x400 0x01>, 1103 <&dmamux1 84 0x400 0x01>; 1104 dma-names = "rx", "tx"; 1105 access-controllers = <&etzpc 18>; 1106 status = "disabled"; 1107 }; 1108 1109 spi5: spi@4c003000 { 1110 compatible = "st,stm32h7-spi"; 1111 reg = <0x4c003000 0x400>; 1112 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&rcc SPI5_K>; 1114 resets = <&rcc SPI5_R>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 dmas = <&dmamux1 85 0x400 0x01>, 1118 <&dmamux1 86 0x400 0x01>; 1119 dma-names = "rx", "tx"; 1120 access-controllers = <&etzpc 19>; 1121 status = "disabled"; 1122 }; 1123 1124 i2c3: i2c@4c004000 { 1125 compatible = "st,stm32mp13-i2c"; 1126 reg = <0x4c004000 0x400>; 1127 interrupt-names = "event", "error"; 1128 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&rcc I2C3_K>; 1131 resets = <&rcc I2C3_R>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 dmas = <&dmamux1 73 0x400 0x1>, 1135 <&dmamux1 74 0x400 0x1>; 1136 dma-names = "rx", "tx"; 1137 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1138 i2c-analog-filter; 1139 access-controllers = <&etzpc 20>; 1140 status = "disabled"; 1141 }; 1142 1143 i2c4: i2c@4c005000 { 1144 compatible = "st,stm32mp13-i2c"; 1145 reg = <0x4c005000 0x400>; 1146 interrupt-names = "event", "error"; 1147 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&rcc I2C4_K>; 1150 resets = <&rcc I2C4_R>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 dmas = <&dmamux1 75 0x400 0x1>, 1154 <&dmamux1 76 0x400 0x1>; 1155 dma-names = "rx", "tx"; 1156 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1157 i2c-analog-filter; 1158 access-controllers = <&etzpc 21>; 1159 status = "disabled"; 1160 }; 1161 1162 i2c5: i2c@4c006000 { 1163 compatible = "st,stm32mp13-i2c"; 1164 reg = <0x4c006000 0x400>; 1165 interrupt-names = "event", "error"; 1166 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&rcc I2C5_K>; 1169 resets = <&rcc I2C5_R>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 dmas = <&dmamux1 115 0x400 0x1>, 1173 <&dmamux1 116 0x400 0x1>; 1174 dma-names = "rx", "tx"; 1175 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1176 i2c-analog-filter; 1177 access-controllers = <&etzpc 22>; 1178 status = "disabled"; 1179 }; 1180 1181 timers12: timer@4c007000 { 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 compatible = "st,stm32-timers"; 1185 reg = <0x4c007000 0x400>; 1186 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1187 interrupt-names = "global"; 1188 clocks = <&rcc TIM12_K>; 1189 clock-names = "int"; 1190 access-controllers = <&etzpc 23>; 1191 status = "disabled"; 1192 1193 pwm { 1194 compatible = "st,stm32-pwm"; 1195 #pwm-cells = <3>; 1196 status = "disabled"; 1197 }; 1198 1199 timer@11 { 1200 compatible = "st,stm32h7-timer-trigger"; 1201 reg = <11>; 1202 status = "disabled"; 1203 }; 1204 }; 1205 1206 timers13: timer@4c008000 { 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 compatible = "st,stm32-timers"; 1210 reg = <0x4c008000 0x400>; 1211 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1212 interrupt-names = "global"; 1213 clocks = <&rcc TIM13_K>; 1214 clock-names = "int"; 1215 access-controllers = <&etzpc 24>; 1216 status = "disabled"; 1217 1218 pwm { 1219 compatible = "st,stm32-pwm"; 1220 #pwm-cells = <3>; 1221 status = "disabled"; 1222 }; 1223 1224 timer@12 { 1225 compatible = "st,stm32h7-timer-trigger"; 1226 reg = <12>; 1227 status = "disabled"; 1228 }; 1229 }; 1230 1231 timers14: timer@4c009000 { 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 compatible = "st,stm32-timers"; 1235 reg = <0x4c009000 0x400>; 1236 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1237 interrupt-names = "global"; 1238 clocks = <&rcc TIM14_K>; 1239 clock-names = "int"; 1240 access-controllers = <&etzpc 25>; 1241 status = "disabled"; 1242 1243 pwm { 1244 compatible = "st,stm32-pwm"; 1245 #pwm-cells = <3>; 1246 status = "disabled"; 1247 }; 1248 1249 timer@13 { 1250 compatible = "st,stm32h7-timer-trigger"; 1251 reg = <13>; 1252 status = "disabled"; 1253 }; 1254 }; 1255 1256 timers15: timer@4c00a000 { 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 compatible = "st,stm32-timers"; 1260 reg = <0x4c00a000 0x400>; 1261 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1262 interrupt-names = "global"; 1263 clocks = <&rcc TIM15_K>; 1264 clock-names = "int"; 1265 dmas = <&dmamux1 105 0x400 0x1>, 1266 <&dmamux1 106 0x400 0x1>, 1267 <&dmamux1 107 0x400 0x1>, 1268 <&dmamux1 108 0x400 0x1>; 1269 dma-names = "ch1", "up", "trig", "com"; 1270 access-controllers = <&etzpc 26>; 1271 status = "disabled"; 1272 1273 pwm { 1274 compatible = "st,stm32-pwm"; 1275 #pwm-cells = <3>; 1276 status = "disabled"; 1277 }; 1278 1279 timer@14 { 1280 compatible = "st,stm32h7-timer-trigger"; 1281 reg = <14>; 1282 status = "disabled"; 1283 }; 1284 }; 1285 1286 timers16: timer@4c00b000 { 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 compatible = "st,stm32-timers"; 1290 reg = <0x4c00b000 0x400>; 1291 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1292 interrupt-names = "global"; 1293 clocks = <&rcc TIM16_K>; 1294 clock-names = "int"; 1295 dmas = <&dmamux1 109 0x400 0x1>, 1296 <&dmamux1 110 0x400 0x1>; 1297 dma-names = "ch1", "up"; 1298 access-controllers = <&etzpc 27>; 1299 status = "disabled"; 1300 1301 pwm { 1302 compatible = "st,stm32-pwm"; 1303 #pwm-cells = <3>; 1304 status = "disabled"; 1305 }; 1306 1307 timer@15 { 1308 compatible = "st,stm32h7-timer-trigger"; 1309 reg = <15>; 1310 status = "disabled"; 1311 }; 1312 }; 1313 1314 timers17: timer@4c00c000 { 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 compatible = "st,stm32-timers"; 1318 reg = <0x4c00c000 0x400>; 1319 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1320 interrupt-names = "global"; 1321 clocks = <&rcc TIM17_K>; 1322 clock-names = "int"; 1323 dmas = <&dmamux1 111 0x400 0x1>, 1324 <&dmamux1 112 0x400 0x1>; 1325 dma-names = "ch1", "up"; 1326 access-controllers = <&etzpc 28>; 1327 status = "disabled"; 1328 1329 pwm { 1330 compatible = "st,stm32-pwm"; 1331 #pwm-cells = <3>; 1332 status = "disabled"; 1333 }; 1334 1335 timer@16 { 1336 compatible = "st,stm32h7-timer-trigger"; 1337 reg = <16>; 1338 status = "disabled"; 1339 }; 1340 }; 1341 1342 lptimer2: timer@50021000 { 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 compatible = "st,stm32-lptimer"; 1346 reg = <0x50021000 0x400>; 1347 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1348 clocks = <&rcc LPTIM2_K>; 1349 clock-names = "mux"; 1350 wakeup-source; 1351 access-controllers = <&etzpc 1>; 1352 status = "disabled"; 1353 1354 pwm { 1355 compatible = "st,stm32-pwm-lp"; 1356 #pwm-cells = <3>; 1357 status = "disabled"; 1358 }; 1359 1360 trigger@1 { 1361 compatible = "st,stm32-lptimer-trigger"; 1362 reg = <1>; 1363 status = "disabled"; 1364 }; 1365 1366 counter { 1367 compatible = "st,stm32-lptimer-counter"; 1368 status = "disabled"; 1369 }; 1370 1371 timer { 1372 compatible = "st,stm32-lptimer-timer"; 1373 status = "disabled"; 1374 }; 1375 }; 1376 1377 lptimer3: timer@50022000 { 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 compatible = "st,stm32-lptimer"; 1381 reg = <0x50022000 0x400>; 1382 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1383 clocks = <&rcc LPTIM3_K>; 1384 clock-names = "mux"; 1385 wakeup-source; 1386 access-controllers = <&etzpc 2>; 1387 status = "disabled"; 1388 1389 pwm { 1390 compatible = "st,stm32-pwm-lp"; 1391 #pwm-cells = <3>; 1392 status = "disabled"; 1393 }; 1394 1395 trigger@2 { 1396 compatible = "st,stm32-lptimer-trigger"; 1397 reg = <2>; 1398 status = "disabled"; 1399 }; 1400 1401 timer { 1402 compatible = "st,stm32-lptimer-timer"; 1403 status = "disabled"; 1404 }; 1405 }; 1406 1407 hash: hash@54003000 { 1408 compatible = "st,stm32mp13-hash"; 1409 reg = <0x54003000 0x400>; 1410 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&rcc HASH1>; 1412 resets = <&rcc HASH1_R>; 1413 dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; 1414 dma-names = "in"; 1415 access-controllers = <&etzpc 41>; 1416 status = "disabled"; 1417 }; 1418 1419 rng: rng@54004000 { 1420 compatible = "st,stm32mp13-rng"; 1421 reg = <0x54004000 0x400>; 1422 clocks = <&rcc RNG1_K>; 1423 resets = <&rcc RNG1_R>; 1424 access-controllers = <&etzpc 40>; 1425 status = "disabled"; 1426 }; 1427 1428 fmc: memory-controller@58002000 { 1429 compatible = "st,stm32mp1-fmc2-ebi"; 1430 reg = <0x58002000 0x1000>; 1431 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1432 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1433 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1434 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1435 <4 0 0x80000000 0x10000000>; /* NAND */ 1436 #address-cells = <2>; 1437 #size-cells = <1>; 1438 clocks = <&rcc FMC_K>; 1439 resets = <&rcc FMC_R>; 1440 access-controllers = <&etzpc 54>; 1441 status = "disabled"; 1442 1443 nand-controller@4,0 { 1444 compatible = "st,stm32mp1-fmc2-nfc"; 1445 reg = <4 0x00000000 0x1000>, 1446 <4 0x08010000 0x1000>, 1447 <4 0x08020000 0x1000>, 1448 <4 0x01000000 0x1000>, 1449 <4 0x09010000 0x1000>, 1450 <4 0x09020000 0x1000>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1454 dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, 1455 <&mdma 24 0x2 0x12000a08 0x0 0x0>, 1456 <&mdma 25 0x2 0x12000a0a 0x0 0x0>; 1457 dma-names = "tx", "rx", "ecc"; 1458 status = "disabled"; 1459 }; 1460 }; 1461 1462 qspi: spi@58003000 { 1463 compatible = "st,stm32f469-qspi"; 1464 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1465 reg-names = "qspi", "qspi_mm"; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1469 dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, 1470 <&mdma 26 0x2 0x10100008 0x0 0x0>; 1471 dma-names = "tx", "rx"; 1472 clocks = <&rcc QSPI_K>; 1473 resets = <&rcc QSPI_R>; 1474 access-controllers = <&etzpc 55>; 1475 status = "disabled"; 1476 }; 1477 1478 sdmmc1: mmc@58005000 { 1479 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1480 arm,primecell-periphid = <0x20253180>; 1481 reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 1482 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1483 clocks = <&rcc SDMMC1_K>; 1484 clock-names = "apb_pclk"; 1485 resets = <&rcc SDMMC1_R>; 1486 cap-sd-highspeed; 1487 cap-mmc-highspeed; 1488 max-frequency = <130000000>; 1489 access-controllers = <&etzpc 50>; 1490 status = "disabled"; 1491 }; 1492 1493 sdmmc2: mmc@58007000 { 1494 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1495 arm,primecell-periphid = <0x20253180>; 1496 reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 1497 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1498 clocks = <&rcc SDMMC2_K>; 1499 clock-names = "apb_pclk"; 1500 resets = <&rcc SDMMC2_R>; 1501 cap-sd-highspeed; 1502 cap-mmc-highspeed; 1503 max-frequency = <130000000>; 1504 access-controllers = <&etzpc 51>; 1505 status = "disabled"; 1506 }; 1507 1508 usbphyc: usbphyc@5a006000 { 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 #clock-cells = <0>; 1512 compatible = "st,stm32mp1-usbphyc"; 1513 reg = <0x5a006000 0x1000>; 1514 clocks = <&rcc USBPHY_K>; 1515 resets = <&rcc USBPHY_R>; 1516 vdda1v1-supply = <&scmi_reg11>; 1517 vdda1v8-supply = <&scmi_reg18>; 1518 access-controllers = <&etzpc 5>; 1519 status = "disabled"; 1520 1521 usbphyc_port0: usb-phy@0 { 1522 #phy-cells = <0>; 1523 reg = <0>; 1524 }; 1525 1526 usbphyc_port1: usb-phy@1 { 1527 #phy-cells = <1>; 1528 reg = <1>; 1529 }; 1530 }; 1531 }; 1532 1533 /* 1534 * Break node order to solve dependency probe issue between 1535 * pinctrl and exti. 1536 */ 1537 pinctrl: pinctrl@50002000 { 1538 #address-cells = <1>; 1539 #size-cells = <1>; 1540 compatible = "st,stm32mp135-pinctrl"; 1541 ranges = <0 0x50002000 0x8400>; 1542 interrupt-parent = <&exti>; 1543 st,syscfg = <&exti 0x60 0xff>; 1544 1545 gpioa: gpio@50002000 { 1546 gpio-controller; 1547 #gpio-cells = <2>; 1548 interrupt-controller; 1549 #interrupt-cells = <2>; 1550 reg = <0x0 0x400>; 1551 clocks = <&rcc GPIOA>; 1552 st,bank-name = "GPIOA"; 1553 ngpios = <16>; 1554 gpio-ranges = <&pinctrl 0 0 16>; 1555 }; 1556 1557 gpiob: gpio@50003000 { 1558 gpio-controller; 1559 #gpio-cells = <2>; 1560 interrupt-controller; 1561 #interrupt-cells = <2>; 1562 reg = <0x1000 0x400>; 1563 clocks = <&rcc GPIOB>; 1564 st,bank-name = "GPIOB"; 1565 ngpios = <16>; 1566 gpio-ranges = <&pinctrl 0 16 16>; 1567 }; 1568 1569 gpioc: gpio@50004000 { 1570 gpio-controller; 1571 #gpio-cells = <2>; 1572 interrupt-controller; 1573 #interrupt-cells = <2>; 1574 reg = <0x2000 0x400>; 1575 clocks = <&rcc GPIOC>; 1576 st,bank-name = "GPIOC"; 1577 ngpios = <16>; 1578 gpio-ranges = <&pinctrl 0 32 16>; 1579 }; 1580 1581 gpiod: gpio@50005000 { 1582 gpio-controller; 1583 #gpio-cells = <2>; 1584 interrupt-controller; 1585 #interrupt-cells = <2>; 1586 reg = <0x3000 0x400>; 1587 clocks = <&rcc GPIOD>; 1588 st,bank-name = "GPIOD"; 1589 ngpios = <16>; 1590 gpio-ranges = <&pinctrl 0 48 16>; 1591 }; 1592 1593 gpioe: gpio@50006000 { 1594 gpio-controller; 1595 #gpio-cells = <2>; 1596 interrupt-controller; 1597 #interrupt-cells = <2>; 1598 reg = <0x4000 0x400>; 1599 clocks = <&rcc GPIOE>; 1600 st,bank-name = "GPIOE"; 1601 ngpios = <16>; 1602 gpio-ranges = <&pinctrl 0 64 16>; 1603 }; 1604 1605 gpiof: gpio@50007000 { 1606 gpio-controller; 1607 #gpio-cells = <2>; 1608 interrupt-controller; 1609 #interrupt-cells = <2>; 1610 reg = <0x5000 0x400>; 1611 clocks = <&rcc GPIOF>; 1612 st,bank-name = "GPIOF"; 1613 ngpios = <16>; 1614 gpio-ranges = <&pinctrl 0 80 16>; 1615 }; 1616 1617 gpiog: gpio@50008000 { 1618 gpio-controller; 1619 #gpio-cells = <2>; 1620 interrupt-controller; 1621 #interrupt-cells = <2>; 1622 reg = <0x6000 0x400>; 1623 clocks = <&rcc GPIOG>; 1624 st,bank-name = "GPIOG"; 1625 ngpios = <16>; 1626 gpio-ranges = <&pinctrl 0 96 16>; 1627 }; 1628 1629 gpioh: gpio@50009000 { 1630 gpio-controller; 1631 #gpio-cells = <2>; 1632 interrupt-controller; 1633 #interrupt-cells = <2>; 1634 reg = <0x7000 0x400>; 1635 clocks = <&rcc GPIOH>; 1636 st,bank-name = "GPIOH"; 1637 ngpios = <15>; 1638 gpio-ranges = <&pinctrl 0 112 15>; 1639 }; 1640 1641 gpioi: gpio@5000a000 { 1642 gpio-controller; 1643 #gpio-cells = <2>; 1644 interrupt-controller; 1645 #interrupt-cells = <2>; 1646 reg = <0x8000 0x400>; 1647 clocks = <&rcc GPIOI>; 1648 st,bank-name = "GPIOI"; 1649 ngpios = <8>; 1650 gpio-ranges = <&pinctrl 0 128 8>; 1651 }; 1652 }; 1653 }; 1654}; 1655