1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/reset/stm32mp13-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 device_type = "cpu"; 21 reg = <0>; 22 }; 23 }; 24 25 arm-pmu { 26 compatible = "arm,cortex-a7-pmu"; 27 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 28 interrupt-affinity = <&cpu0>; 29 interrupt-parent = <&intc>; 30 }; 31 32 firmware { 33 optee { 34 method = "smc"; 35 compatible = "linaro,optee-tz"; 36 interrupt-parent = <&intc>; 37 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 38 }; 39 40 scmi: scmi { 41 compatible = "linaro,scmi-optee"; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 linaro,optee-channel-id = <0>; 45 46 scmi_clk: protocol@14 { 47 reg = <0x14>; 48 #clock-cells = <1>; 49 }; 50 51 scmi_reset: protocol@16 { 52 reg = <0x16>; 53 #reset-cells = <1>; 54 }; 55 56 scmi_voltd: protocol@17 { 57 reg = <0x17>; 58 59 scmi_regu: regulators { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 scmi_reg11: regulator@0 { 64 reg = <VOLTD_SCMI_REG11>; 65 regulator-name = "reg11"; 66 }; 67 scmi_reg18: regulator@1 { 68 reg = <VOLTD_SCMI_REG18>; 69 regulator-name = "reg18"; 70 }; 71 scmi_usb33: regulator@2 { 72 reg = <VOLTD_SCMI_USB33>; 73 regulator-name = "usb33"; 74 }; 75 }; 76 }; 77 }; 78 }; 79 80 intc: interrupt-controller@a0021000 { 81 compatible = "arm,cortex-a7-gic"; 82 #interrupt-cells = <3>; 83 interrupt-controller; 84 reg = <0xa0021000 0x1000>, 85 <0xa0022000 0x2000>; 86 }; 87 88 psci { 89 compatible = "arm,psci-1.0"; 90 method = "smc"; 91 }; 92 93 timer { 94 compatible = "arm,armv7-timer"; 95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 99 interrupt-parent = <&intc>; 100 always-on; 101 }; 102 103 thermal-zones { 104 cpu_thermal: cpu-thermal { 105 polling-delay-passive = <0>; 106 polling-delay = <0>; 107 thermal-sensors = <&dts>; 108 109 trips { 110 cpu_alert1: cpu-alert1 { 111 temperature = <85000>; 112 hysteresis = <0>; 113 type = "passive"; 114 }; 115 116 cpu-crit { 117 temperature = <120000>; 118 hysteresis = <0>; 119 type = "critical"; 120 }; 121 }; 122 123 cooling-maps { 124 }; 125 }; 126 }; 127 128 soc { 129 compatible = "simple-bus"; 130 #address-cells = <1>; 131 #size-cells = <1>; 132 interrupt-parent = <&intc>; 133 ranges; 134 135 timers2: timer@40000000 { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 compatible = "st,stm32-timers"; 139 reg = <0x40000000 0x400>; 140 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 141 interrupt-names = "global"; 142 clocks = <&rcc TIM2_K>; 143 clock-names = "int"; 144 dmas = <&dmamux1 18 0x400 0x1>, 145 <&dmamux1 19 0x400 0x1>, 146 <&dmamux1 20 0x400 0x1>, 147 <&dmamux1 21 0x400 0x1>, 148 <&dmamux1 22 0x400 0x1>; 149 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 150 status = "disabled"; 151 152 pwm { 153 compatible = "st,stm32-pwm"; 154 #pwm-cells = <3>; 155 status = "disabled"; 156 }; 157 158 timer@1 { 159 compatible = "st,stm32h7-timer-trigger"; 160 reg = <1>; 161 status = "disabled"; 162 }; 163 164 counter { 165 compatible = "st,stm32-timer-counter"; 166 status = "disabled"; 167 }; 168 }; 169 170 timers3: timer@40001000 { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 compatible = "st,stm32-timers"; 174 reg = <0x40001000 0x400>; 175 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "global"; 177 clocks = <&rcc TIM3_K>; 178 clock-names = "int"; 179 dmas = <&dmamux1 23 0x400 0x1>, 180 <&dmamux1 24 0x400 0x1>, 181 <&dmamux1 25 0x400 0x1>, 182 <&dmamux1 26 0x400 0x1>, 183 <&dmamux1 27 0x400 0x1>, 184 <&dmamux1 28 0x400 0x1>; 185 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 186 status = "disabled"; 187 188 pwm { 189 compatible = "st,stm32-pwm"; 190 #pwm-cells = <3>; 191 status = "disabled"; 192 }; 193 194 timer@2 { 195 compatible = "st,stm32h7-timer-trigger"; 196 reg = <2>; 197 status = "disabled"; 198 }; 199 200 counter { 201 compatible = "st,stm32-timer-counter"; 202 status = "disabled"; 203 }; 204 }; 205 206 timers4: timer@40002000 { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 compatible = "st,stm32-timers"; 210 reg = <0x40002000 0x400>; 211 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "global"; 213 clocks = <&rcc TIM4_K>; 214 clock-names = "int"; 215 dmas = <&dmamux1 29 0x400 0x1>, 216 <&dmamux1 30 0x400 0x1>, 217 <&dmamux1 31 0x400 0x1>, 218 <&dmamux1 32 0x400 0x1>; 219 dma-names = "ch1", "ch2", "ch3", "up"; 220 status = "disabled"; 221 222 pwm { 223 compatible = "st,stm32-pwm"; 224 #pwm-cells = <3>; 225 status = "disabled"; 226 }; 227 228 timer@3 { 229 compatible = "st,stm32h7-timer-trigger"; 230 reg = <3>; 231 status = "disabled"; 232 }; 233 234 counter { 235 compatible = "st,stm32-timer-counter"; 236 status = "disabled"; 237 }; 238 }; 239 240 timers5: timer@40003000 { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 compatible = "st,stm32-timers"; 244 reg = <0x40003000 0x400>; 245 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 246 interrupt-names = "global"; 247 clocks = <&rcc TIM5_K>; 248 clock-names = "int"; 249 dmas = <&dmamux1 55 0x400 0x1>, 250 <&dmamux1 56 0x400 0x1>, 251 <&dmamux1 57 0x400 0x1>, 252 <&dmamux1 58 0x400 0x1>, 253 <&dmamux1 59 0x400 0x1>, 254 <&dmamux1 60 0x400 0x1>; 255 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 256 status = "disabled"; 257 258 pwm { 259 compatible = "st,stm32-pwm"; 260 #pwm-cells = <3>; 261 status = "disabled"; 262 }; 263 264 timer@4 { 265 compatible = "st,stm32h7-timer-trigger"; 266 reg = <4>; 267 status = "disabled"; 268 }; 269 270 counter { 271 compatible = "st,stm32-timer-counter"; 272 status = "disabled"; 273 }; 274 }; 275 276 timers6: timer@40004000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "st,stm32-timers"; 280 reg = <0x40004000 0x400>; 281 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 282 interrupt-names = "global"; 283 clocks = <&rcc TIM6_K>; 284 clock-names = "int"; 285 dmas = <&dmamux1 69 0x400 0x1>; 286 dma-names = "up"; 287 status = "disabled"; 288 289 counter { 290 compatible = "st,stm32-timer-counter"; 291 status = "disabled"; 292 }; 293 294 timer@5 { 295 compatible = "st,stm32h7-timer-trigger"; 296 reg = <5>; 297 status = "disabled"; 298 }; 299 }; 300 301 timers7: timer@40005000 { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 compatible = "st,stm32-timers"; 305 reg = <0x40005000 0x400>; 306 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-names = "global"; 308 clocks = <&rcc TIM7_K>; 309 clock-names = "int"; 310 dmas = <&dmamux1 70 0x400 0x1>; 311 dma-names = "up"; 312 status = "disabled"; 313 314 counter { 315 compatible = "st,stm32-timer-counter"; 316 status = "disabled"; 317 }; 318 319 timer@6 { 320 compatible = "st,stm32h7-timer-trigger"; 321 reg = <6>; 322 status = "disabled"; 323 }; 324 }; 325 326 lptimer1: timer@40009000 { 327 #address-cells = <1>; 328 #size-cells = <0>; 329 compatible = "st,stm32-lptimer"; 330 reg = <0x40009000 0x400>; 331 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&rcc LPTIM1_K>; 333 clock-names = "mux"; 334 wakeup-source; 335 status = "disabled"; 336 337 pwm { 338 compatible = "st,stm32-pwm-lp"; 339 #pwm-cells = <3>; 340 status = "disabled"; 341 }; 342 343 trigger@0 { 344 compatible = "st,stm32-lptimer-trigger"; 345 reg = <0>; 346 status = "disabled"; 347 }; 348 349 counter { 350 compatible = "st,stm32-lptimer-counter"; 351 status = "disabled"; 352 }; 353 354 timer { 355 compatible = "st,stm32-lptimer-timer"; 356 status = "disabled"; 357 }; 358 }; 359 360 i2s2: audio-controller@4000b000 { 361 compatible = "st,stm32h7-i2s"; 362 reg = <0x4000b000 0x400>; 363 #sound-dai-cells = <0>; 364 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 365 dmas = <&dmamux1 39 0x400 0x01>, 366 <&dmamux1 40 0x400 0x01>; 367 dma-names = "rx", "tx"; 368 status = "disabled"; 369 }; 370 371 spi2: spi@4000b000 { 372 compatible = "st,stm32h7-spi"; 373 reg = <0x4000b000 0x400>; 374 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&rcc SPI2_K>; 376 resets = <&rcc SPI2_R>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 dmas = <&dmamux1 39 0x400 0x01>, 380 <&dmamux1 40 0x400 0x01>; 381 dma-names = "rx", "tx"; 382 status = "disabled"; 383 }; 384 385 i2s3: audio-controller@4000c000 { 386 compatible = "st,stm32h7-i2s"; 387 reg = <0x4000c000 0x400>; 388 #sound-dai-cells = <0>; 389 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 390 dmas = <&dmamux1 61 0x400 0x01>, 391 <&dmamux1 62 0x400 0x01>; 392 dma-names = "rx", "tx"; 393 status = "disabled"; 394 }; 395 396 spi3: spi@4000c000 { 397 compatible = "st,stm32h7-spi"; 398 reg = <0x4000c000 0x400>; 399 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&rcc SPI3_K>; 401 resets = <&rcc SPI3_R>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 dmas = <&dmamux1 61 0x400 0x01>, 405 <&dmamux1 62 0x400 0x01>; 406 dma-names = "rx", "tx"; 407 status = "disabled"; 408 }; 409 410 spdifrx: audio-controller@4000d000 { 411 compatible = "st,stm32h7-spdifrx"; 412 reg = <0x4000d000 0x400>; 413 #sound-dai-cells = <0>; 414 clocks = <&rcc SPDIF_K>; 415 clock-names = "kclk"; 416 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 417 dmas = <&dmamux1 93 0x400 0x01>, 418 <&dmamux1 94 0x400 0x01>; 419 dma-names = "rx", "rx-ctrl"; 420 status = "disabled"; 421 }; 422 423 usart3: serial@4000f000 { 424 compatible = "st,stm32h7-uart"; 425 reg = <0x4000f000 0x400>; 426 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&rcc USART3_K>; 428 resets = <&rcc USART3_R>; 429 wakeup-source; 430 dmas = <&dmamux1 45 0x400 0x5>, 431 <&dmamux1 46 0x400 0x1>; 432 dma-names = "rx", "tx"; 433 status = "disabled"; 434 }; 435 436 uart4: serial@40010000 { 437 compatible = "st,stm32h7-uart"; 438 reg = <0x40010000 0x400>; 439 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&rcc UART4_K>; 441 resets = <&rcc UART4_R>; 442 wakeup-source; 443 dmas = <&dmamux1 63 0x400 0x5>, 444 <&dmamux1 64 0x400 0x1>; 445 dma-names = "rx", "tx"; 446 status = "disabled"; 447 }; 448 449 uart5: serial@40011000 { 450 compatible = "st,stm32h7-uart"; 451 reg = <0x40011000 0x400>; 452 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&rcc UART5_K>; 454 resets = <&rcc UART5_R>; 455 wakeup-source; 456 dmas = <&dmamux1 65 0x400 0x5>, 457 <&dmamux1 66 0x400 0x1>; 458 dma-names = "rx", "tx"; 459 status = "disabled"; 460 }; 461 462 i2c1: i2c@40012000 { 463 compatible = "st,stm32mp13-i2c"; 464 reg = <0x40012000 0x400>; 465 interrupt-names = "event", "error"; 466 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&rcc I2C1_K>; 469 resets = <&rcc I2C1_R>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 dmas = <&dmamux1 33 0x400 0x1>, 473 <&dmamux1 34 0x400 0x1>; 474 dma-names = "rx", "tx"; 475 st,syscfg-fmp = <&syscfg 0x4 0x1>; 476 i2c-analog-filter; 477 status = "disabled"; 478 }; 479 480 i2c2: i2c@40013000 { 481 compatible = "st,stm32mp13-i2c"; 482 reg = <0x40013000 0x400>; 483 interrupt-names = "event", "error"; 484 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&rcc I2C2_K>; 487 resets = <&rcc I2C2_R>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 dmas = <&dmamux1 35 0x400 0x1>, 491 <&dmamux1 36 0x400 0x1>; 492 dma-names = "rx", "tx"; 493 st,syscfg-fmp = <&syscfg 0x4 0x2>; 494 i2c-analog-filter; 495 status = "disabled"; 496 }; 497 498 uart7: serial@40018000 { 499 compatible = "st,stm32h7-uart"; 500 reg = <0x40018000 0x400>; 501 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&rcc UART7_K>; 503 resets = <&rcc UART7_R>; 504 wakeup-source; 505 dmas = <&dmamux1 79 0x400 0x5>, 506 <&dmamux1 80 0x400 0x1>; 507 dma-names = "rx", "tx"; 508 status = "disabled"; 509 }; 510 511 uart8: serial@40019000 { 512 compatible = "st,stm32h7-uart"; 513 reg = <0x40019000 0x400>; 514 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&rcc UART8_K>; 516 resets = <&rcc UART8_R>; 517 wakeup-source; 518 dmas = <&dmamux1 81 0x400 0x5>, 519 <&dmamux1 82 0x400 0x1>; 520 dma-names = "rx", "tx"; 521 status = "disabled"; 522 }; 523 524 timers1: timer@44000000 { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 compatible = "st,stm32-timers"; 528 reg = <0x44000000 0x400>; 529 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 533 interrupt-names = "brk", "up", "trg-com", "cc"; 534 clocks = <&rcc TIM1_K>; 535 clock-names = "int"; 536 dmas = <&dmamux1 11 0x400 0x1>, 537 <&dmamux1 12 0x400 0x1>, 538 <&dmamux1 13 0x400 0x1>, 539 <&dmamux1 14 0x400 0x1>, 540 <&dmamux1 15 0x400 0x1>, 541 <&dmamux1 16 0x400 0x1>, 542 <&dmamux1 17 0x400 0x1>; 543 dma-names = "ch1", "ch2", "ch3", "ch4", 544 "up", "trig", "com"; 545 status = "disabled"; 546 547 pwm { 548 compatible = "st,stm32-pwm"; 549 #pwm-cells = <3>; 550 status = "disabled"; 551 }; 552 553 timer@0 { 554 compatible = "st,stm32h7-timer-trigger"; 555 reg = <0>; 556 status = "disabled"; 557 }; 558 559 counter { 560 compatible = "st,stm32-timer-counter"; 561 status = "disabled"; 562 }; 563 }; 564 565 timers8: timer@44001000 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 compatible = "st,stm32-timers"; 569 reg = <0x44001000 0x400>; 570 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "brk", "up", "trg-com", "cc"; 575 clocks = <&rcc TIM8_K>; 576 clock-names = "int"; 577 dmas = <&dmamux1 47 0x400 0x1>, 578 <&dmamux1 48 0x400 0x1>, 579 <&dmamux1 49 0x400 0x1>, 580 <&dmamux1 50 0x400 0x1>, 581 <&dmamux1 51 0x400 0x1>, 582 <&dmamux1 52 0x400 0x1>, 583 <&dmamux1 53 0x400 0x1>; 584 dma-names = "ch1", "ch2", "ch3", "ch4", 585 "up", "trig", "com"; 586 status = "disabled"; 587 588 pwm { 589 compatible = "st,stm32-pwm"; 590 #pwm-cells = <3>; 591 status = "disabled"; 592 }; 593 594 timer@7 { 595 compatible = "st,stm32h7-timer-trigger"; 596 reg = <7>; 597 status = "disabled"; 598 }; 599 600 counter { 601 compatible = "st,stm32-timer-counter"; 602 status = "disabled"; 603 }; 604 }; 605 606 usart6: serial@44003000 { 607 compatible = "st,stm32h7-uart"; 608 reg = <0x44003000 0x400>; 609 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&rcc USART6_K>; 611 resets = <&rcc USART6_R>; 612 wakeup-source; 613 dmas = <&dmamux1 71 0x400 0x5>, 614 <&dmamux1 72 0x400 0x1>; 615 dma-names = "rx", "tx"; 616 status = "disabled"; 617 }; 618 619 i2s1: audio-controller@44004000 { 620 compatible = "st,stm32h7-i2s"; 621 reg = <0x44004000 0x400>; 622 #sound-dai-cells = <0>; 623 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 624 dmas = <&dmamux1 37 0x400 0x01>, 625 <&dmamux1 38 0x400 0x01>; 626 dma-names = "rx", "tx"; 627 status = "disabled"; 628 }; 629 630 spi1: spi@44004000 { 631 compatible = "st,stm32h7-spi"; 632 reg = <0x44004000 0x400>; 633 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&rcc SPI1_K>; 635 resets = <&rcc SPI1_R>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 dmas = <&dmamux1 37 0x400 0x01>, 639 <&dmamux1 38 0x400 0x01>; 640 dma-names = "rx", "tx"; 641 status = "disabled"; 642 }; 643 644 sai1: sai@4400a000 { 645 compatible = "st,stm32h7-sai"; 646 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 647 ranges = <0 0x4400a000 0x400>; 648 #address-cells = <1>; 649 #size-cells = <1>; 650 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 651 resets = <&rcc SAI1_R>; 652 status = "disabled"; 653 654 sai1a: audio-controller@4400a004 { 655 compatible = "st,stm32-sai-sub-a"; 656 reg = <0x4 0x20>; 657 #sound-dai-cells = <0>; 658 clocks = <&rcc SAI1_K>; 659 clock-names = "sai_ck"; 660 dmas = <&dmamux1 87 0x400 0x01>; 661 status = "disabled"; 662 }; 663 664 sai1b: audio-controller@4400a024 { 665 compatible = "st,stm32-sai-sub-b"; 666 reg = <0x24 0x20>; 667 #sound-dai-cells = <0>; 668 clocks = <&rcc SAI1_K>; 669 clock-names = "sai_ck"; 670 dmas = <&dmamux1 88 0x400 0x01>; 671 status = "disabled"; 672 }; 673 }; 674 675 sai2: sai@4400b000 { 676 compatible = "st,stm32h7-sai"; 677 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 678 ranges = <0 0x4400b000 0x400>; 679 #address-cells = <1>; 680 #size-cells = <1>; 681 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 682 resets = <&rcc SAI2_R>; 683 status = "disabled"; 684 685 sai2a: audio-controller@4400b004 { 686 compatible = "st,stm32-sai-sub-a"; 687 reg = <0x4 0x20>; 688 #sound-dai-cells = <0>; 689 clocks = <&rcc SAI2_K>; 690 clock-names = "sai_ck"; 691 dmas = <&dmamux1 89 0x400 0x01>; 692 status = "disabled"; 693 }; 694 695 sai2b: audio-controller@4400b024 { 696 compatible = "st,stm32-sai-sub-b"; 697 reg = <0x24 0x20>; 698 #sound-dai-cells = <0>; 699 clocks = <&rcc SAI2_K>; 700 clock-names = "sai_ck"; 701 dmas = <&dmamux1 90 0x400 0x01>; 702 status = "disabled"; 703 }; 704 }; 705 706 dfsdm: dfsdm@4400d000 { 707 compatible = "st,stm32mp1-dfsdm"; 708 reg = <0x4400d000 0x800>; 709 clocks = <&rcc DFSDM_K>; 710 clock-names = "dfsdm"; 711 #address-cells = <1>; 712 #size-cells = <0>; 713 status = "disabled"; 714 715 dfsdm0: filter@0 { 716 compatible = "st,stm32-dfsdm-adc"; 717 reg = <0>; 718 #io-channel-cells = <1>; 719 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 720 dmas = <&dmamux1 101 0x400 0x01>; 721 dma-names = "rx"; 722 status = "disabled"; 723 }; 724 725 dfsdm1: filter@1 { 726 compatible = "st,stm32-dfsdm-adc"; 727 reg = <1>; 728 #io-channel-cells = <1>; 729 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 730 dmas = <&dmamux1 102 0x400 0x01>; 731 dma-names = "rx"; 732 status = "disabled"; 733 }; 734 }; 735 736 dma1: dma-controller@48000000 { 737 compatible = "st,stm32-dma"; 738 reg = <0x48000000 0x400>; 739 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&rcc DMA1>; 748 resets = <&rcc DMA1_R>; 749 #dma-cells = <4>; 750 st,mem2mem; 751 dma-requests = <8>; 752 }; 753 754 dma2: dma-controller@48001000 { 755 compatible = "st,stm32-dma"; 756 reg = <0x48001000 0x400>; 757 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&rcc DMA2>; 766 resets = <&rcc DMA2_R>; 767 #dma-cells = <4>; 768 st,mem2mem; 769 dma-requests = <8>; 770 }; 771 772 dmamux1: dma-router@48002000 { 773 compatible = "st,stm32h7-dmamux"; 774 reg = <0x48002000 0x40>; 775 clocks = <&rcc DMAMUX1>; 776 resets = <&rcc DMAMUX1_R>; 777 #dma-cells = <3>; 778 dma-masters = <&dma1 &dma2>; 779 dma-requests = <128>; 780 dma-channels = <16>; 781 }; 782 783 rcc: rcc@50000000 { 784 compatible = "st,stm32mp13-rcc", "syscon"; 785 reg = <0x50000000 0x1000>; 786 #clock-cells = <1>; 787 #reset-cells = <1>; 788 clock-names = "hse", "hsi", "csi", "lse", "lsi"; 789 clocks = <&scmi_clk CK_SCMI_HSE>, 790 <&scmi_clk CK_SCMI_HSI>, 791 <&scmi_clk CK_SCMI_CSI>, 792 <&scmi_clk CK_SCMI_LSE>, 793 <&scmi_clk CK_SCMI_LSI>; 794 }; 795 796 pwr_regulators: pwr@50001000 { 797 compatible = "st,stm32mp1,pwr-reg"; 798 reg = <0x50001000 0x10>; 799 status = "disabled"; 800 801 reg11: reg11 { 802 regulator-name = "reg11"; 803 regulator-min-microvolt = <1100000>; 804 regulator-max-microvolt = <1100000>; 805 }; 806 807 reg18: reg18 { 808 regulator-name = "reg18"; 809 regulator-min-microvolt = <1800000>; 810 regulator-max-microvolt = <1800000>; 811 }; 812 813 usb33: usb33 { 814 regulator-name = "usb33"; 815 regulator-min-microvolt = <3300000>; 816 regulator-max-microvolt = <3300000>; 817 }; 818 }; 819 820 exti: interrupt-controller@5000d000 { 821 compatible = "st,stm32mp1-exti", "syscon"; 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 reg = <0x5000d000 0x400>; 825 interrupts-extended = 826 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 827 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 828 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 829 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 830 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 831 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 832 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 833 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 834 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 835 <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 836 <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 837 <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 838 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 839 <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 840 <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 841 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 842 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 843 <0>, 844 <0>, 845 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 846 <0>, /* EXTI_20 */ 847 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 848 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 849 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 850 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 851 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 852 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 853 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 854 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 855 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 856 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 857 <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 858 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 859 <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 860 <0>, 861 <0>, 862 <0>, 863 <0>, 864 <0>, 865 <0>, 866 <0>, /* EXTI_40 */ 867 <0>, 868 <0>, 869 <0>, 870 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 871 <0>, 872 <0>, 873 <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 874 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 875 <0>, 876 <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 877 <0>, 878 <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 879 <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 880 <0>, 881 <0>, 882 <0>, 883 <0>, 884 <0>, 885 <0>, 886 <0>, /* EXTI_60 */ 887 <0>, 888 <0>, 889 <0>, 890 <0>, 891 <0>, 892 <0>, 893 <0>, 894 <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 895 <0>, 896 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 897 }; 898 899 syscfg: syscon@50020000 { 900 compatible = "st,stm32mp157-syscfg", "syscon"; 901 reg = <0x50020000 0x400>; 902 clocks = <&rcc SYSCFG>; 903 }; 904 905 lptimer4: timer@50023000 { 906 compatible = "st,stm32-lptimer"; 907 reg = <0x50023000 0x400>; 908 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&rcc LPTIM4_K>; 910 clock-names = "mux"; 911 wakeup-source; 912 status = "disabled"; 913 914 pwm { 915 compatible = "st,stm32-pwm-lp"; 916 #pwm-cells = <3>; 917 status = "disabled"; 918 }; 919 920 timer { 921 compatible = "st,stm32-lptimer-timer"; 922 status = "disabled"; 923 }; 924 }; 925 926 lptimer5: timer@50024000 { 927 compatible = "st,stm32-lptimer"; 928 reg = <0x50024000 0x400>; 929 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&rcc LPTIM5_K>; 931 clock-names = "mux"; 932 wakeup-source; 933 status = "disabled"; 934 935 pwm { 936 compatible = "st,stm32-pwm-lp"; 937 #pwm-cells = <3>; 938 status = "disabled"; 939 }; 940 941 timer { 942 compatible = "st,stm32-lptimer-timer"; 943 status = "disabled"; 944 }; 945 }; 946 947 dts: thermal@50028000 { 948 compatible = "st,stm32-thermal"; 949 reg = <0x50028000 0x100>; 950 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&rcc DTS>; 952 clock-names = "pclk"; 953 #thermal-sensor-cells = <0>; 954 status = "disabled"; 955 }; 956 957 hdp: pinctrl@5002a000 { 958 compatible = "st,stm32mp131-hdp"; 959 reg = <0x5002a000 0x400>; 960 clocks = <&rcc HDP>; 961 status = "disabled"; 962 }; 963 964 mdma: dma-controller@58000000 { 965 compatible = "st,stm32h7-mdma"; 966 reg = <0x58000000 0x1000>; 967 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&rcc MDMA>; 969 #dma-cells = <5>; 970 dma-channels = <32>; 971 dma-requests = <48>; 972 }; 973 974 crc1: crc@58009000 { 975 compatible = "st,stm32f7-crc"; 976 reg = <0x58009000 0x400>; 977 clocks = <&rcc CRC1>; 978 status = "disabled"; 979 }; 980 981 usbh_ohci: usb@5800c000 { 982 compatible = "generic-ohci"; 983 reg = <0x5800c000 0x1000>; 984 clocks = <&usbphyc>, <&rcc USBH>; 985 resets = <&rcc USBH_R>; 986 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 987 status = "disabled"; 988 }; 989 990 usbh_ehci: usb@5800d000 { 991 compatible = "generic-ehci"; 992 reg = <0x5800d000 0x1000>; 993 clocks = <&usbphyc>, <&rcc USBH>; 994 resets = <&rcc USBH_R>; 995 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 996 companion = <&usbh_ohci>; 997 status = "disabled"; 998 }; 999 1000 iwdg2: watchdog@5a002000 { 1001 compatible = "st,stm32mp1-iwdg"; 1002 reg = <0x5a002000 0x400>; 1003 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; 1004 clock-names = "pclk", "lsi"; 1005 status = "disabled"; 1006 }; 1007 1008 rtc: rtc@5c004000 { 1009 compatible = "st,stm32mp1-rtc"; 1010 reg = <0x5c004000 0x400>; 1011 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&scmi_clk CK_SCMI_RTCAPB>, 1013 <&scmi_clk CK_SCMI_RTC>; 1014 clock-names = "pclk", "rtc_ck"; 1015 status = "disabled"; 1016 }; 1017 1018 bsec: efuse@5c005000 { 1019 compatible = "st,stm32mp13-bsec"; 1020 reg = <0x5c005000 0x400>; 1021 #address-cells = <1>; 1022 #size-cells = <1>; 1023 1024 part_number_otp: part_number_otp@4 { 1025 reg = <0x4 0x2>; 1026 bits = <0 12>; 1027 }; 1028 vrefint: vrefin-cal@52 { 1029 reg = <0x52 0x2>; 1030 }; 1031 ts_cal1: calib@5c { 1032 reg = <0x5c 0x2>; 1033 }; 1034 ts_cal2: calib@5e { 1035 reg = <0x5e 0x2>; 1036 }; 1037 ethernet_mac1_address: mac1@e4 { 1038 reg = <0xe4 0x6>; 1039 }; 1040 ethernet_mac2_address: mac2@ea { 1041 reg = <0xea 0x6>; 1042 }; 1043 }; 1044 1045 etzpc: bus@5c007000 { 1046 compatible = "st,stm32-etzpc", "simple-bus"; 1047 reg = <0x5c007000 0x400>; 1048 #address-cells = <1>; 1049 #size-cells = <1>; 1050 #access-controller-cells = <1>; 1051 ranges; 1052 1053 adc_2: adc@48004000 { 1054 compatible = "st,stm32mp13-adc-core"; 1055 reg = <0x48004000 0x400>; 1056 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1057 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 1058 clock-names = "bus", "adc"; 1059 interrupt-controller; 1060 #interrupt-cells = <1>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 access-controllers = <&etzpc 33>; 1064 status = "disabled"; 1065 1066 adc2: adc@0 { 1067 compatible = "st,stm32mp13-adc"; 1068 #io-channel-cells = <1>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 reg = <0x0>; 1072 interrupt-parent = <&adc_2>; 1073 interrupts = <0>; 1074 dmas = <&dmamux1 10 0x400 0x80000001>; 1075 dma-names = "rx"; 1076 nvmem-cells = <&vrefint>; 1077 nvmem-cell-names = "vrefint"; 1078 status = "disabled"; 1079 1080 channel@13 { 1081 reg = <13>; 1082 label = "vrefint"; 1083 }; 1084 channel@14 { 1085 reg = <14>; 1086 label = "vddcore"; 1087 }; 1088 channel@16 { 1089 reg = <16>; 1090 label = "vddcpu"; 1091 }; 1092 channel@17 { 1093 reg = <17>; 1094 label = "vddq_ddr"; 1095 }; 1096 }; 1097 }; 1098 1099 usbotg_hs: usb@49000000 { 1100 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1101 reg = <0x49000000 0x40000>; 1102 clocks = <&rcc USBO_K>; 1103 clock-names = "otg"; 1104 resets = <&rcc USBO_R>; 1105 reset-names = "dwc2"; 1106 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1107 g-rx-fifo-size = <512>; 1108 g-np-tx-fifo-size = <32>; 1109 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1110 dr_mode = "otg"; 1111 otg-rev = <0x200>; 1112 usb33d-supply = <&scmi_usb33>; 1113 access-controllers = <&etzpc 34>; 1114 status = "disabled"; 1115 }; 1116 1117 usart1: serial@4c000000 { 1118 compatible = "st,stm32h7-uart"; 1119 reg = <0x4c000000 0x400>; 1120 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&rcc USART1_K>; 1122 resets = <&rcc USART1_R>; 1123 wakeup-source; 1124 dmas = <&dmamux1 41 0x400 0x5>, 1125 <&dmamux1 42 0x400 0x1>; 1126 dma-names = "rx", "tx"; 1127 access-controllers = <&etzpc 16>; 1128 status = "disabled"; 1129 }; 1130 1131 usart2: serial@4c001000 { 1132 compatible = "st,stm32h7-uart"; 1133 reg = <0x4c001000 0x400>; 1134 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&rcc USART2_K>; 1136 resets = <&rcc USART2_R>; 1137 wakeup-source; 1138 dmas = <&dmamux1 43 0x400 0x5>, 1139 <&dmamux1 44 0x400 0x1>; 1140 dma-names = "rx", "tx"; 1141 access-controllers = <&etzpc 17>; 1142 status = "disabled"; 1143 }; 1144 1145 i2s4: audio-controller@4c002000 { 1146 compatible = "st,stm32h7-i2s"; 1147 reg = <0x4c002000 0x400>; 1148 #sound-dai-cells = <0>; 1149 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1150 dmas = <&dmamux1 83 0x400 0x01>, 1151 <&dmamux1 84 0x400 0x01>; 1152 dma-names = "rx", "tx"; 1153 access-controllers = <&etzpc 13>; 1154 status = "disabled"; 1155 }; 1156 1157 spi4: spi@4c002000 { 1158 compatible = "st,stm32h7-spi"; 1159 reg = <0x4c002000 0x400>; 1160 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&rcc SPI4_K>; 1162 resets = <&rcc SPI4_R>; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 dmas = <&dmamux1 83 0x400 0x01>, 1166 <&dmamux1 84 0x400 0x01>; 1167 dma-names = "rx", "tx"; 1168 access-controllers = <&etzpc 18>; 1169 status = "disabled"; 1170 }; 1171 1172 spi5: spi@4c003000 { 1173 compatible = "st,stm32h7-spi"; 1174 reg = <0x4c003000 0x400>; 1175 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&rcc SPI5_K>; 1177 resets = <&rcc SPI5_R>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 dmas = <&dmamux1 85 0x400 0x01>, 1181 <&dmamux1 86 0x400 0x01>; 1182 dma-names = "rx", "tx"; 1183 access-controllers = <&etzpc 19>; 1184 status = "disabled"; 1185 }; 1186 1187 i2c3: i2c@4c004000 { 1188 compatible = "st,stm32mp13-i2c"; 1189 reg = <0x4c004000 0x400>; 1190 interrupt-names = "event", "error"; 1191 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&rcc I2C3_K>; 1194 resets = <&rcc I2C3_R>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 dmas = <&dmamux1 73 0x400 0x1>, 1198 <&dmamux1 74 0x400 0x1>; 1199 dma-names = "rx", "tx"; 1200 st,syscfg-fmp = <&syscfg 0x4 0x4>; 1201 i2c-analog-filter; 1202 access-controllers = <&etzpc 20>; 1203 status = "disabled"; 1204 }; 1205 1206 i2c4: i2c@4c005000 { 1207 compatible = "st,stm32mp13-i2c"; 1208 reg = <0x4c005000 0x400>; 1209 interrupt-names = "event", "error"; 1210 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&rcc I2C4_K>; 1213 resets = <&rcc I2C4_R>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 dmas = <&dmamux1 75 0x400 0x1>, 1217 <&dmamux1 76 0x400 0x1>; 1218 dma-names = "rx", "tx"; 1219 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1220 i2c-analog-filter; 1221 access-controllers = <&etzpc 21>; 1222 status = "disabled"; 1223 }; 1224 1225 i2c5: i2c@4c006000 { 1226 compatible = "st,stm32mp13-i2c"; 1227 reg = <0x4c006000 0x400>; 1228 interrupt-names = "event", "error"; 1229 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&rcc I2C5_K>; 1232 resets = <&rcc I2C5_R>; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 dmas = <&dmamux1 115 0x400 0x1>, 1236 <&dmamux1 116 0x400 0x1>; 1237 dma-names = "rx", "tx"; 1238 st,syscfg-fmp = <&syscfg 0x4 0x10>; 1239 i2c-analog-filter; 1240 access-controllers = <&etzpc 22>; 1241 status = "disabled"; 1242 }; 1243 1244 timers12: timer@4c007000 { 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 compatible = "st,stm32-timers"; 1248 reg = <0x4c007000 0x400>; 1249 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1250 interrupt-names = "global"; 1251 clocks = <&rcc TIM12_K>; 1252 clock-names = "int"; 1253 access-controllers = <&etzpc 23>; 1254 status = "disabled"; 1255 1256 counter { 1257 compatible = "st,stm32-timer-counter"; 1258 status = "disabled"; 1259 }; 1260 1261 pwm { 1262 compatible = "st,stm32-pwm"; 1263 #pwm-cells = <3>; 1264 status = "disabled"; 1265 }; 1266 1267 timer@11 { 1268 compatible = "st,stm32h7-timer-trigger"; 1269 reg = <11>; 1270 status = "disabled"; 1271 }; 1272 }; 1273 1274 timers13: timer@4c008000 { 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 compatible = "st,stm32-timers"; 1278 reg = <0x4c008000 0x400>; 1279 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1280 interrupt-names = "global"; 1281 clocks = <&rcc TIM13_K>; 1282 clock-names = "int"; 1283 access-controllers = <&etzpc 24>; 1284 status = "disabled"; 1285 1286 counter { 1287 compatible = "st,stm32-timer-counter"; 1288 status = "disabled"; 1289 }; 1290 1291 pwm { 1292 compatible = "st,stm32-pwm"; 1293 #pwm-cells = <3>; 1294 status = "disabled"; 1295 }; 1296 1297 timer@12 { 1298 compatible = "st,stm32h7-timer-trigger"; 1299 reg = <12>; 1300 status = "disabled"; 1301 }; 1302 }; 1303 1304 timers14: timer@4c009000 { 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 compatible = "st,stm32-timers"; 1308 reg = <0x4c009000 0x400>; 1309 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1310 interrupt-names = "global"; 1311 clocks = <&rcc TIM14_K>; 1312 clock-names = "int"; 1313 access-controllers = <&etzpc 25>; 1314 status = "disabled"; 1315 1316 counter { 1317 compatible = "st,stm32-timer-counter"; 1318 status = "disabled"; 1319 }; 1320 1321 pwm { 1322 compatible = "st,stm32-pwm"; 1323 #pwm-cells = <3>; 1324 status = "disabled"; 1325 }; 1326 1327 timer@13 { 1328 compatible = "st,stm32h7-timer-trigger"; 1329 reg = <13>; 1330 status = "disabled"; 1331 }; 1332 }; 1333 1334 timers15: timer@4c00a000 { 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 compatible = "st,stm32-timers"; 1338 reg = <0x4c00a000 0x400>; 1339 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1340 interrupt-names = "global"; 1341 clocks = <&rcc TIM15_K>; 1342 clock-names = "int"; 1343 dmas = <&dmamux1 105 0x400 0x1>, 1344 <&dmamux1 106 0x400 0x1>, 1345 <&dmamux1 107 0x400 0x1>, 1346 <&dmamux1 108 0x400 0x1>; 1347 dma-names = "ch1", "up", "trig", "com"; 1348 access-controllers = <&etzpc 26>; 1349 status = "disabled"; 1350 1351 counter { 1352 compatible = "st,stm32-timer-counter"; 1353 status = "disabled"; 1354 }; 1355 1356 pwm { 1357 compatible = "st,stm32-pwm"; 1358 #pwm-cells = <3>; 1359 status = "disabled"; 1360 }; 1361 1362 timer@14 { 1363 compatible = "st,stm32h7-timer-trigger"; 1364 reg = <14>; 1365 status = "disabled"; 1366 }; 1367 }; 1368 1369 timers16: timer@4c00b000 { 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 compatible = "st,stm32-timers"; 1373 reg = <0x4c00b000 0x400>; 1374 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1375 interrupt-names = "global"; 1376 clocks = <&rcc TIM16_K>; 1377 clock-names = "int"; 1378 dmas = <&dmamux1 109 0x400 0x1>, 1379 <&dmamux1 110 0x400 0x1>; 1380 dma-names = "ch1", "up"; 1381 access-controllers = <&etzpc 27>; 1382 status = "disabled"; 1383 1384 counter { 1385 compatible = "st,stm32-timer-counter"; 1386 status = "disabled"; 1387 }; 1388 1389 pwm { 1390 compatible = "st,stm32-pwm"; 1391 #pwm-cells = <3>; 1392 status = "disabled"; 1393 }; 1394 1395 timer@15 { 1396 compatible = "st,stm32h7-timer-trigger"; 1397 reg = <15>; 1398 status = "disabled"; 1399 }; 1400 }; 1401 1402 timers17: timer@4c00c000 { 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 compatible = "st,stm32-timers"; 1406 reg = <0x4c00c000 0x400>; 1407 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1408 interrupt-names = "global"; 1409 clocks = <&rcc TIM17_K>; 1410 clock-names = "int"; 1411 dmas = <&dmamux1 111 0x400 0x1>, 1412 <&dmamux1 112 0x400 0x1>; 1413 dma-names = "ch1", "up"; 1414 access-controllers = <&etzpc 28>; 1415 status = "disabled"; 1416 1417 counter { 1418 compatible = "st,stm32-timer-counter"; 1419 status = "disabled"; 1420 }; 1421 1422 pwm { 1423 compatible = "st,stm32-pwm"; 1424 #pwm-cells = <3>; 1425 status = "disabled"; 1426 }; 1427 1428 timer@16 { 1429 compatible = "st,stm32h7-timer-trigger"; 1430 reg = <16>; 1431 status = "disabled"; 1432 }; 1433 }; 1434 1435 lptimer2: timer@50021000 { 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 compatible = "st,stm32-lptimer"; 1439 reg = <0x50021000 0x400>; 1440 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1441 clocks = <&rcc LPTIM2_K>; 1442 clock-names = "mux"; 1443 wakeup-source; 1444 access-controllers = <&etzpc 1>; 1445 status = "disabled"; 1446 1447 pwm { 1448 compatible = "st,stm32-pwm-lp"; 1449 #pwm-cells = <3>; 1450 status = "disabled"; 1451 }; 1452 1453 trigger@1 { 1454 compatible = "st,stm32-lptimer-trigger"; 1455 reg = <1>; 1456 status = "disabled"; 1457 }; 1458 1459 counter { 1460 compatible = "st,stm32-lptimer-counter"; 1461 status = "disabled"; 1462 }; 1463 1464 timer { 1465 compatible = "st,stm32-lptimer-timer"; 1466 status = "disabled"; 1467 }; 1468 }; 1469 1470 lptimer3: timer@50022000 { 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 compatible = "st,stm32-lptimer"; 1474 reg = <0x50022000 0x400>; 1475 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1476 clocks = <&rcc LPTIM3_K>; 1477 clock-names = "mux"; 1478 wakeup-source; 1479 access-controllers = <&etzpc 2>; 1480 status = "disabled"; 1481 1482 pwm { 1483 compatible = "st,stm32-pwm-lp"; 1484 #pwm-cells = <3>; 1485 status = "disabled"; 1486 }; 1487 1488 trigger@2 { 1489 compatible = "st,stm32-lptimer-trigger"; 1490 reg = <2>; 1491 status = "disabled"; 1492 }; 1493 1494 timer { 1495 compatible = "st,stm32-lptimer-timer"; 1496 status = "disabled"; 1497 }; 1498 }; 1499 1500 hash: hash@54003000 { 1501 compatible = "st,stm32mp13-hash"; 1502 reg = <0x54003000 0x400>; 1503 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1504 clocks = <&rcc HASH1>; 1505 resets = <&rcc HASH1_R>; 1506 dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; 1507 dma-names = "in"; 1508 access-controllers = <&etzpc 41>; 1509 status = "disabled"; 1510 }; 1511 1512 rng: rng@54004000 { 1513 compatible = "st,stm32mp13-rng"; 1514 reg = <0x54004000 0x400>; 1515 clocks = <&rcc RNG1_K>; 1516 resets = <&rcc RNG1_R>; 1517 access-controllers = <&etzpc 40>; 1518 status = "disabled"; 1519 }; 1520 1521 fmc: memory-controller@58002000 { 1522 compatible = "st,stm32mp1-fmc2-ebi"; 1523 reg = <0x58002000 0x1000>; 1524 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1525 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1526 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1527 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1528 <4 0 0x80000000 0x10000000>; /* NAND */ 1529 #address-cells = <2>; 1530 #size-cells = <1>; 1531 clocks = <&rcc FMC_K>; 1532 resets = <&rcc FMC_R>; 1533 access-controllers = <&etzpc 54>; 1534 status = "disabled"; 1535 1536 nand-controller@4,0 { 1537 compatible = "st,stm32mp1-fmc2-nfc"; 1538 reg = <4 0x00000000 0x1000>, 1539 <4 0x08010000 0x1000>, 1540 <4 0x08020000 0x1000>, 1541 <4 0x01000000 0x1000>, 1542 <4 0x09010000 0x1000>, 1543 <4 0x09020000 0x1000>; 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1547 dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, 1548 <&mdma 24 0x2 0x12000a08 0x0 0x0>, 1549 <&mdma 25 0x2 0x12000a0a 0x0 0x0>; 1550 dma-names = "tx", "rx", "ecc"; 1551 status = "disabled"; 1552 }; 1553 }; 1554 1555 qspi: spi@58003000 { 1556 compatible = "st,stm32f469-qspi"; 1557 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1558 reg-names = "qspi", "qspi_mm"; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1562 dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, 1563 <&mdma 26 0x2 0x10100008 0x0 0x0>; 1564 dma-names = "tx", "rx"; 1565 clocks = <&rcc QSPI_K>; 1566 resets = <&rcc QSPI_R>; 1567 access-controllers = <&etzpc 55>; 1568 status = "disabled"; 1569 }; 1570 1571 sdmmc1: mmc@58005000 { 1572 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1573 arm,primecell-periphid = <0x20253180>; 1574 reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 1575 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1576 clocks = <&rcc SDMMC1_K>; 1577 clock-names = "apb_pclk"; 1578 resets = <&rcc SDMMC1_R>; 1579 cap-sd-highspeed; 1580 cap-mmc-highspeed; 1581 max-frequency = <130000000>; 1582 access-controllers = <&etzpc 50>; 1583 status = "disabled"; 1584 }; 1585 1586 sdmmc2: mmc@58007000 { 1587 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1588 arm,primecell-periphid = <0x20253180>; 1589 reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 1590 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1591 clocks = <&rcc SDMMC2_K>; 1592 clock-names = "apb_pclk"; 1593 resets = <&rcc SDMMC2_R>; 1594 cap-sd-highspeed; 1595 cap-mmc-highspeed; 1596 max-frequency = <130000000>; 1597 access-controllers = <&etzpc 51>; 1598 status = "disabled"; 1599 }; 1600 1601 ethernet1: ethernet@5800a000 { 1602 compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; 1603 reg = <0x5800a000 0x2000>; 1604 reg-names = "stmmaceth"; 1605 interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1606 <&exti 68 1>; 1607 interrupt-names = "macirq", "eth_wake_irq"; 1608 clock-names = "stmmaceth", 1609 "mac-clk-tx", 1610 "mac-clk-rx", 1611 "ethstp", 1612 "ptp_ref", 1613 "eth-ck"; 1614 clocks = <&rcc ETH1MAC>, 1615 <&rcc ETH1TX>, 1616 <&rcc ETH1RX>, 1617 <&rcc ETH1STP>, 1618 <&rcc ETH1PTP_K>, 1619 <&rcc ETH1CK_K>; 1620 st,syscon = <&syscfg 0x4 0xff0000>; 1621 snps,mixed-burst; 1622 snps,pbl = <2>; 1623 snps,axi-config = <&stmmac_axi_config_1>; 1624 snps,tso; 1625 access-controllers = <&etzpc 48>; 1626 nvmem-cells = <ðernet_mac1_address>; 1627 nvmem-cell-names = "mac-address"; 1628 status = "disabled"; 1629 1630 stmmac_axi_config_1: stmmac-axi-config { 1631 snps,blen = <0 0 0 0 16 8 4>; 1632 snps,rd_osr_lmt = <0x7>; 1633 snps,wr_osr_lmt = <0x7>; 1634 }; 1635 }; 1636 1637 usbphyc: usbphyc@5a006000 { 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 #clock-cells = <0>; 1641 compatible = "st,stm32mp1-usbphyc"; 1642 reg = <0x5a006000 0x1000>; 1643 clocks = <&rcc USBPHY_K>; 1644 resets = <&rcc USBPHY_R>; 1645 vdda1v1-supply = <&scmi_reg11>; 1646 vdda1v8-supply = <&scmi_reg18>; 1647 access-controllers = <&etzpc 5>; 1648 status = "disabled"; 1649 1650 usbphyc_port0: usb-phy@0 { 1651 #phy-cells = <0>; 1652 reg = <0>; 1653 }; 1654 1655 usbphyc_port1: usb-phy@1 { 1656 #phy-cells = <1>; 1657 reg = <1>; 1658 }; 1659 }; 1660 }; 1661 1662 /* 1663 * Break node order to solve dependency probe issue between 1664 * pinctrl and exti. 1665 */ 1666 pinctrl: pinctrl@50002000 { 1667 #address-cells = <1>; 1668 #size-cells = <1>; 1669 compatible = "st,stm32mp135-pinctrl"; 1670 ranges = <0 0x50002000 0x8400>; 1671 interrupt-parent = <&exti>; 1672 st,syscfg = <&exti 0x60 0xff>; 1673 1674 gpioa: gpio@50002000 { 1675 gpio-controller; 1676 #gpio-cells = <2>; 1677 interrupt-controller; 1678 #interrupt-cells = <2>; 1679 reg = <0x0 0x400>; 1680 clocks = <&rcc GPIOA>; 1681 st,bank-name = "GPIOA"; 1682 ngpios = <16>; 1683 gpio-ranges = <&pinctrl 0 0 16>; 1684 }; 1685 1686 gpiob: gpio@50003000 { 1687 gpio-controller; 1688 #gpio-cells = <2>; 1689 interrupt-controller; 1690 #interrupt-cells = <2>; 1691 reg = <0x1000 0x400>; 1692 clocks = <&rcc GPIOB>; 1693 st,bank-name = "GPIOB"; 1694 ngpios = <16>; 1695 gpio-ranges = <&pinctrl 0 16 16>; 1696 }; 1697 1698 gpioc: gpio@50004000 { 1699 gpio-controller; 1700 #gpio-cells = <2>; 1701 interrupt-controller; 1702 #interrupt-cells = <2>; 1703 reg = <0x2000 0x400>; 1704 clocks = <&rcc GPIOC>; 1705 st,bank-name = "GPIOC"; 1706 ngpios = <16>; 1707 gpio-ranges = <&pinctrl 0 32 16>; 1708 }; 1709 1710 gpiod: gpio@50005000 { 1711 gpio-controller; 1712 #gpio-cells = <2>; 1713 interrupt-controller; 1714 #interrupt-cells = <2>; 1715 reg = <0x3000 0x400>; 1716 clocks = <&rcc GPIOD>; 1717 st,bank-name = "GPIOD"; 1718 ngpios = <16>; 1719 gpio-ranges = <&pinctrl 0 48 16>; 1720 }; 1721 1722 gpioe: gpio@50006000 { 1723 gpio-controller; 1724 #gpio-cells = <2>; 1725 interrupt-controller; 1726 #interrupt-cells = <2>; 1727 reg = <0x4000 0x400>; 1728 clocks = <&rcc GPIOE>; 1729 st,bank-name = "GPIOE"; 1730 ngpios = <16>; 1731 gpio-ranges = <&pinctrl 0 64 16>; 1732 }; 1733 1734 gpiof: gpio@50007000 { 1735 gpio-controller; 1736 #gpio-cells = <2>; 1737 interrupt-controller; 1738 #interrupt-cells = <2>; 1739 reg = <0x5000 0x400>; 1740 clocks = <&rcc GPIOF>; 1741 st,bank-name = "GPIOF"; 1742 ngpios = <16>; 1743 gpio-ranges = <&pinctrl 0 80 16>; 1744 }; 1745 1746 gpiog: gpio@50008000 { 1747 gpio-controller; 1748 #gpio-cells = <2>; 1749 interrupt-controller; 1750 #interrupt-cells = <2>; 1751 reg = <0x6000 0x400>; 1752 clocks = <&rcc GPIOG>; 1753 st,bank-name = "GPIOG"; 1754 ngpios = <16>; 1755 gpio-ranges = <&pinctrl 0 96 16>; 1756 }; 1757 1758 gpioh: gpio@50009000 { 1759 gpio-controller; 1760 #gpio-cells = <2>; 1761 interrupt-controller; 1762 #interrupt-cells = <2>; 1763 reg = <0x7000 0x400>; 1764 clocks = <&rcc GPIOH>; 1765 st,bank-name = "GPIOH"; 1766 ngpios = <15>; 1767 gpio-ranges = <&pinctrl 0 112 15>; 1768 }; 1769 1770 gpioi: gpio@5000a000 { 1771 gpio-controller; 1772 #gpio-cells = <2>; 1773 interrupt-controller; 1774 #interrupt-cells = <2>; 1775 reg = <0x8000 0x400>; 1776 clocks = <&rcc GPIOI>; 1777 st,bank-name = "GPIOI"; 1778 ngpios = <8>; 1779 gpio-ranges = <&pinctrl 0 128 8>; 1780 }; 1781 }; 1782 }; 1783}; 1784