1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> 5 */ 6#include <dt-bindings/pinctrl/stm32-pinfunc.h> 7 8&pinctrl { 9 /omit-if-no-ref/ 10 adc1_pins_a: adc1-pins-0 { 11 pins { 12 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ 13 }; 14 }; 15 16 /omit-if-no-ref/ 17 adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { 18 pins { 19 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 20 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ 21 }; 22 }; 23 24 /omit-if-no-ref/ 25 adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { 26 pins { 27 pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */ 28 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */ 29 }; 30 }; 31 32 /omit-if-no-ref/ 33 dcmipp_pins_a: dcmi-0 { 34 pins1 { 35 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ 36 <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */ 37 <STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */ 38 <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ 39 <STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */ 40 <STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */ 41 <STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */ 42 <STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */ 43 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ 44 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ 45 <STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */ 46 bias-disable; 47 }; 48 }; 49 50 /omit-if-no-ref/ 51 dcmipp_sleep_pins_a: dcmi-sleep-0 { 52 pins1 { 53 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ 54 <STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */ 55 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */ 56 <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ 57 <STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */ 58 <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */ 59 <STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */ 60 <STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */ 61 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ 62 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ 63 <STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */ 64 }; 65 }; 66 67 /omit-if-no-ref/ 68 eth1_rgmii_pins_a: eth1-rgmii-0 { 69 pins1 { 70 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 71 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 72 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 73 <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */ 74 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 75 <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */ 76 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ 77 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ 78 bias-disable; 79 drive-push-pull; 80 slew-rate = <2>; 81 }; 82 83 pins2 { 84 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 85 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 86 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ 87 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 88 <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */ 89 <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */ 90 bias-disable; 91 }; 92 }; 93 94 /omit-if-no-ref/ 95 eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { 96 pins1 { 97 pinmux = <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ 98 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ 99 bias-disable; 100 drive-push-pull; 101 slew-rate = <2>; 102 }; 103 104 pins2 { 105 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 106 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 107 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 108 <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */ 109 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 110 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 111 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 112 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 113 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */ 114 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */ 115 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */ 116 <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */ 117 }; 118 }; 119 120 /omit-if-no-ref/ 121 eth1_rmii_pins_a: eth1-rmii-0 { 122 pins1 { 123 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */ 124 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */ 125 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */ 126 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */ 127 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ 128 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ 129 bias-disable; 130 drive-push-pull; 131 slew-rate = <1>; 132 }; 133 134 pins2 { 135 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */ 136 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */ 137 <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */ 138 bias-disable; 139 }; 140 }; 141 142 /omit-if-no-ref/ 143 eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { 144 pins1 { 145 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */ 146 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */ 147 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */ 148 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */ 149 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 150 <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */ 151 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */ 152 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */ 153 <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */ 154 }; 155 }; 156 157 /omit-if-no-ref/ 158 eth2_rgmii_pins_a: eth2-rgmii-0 { 159 pins1 { 160 pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */ 161 <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */ 162 <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */ 163 <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */ 164 <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */ 165 <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */ 166 <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */ 167 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ 168 bias-disable; 169 drive-push-pull; 170 slew-rate = <2>; 171 }; 172 173 pins2 { 174 pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */ 175 <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */ 176 <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */ 177 <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */ 178 <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */ 179 <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */ 180 bias-disable; 181 }; 182 }; 183 184 /omit-if-no-ref/ 185 eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { 186 pins1 { 187 pinmux = <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */ 188 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ 189 bias-disable; 190 drive-push-pull; 191 slew-rate = <2>; 192 }; 193 194 pins2 { 195 pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ 196 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */ 197 <STM32_PINMUX('G', 1, ANALOG)>, /* ETH_RGMII_TXD2 */ 198 <STM32_PINMUX('E', 6, ANALOG)>, /* ETH_RGMII_TXD3 */ 199 <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_TX_CTL */ 200 <STM32_PINMUX('G', 3, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 201 <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 202 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ 203 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 204 <STM32_PINMUX('A', 8, ANALOG)>, /* ETH_RGMII_RXD3 */ 205 <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */ 206 <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */ 207 }; 208 }; 209 210 /omit-if-no-ref/ 211 eth2_rmii_pins_a: eth2-rmii-0 { 212 pins1 { 213 pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */ 214 <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */ 215 <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */ 216 <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */ 217 <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */ 218 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ 219 bias-disable; 220 drive-push-pull; 221 slew-rate = <1>; 222 }; 223 224 pins2 { 225 pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */ 226 <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */ 227 <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */ 228 bias-disable; 229 }; 230 }; 231 232 /omit-if-no-ref/ 233 eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { 234 pins1 { 235 pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */ 236 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */ 237 <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */ 238 <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */ 239 <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */ 240 <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */ 241 <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */ 242 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */ 243 <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */ 244 }; 245 }; 246 247 /omit-if-no-ref/ 248 goodix_pins_a: goodix-0 { 249 /* 250 * touchscreen reset needs to be configured 251 * via the pinctrl not the driver (a pull-down resistor 252 * has been soldered onto the reset line which forces 253 * the touchscreen to reset state). 254 */ 255 pins1 { 256 pinmux = <STM32_PINMUX('H', 2, GPIO)>; 257 output-high; 258 bias-pull-up; 259 }; 260 /* 261 * Interrupt line must have a pull-down resistor 262 * in order to freeze the i2c address at 0x5D 263 */ 264 pins2 { 265 pinmux = <STM32_PINMUX('F', 5, GPIO)>; 266 bias-pull-down; 267 }; 268 }; 269 270 /omit-if-no-ref/ 271 i2c1_pins_a: i2c1-0 { 272 pins { 273 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ 274 <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */ 275 bias-disable; 276 drive-open-drain; 277 slew-rate = <0>; 278 }; 279 }; 280 281 /omit-if-no-ref/ 282 i2c1_sleep_pins_a: i2c1-sleep-0 { 283 pins { 284 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ 285 <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */ 286 }; 287 }; 288 289 /omit-if-no-ref/ 290 i2c5_pins_a: i2c5-0 { 291 pins { 292 pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ 293 <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */ 294 bias-disable; 295 drive-open-drain; 296 slew-rate = <0>; 297 }; 298 }; 299 300 /omit-if-no-ref/ 301 i2c5_sleep_pins_a: i2c5-sleep-0 { 302 pins { 303 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ 304 <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */ 305 }; 306 }; 307 308 /omit-if-no-ref/ 309 i2c5_pins_b: i2c5-1 { 310 pins { 311 pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ 312 <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */ 313 bias-disable; 314 drive-open-drain; 315 slew-rate = <0>; 316 }; 317 }; 318 319 /omit-if-no-ref/ 320 i2c5_sleep_pins_b: i2c5-sleep-1 { 321 pins { 322 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ 323 <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */ 324 }; 325 }; 326 327 /omit-if-no-ref/ 328 ltdc_pins_a: ltdc-0 { 329 pins { 330 pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */ 331 <STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */ 332 <STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */ 333 <STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */ 334 <STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */ 335 <STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */ 336 <STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */ 337 <STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */ 338 <STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */ 339 <STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */ 340 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 341 <STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */ 342 <STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */ 343 <STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */ 344 <STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */ 345 <STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */ 346 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */ 347 <STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */ 348 <STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */ 349 <STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */ 350 <STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */ 351 <STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */ 352 bias-disable; 353 drive-push-pull; 354 slew-rate = <0>; 355 }; 356 }; 357 358 /omit-if-no-ref/ 359 ltdc_sleep_pins_a: ltdc-sleep-0 { 360 pins { 361 pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */ 362 <STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */ 363 <STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */ 364 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */ 365 <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */ 366 <STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */ 367 <STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */ 368 <STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */ 369 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */ 370 <STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */ 371 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 372 <STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */ 373 <STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */ 374 <STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */ 375 <STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */ 376 <STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */ 377 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */ 378 <STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */ 379 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */ 380 <STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */ 381 <STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */ 382 <STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */ 383 }; 384 }; 385 386 /omit-if-no-ref/ 387 m_can1_pins_a: m-can1-0 { 388 pins1 { 389 pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */ 390 slew-rate = <1>; 391 drive-push-pull; 392 bias-disable; 393 }; 394 pins2 { 395 pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ 396 bias-disable; 397 }; 398 }; 399 400 /omit-if-no-ref/ 401 m_can1_sleep_pins_a: m_can1-sleep-0 { 402 pins { 403 pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */ 404 <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */ 405 }; 406 }; 407 408 /omit-if-no-ref/ 409 m_can2_pins_a: m-can2-0 { 410 pins1 { 411 pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */ 412 slew-rate = <1>; 413 drive-push-pull; 414 bias-disable; 415 }; 416 pins2 { 417 pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */ 418 bias-disable; 419 }; 420 }; 421 422 /omit-if-no-ref/ 423 m_can2_sleep_pins_a: m_can2-sleep-0 { 424 pins { 425 pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */ 426 <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */ 427 }; 428 }; 429 430 /omit-if-no-ref/ 431 mcp23017_pins_a: mcp23017-0 { 432 pins { 433 pinmux = <STM32_PINMUX('G', 12, GPIO)>; 434 bias-pull-up; 435 }; 436 }; 437 438 /omit-if-no-ref/ 439 pwm3_pins_a: pwm3-0 { 440 pins { 441 pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */ 442 bias-pull-down; 443 drive-push-pull; 444 slew-rate = <0>; 445 }; 446 }; 447 448 /omit-if-no-ref/ 449 pwm3_sleep_pins_a: pwm3-sleep-0 { 450 pins { 451 pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */ 452 }; 453 }; 454 455 /omit-if-no-ref/ 456 pwm4_pins_a: pwm4-0 { 457 pins { 458 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ 459 bias-pull-down; 460 drive-push-pull; 461 slew-rate = <0>; 462 }; 463 }; 464 465 /omit-if-no-ref/ 466 pwm4_sleep_pins_a: pwm4-sleep-0 { 467 pins { 468 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ 469 }; 470 }; 471 472 /omit-if-no-ref/ 473 pwm5_pins_a: pwm5-0 { 474 pins { 475 pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */ 476 bias-pull-down; 477 drive-push-pull; 478 slew-rate = <0>; 479 }; 480 }; 481 482 /omit-if-no-ref/ 483 pwm5_sleep_pins_a: pwm5-sleep-0 { 484 pins { 485 pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */ 486 }; 487 }; 488 489 /omit-if-no-ref/ 490 pwm8_pins_a: pwm8-0 { 491 pins { 492 pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */ 493 bias-pull-down; 494 drive-push-pull; 495 slew-rate = <0>; 496 }; 497 }; 498 499 /omit-if-no-ref/ 500 pwm8_sleep_pins_a: pwm8-sleep-0 { 501 pins { 502 pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */ 503 }; 504 }; 505 506 /omit-if-no-ref/ 507 pwm13_pins_a: pwm13-0 { 508 pins { 509 pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */ 510 bias-pull-down; 511 drive-push-pull; 512 slew-rate = <0>; 513 }; 514 }; 515 516 /omit-if-no-ref/ 517 pwm13_sleep_pins_a: pwm13-sleep-0 { 518 pins { 519 pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */ 520 }; 521 }; 522 523 /omit-if-no-ref/ 524 pwm14_pins_a: pwm14-0 { 525 pins { 526 pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */ 527 bias-pull-down; 528 drive-push-pull; 529 slew-rate = <0>; 530 }; 531 }; 532 533 /omit-if-no-ref/ 534 pwm14_sleep_pins_a: pwm14-sleep-0 { 535 pins { 536 pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */ 537 }; 538 }; 539 540 /omit-if-no-ref/ 541 qspi_clk_pins_a: qspi-clk-0 { 542 pins { 543 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ 544 bias-disable; 545 drive-push-pull; 546 slew-rate = <3>; 547 }; 548 }; 549 550 /omit-if-no-ref/ 551 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { 552 pins { 553 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ 554 }; 555 }; 556 557 /omit-if-no-ref/ 558 qspi_bk1_pins_a: qspi-bk1-0 { 559 pins { 560 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 561 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 562 <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */ 563 <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */ 564 bias-disable; 565 drive-push-pull; 566 slew-rate = <1>; 567 }; 568 }; 569 570 /omit-if-no-ref/ 571 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { 572 pins { 573 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ 574 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ 575 <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */ 576 <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */ 577 }; 578 }; 579 580 /omit-if-no-ref/ 581 qspi_cs1_pins_a: qspi-cs1-0 { 582 pins { 583 pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */ 584 bias-pull-up; 585 drive-push-pull; 586 slew-rate = <1>; 587 }; 588 }; 589 590 /omit-if-no-ref/ 591 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { 592 pins { 593 pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */ 594 }; 595 }; 596 597 /omit-if-no-ref/ 598 sai1a_pins_a: sai1a-0 { 599 pins { 600 pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */ 601 <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */ 602 <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */ 603 slew-rate = <0>; 604 drive-push-pull; 605 bias-disable; 606 }; 607 }; 608 609 /omit-if-no-ref/ 610 sai1a_sleep_pins_a: sai1a-sleep-0 { 611 pins { 612 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */ 613 <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */ 614 <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */ 615 }; 616 }; 617 618 /omit-if-no-ref/ 619 sai1b_pins_a: sai1b-0 { 620 pins { 621 pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */ 622 bias-disable; 623 }; 624 }; 625 626 /omit-if-no-ref/ 627 sai1b_sleep_pins_a: sai1b-sleep-0 { 628 pins { 629 pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */ 630 }; 631 }; 632 633 /omit-if-no-ref/ 634 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 635 pins { 636 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 637 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 638 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 639 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 640 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 641 slew-rate = <1>; 642 drive-push-pull; 643 bias-disable; 644 }; 645 }; 646 647 /omit-if-no-ref/ 648 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { 649 pins1 { 650 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 651 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 652 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 653 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 654 slew-rate = <1>; 655 drive-push-pull; 656 bias-disable; 657 }; 658 pins2 { 659 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 660 slew-rate = <1>; 661 drive-open-drain; 662 bias-disable; 663 }; 664 }; 665 666 /omit-if-no-ref/ 667 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { 668 pins { 669 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 670 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 671 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ 672 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 673 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 674 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 675 }; 676 }; 677 678 /omit-if-no-ref/ 679 sdmmc1_clk_pins_a: sdmmc1-clk-0 { 680 pins { 681 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 682 slew-rate = <1>; 683 drive-push-pull; 684 bias-disable; 685 }; 686 }; 687 688 /omit-if-no-ref/ 689 sdmmc2_b4_pins_a: sdmmc2-b4-0 { 690 pins { 691 pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ 692 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ 693 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ 694 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */ 695 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 696 slew-rate = <1>; 697 drive-push-pull; 698 bias-pull-up; 699 }; 700 }; 701 702 /omit-if-no-ref/ 703 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { 704 pins1 { 705 pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ 706 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ 707 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ 708 <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */ 709 slew-rate = <1>; 710 drive-push-pull; 711 bias-pull-up; 712 }; 713 pins2 { 714 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 715 slew-rate = <1>; 716 drive-open-drain; 717 bias-pull-up; 718 }; 719 }; 720 721 /omit-if-no-ref/ 722 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { 723 pins { 724 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ 725 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ 726 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ 727 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ 728 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ 729 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ 730 }; 731 }; 732 733 /omit-if-no-ref/ 734 sdmmc2_clk_pins_a: sdmmc2-clk-0 { 735 pins { 736 pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ 737 slew-rate = <1>; 738 drive-push-pull; 739 bias-pull-up; 740 }; 741 }; 742 743 /omit-if-no-ref/ 744 sdmmc2_d47_pins_a: sdmmc2-d47-0 { 745 pins { 746 pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */ 747 <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */ 748 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 749 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 750 slew-rate = <1>; 751 drive-push-pull; 752 bias-pull-up; 753 }; 754 }; 755 756 /omit-if-no-ref/ 757 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { 758 pins { 759 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */ 760 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */ 761 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 762 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 763 }; 764 }; 765 766 /omit-if-no-ref/ 767 spi2_pins_a: spi2-0 { 768 pins1 { 769 pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */ 770 <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */ 771 bias-disable; 772 drive-push-pull; 773 slew-rate = <1>; 774 }; 775 776 pins2 { 777 pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */ 778 bias-disable; 779 }; 780 }; 781 782 /omit-if-no-ref/ 783 spi2_sleep_pins_a: spi2-sleep-0 { 784 pins { 785 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */ 786 <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */ 787 <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */ 788 }; 789 }; 790 791 /omit-if-no-ref/ 792 spi3_pins_a: spi3-0 { 793 pins1 { 794 pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */ 795 <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */ 796 bias-disable; 797 drive-push-pull; 798 slew-rate = <1>; 799 }; 800 801 pins2 { 802 pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */ 803 bias-disable; 804 }; 805 }; 806 807 /omit-if-no-ref/ 808 spi3_sleep_pins_a: spi3-sleep-0 { 809 pins { 810 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */ 811 <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */ 812 <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */ 813 }; 814 }; 815 816 /omit-if-no-ref/ 817 spi5_pins_a: spi5-0 { 818 pins1 { 819 pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ 820 <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */ 821 bias-disable; 822 drive-push-pull; 823 slew-rate = <1>; 824 }; 825 826 pins2 { 827 pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */ 828 bias-disable; 829 }; 830 }; 831 832 /omit-if-no-ref/ 833 spi5_sleep_pins_a: spi5-sleep-0 { 834 pins { 835 pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */ 836 <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */ 837 <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */ 838 }; 839 }; 840 841 /omit-if-no-ref/ 842 stm32g0_intn_pins_a: stm32g0-intn-0 { 843 pins { 844 pinmux = <STM32_PINMUX('I', 2, GPIO)>; 845 bias-pull-up; 846 }; 847 }; 848 849 /omit-if-no-ref/ 850 uart4_pins_a: uart4-0 { 851 pins1 { 852 pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ 853 bias-disable; 854 drive-push-pull; 855 slew-rate = <0>; 856 }; 857 pins2 { 858 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ 859 bias-disable; 860 }; 861 }; 862 863 /omit-if-no-ref/ 864 uart4_idle_pins_a: uart4-idle-0 { 865 pins1 { 866 pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */ 867 }; 868 pins2 { 869 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ 870 bias-disable; 871 }; 872 }; 873 874 /omit-if-no-ref/ 875 uart4_sleep_pins_a: uart4-sleep-0 { 876 pins { 877 pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */ 878 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ 879 }; 880 }; 881 882 /omit-if-no-ref/ 883 uart4_pins_b: uart4-1 { 884 pins1 { 885 pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */ 886 bias-disable; 887 drive-push-pull; 888 slew-rate = <0>; 889 }; 890 pins2 { 891 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ 892 bias-pull-up; 893 }; 894 }; 895 896 /omit-if-no-ref/ 897 uart4_idle_pins_b: uart4-idle-1 { 898 pins1 { 899 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */ 900 }; 901 pins2 { 902 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ 903 bias-pull-up; 904 }; 905 }; 906 907 /omit-if-no-ref/ 908 uart4_sleep_pins_b: uart4-sleep-1 { 909 pins { 910 pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */ 911 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ 912 }; 913 }; 914 915 /omit-if-no-ref/ 916 uart7_pins_a: uart7-0 { 917 pins1 { 918 pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */ 919 <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ 920 bias-disable; 921 drive-push-pull; 922 slew-rate = <0>; 923 }; 924 pins2 { 925 pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */ 926 <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */ 927 bias-disable; 928 }; 929 }; 930 931 /omit-if-no-ref/ 932 uart7_idle_pins_a: uart7-idle-0 { 933 pins1 { 934 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ 935 <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ 936 }; 937 pins2 { 938 pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ 939 bias-disable; 940 drive-push-pull; 941 slew-rate = <0>; 942 }; 943 pins3 { 944 pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ 945 bias-disable; 946 }; 947 }; 948 949 /omit-if-no-ref/ 950 uart7_sleep_pins_a: uart7-sleep-0 { 951 pins { 952 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ 953 <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */ 954 <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */ 955 <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ 956 }; 957 }; 958 959 /omit-if-no-ref/ 960 uart8_pins_a: uart8-0 { 961 pins1 { 962 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ 963 bias-disable; 964 drive-push-pull; 965 slew-rate = <0>; 966 }; 967 pins2 { 968 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ 969 bias-pull-up; 970 }; 971 }; 972 973 /omit-if-no-ref/ 974 uart8_idle_pins_a: uart8-idle-0 { 975 pins1 { 976 pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */ 977 }; 978 pins2 { 979 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ 980 bias-pull-up; 981 }; 982 }; 983 984 /omit-if-no-ref/ 985 uart8_sleep_pins_a: uart8-sleep-0 { 986 pins { 987 pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */ 988 <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */ 989 }; 990 }; 991 992 /omit-if-no-ref/ 993 usart1_pins_a: usart1-0 { 994 pins1 { 995 pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */ 996 <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ 997 bias-disable; 998 drive-push-pull; 999 slew-rate = <0>; 1000 }; 1001 pins2 { 1002 pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */ 1003 <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */ 1004 bias-pull-up; 1005 }; 1006 }; 1007 1008 /omit-if-no-ref/ 1009 usart1_idle_pins_a: usart1-idle-0 { 1010 pins1 { 1011 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ 1012 <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */ 1013 }; 1014 pins2 { 1015 pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ 1016 bias-disable; 1017 drive-push-pull; 1018 slew-rate = <0>; 1019 }; 1020 pins3 { 1021 pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */ 1022 bias-pull-up; 1023 }; 1024 }; 1025 1026 /omit-if-no-ref/ 1027 usart1_sleep_pins_a: usart1-sleep-0 { 1028 pins { 1029 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ 1030 <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */ 1031 <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */ 1032 <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */ 1033 }; 1034 }; 1035 1036 /omit-if-no-ref/ 1037 usart1_pins_b: usart1-1 { 1038 pins1 { 1039 pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */ 1040 bias-disable; 1041 drive-push-pull; 1042 slew-rate = <0>; 1043 }; 1044 pins2 { 1045 pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ 1046 bias-pull-up; 1047 }; 1048 }; 1049 1050 /omit-if-no-ref/ 1051 usart1_idle_pins_b: usart1-idle-1 { 1052 pins1 { 1053 pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */ 1054 }; 1055 pins2 { 1056 pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ 1057 bias-pull-up; 1058 }; 1059 }; 1060 1061 /omit-if-no-ref/ 1062 usart1_sleep_pins_b: usart1-sleep-1 { 1063 pins { 1064 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ 1065 <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */ 1066 }; 1067 }; 1068 1069 /omit-if-no-ref/ 1070 usart2_pins_a: usart2-0 { 1071 pins1 { 1072 pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */ 1073 <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ 1074 bias-disable; 1075 drive-push-pull; 1076 slew-rate = <0>; 1077 }; 1078 pins2 { 1079 pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ 1080 <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */ 1081 bias-disable; 1082 }; 1083 }; 1084 1085 /omit-if-no-ref/ 1086 usart2_idle_pins_a: usart2-idle-0 { 1087 pins1 { 1088 pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ 1089 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ 1090 }; 1091 pins2 { 1092 pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ 1093 bias-disable; 1094 drive-push-pull; 1095 slew-rate = <0>; 1096 }; 1097 pins3 { 1098 pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ 1099 bias-disable; 1100 }; 1101 }; 1102 1103 /omit-if-no-ref/ 1104 usart2_sleep_pins_a: usart2-sleep-0 { 1105 pins { 1106 pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ 1107 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 1108 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ 1109 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ 1110 }; 1111 }; 1112 1113 /omit-if-no-ref/ 1114 usart2_pins_b: usart2-1 { 1115 pins1 { 1116 pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */ 1117 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ 1118 bias-disable; 1119 drive-push-pull; 1120 slew-rate = <0>; 1121 }; 1122 pins2 { 1123 pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ 1124 <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */ 1125 bias-disable; 1126 }; 1127 }; 1128 1129 /omit-if-no-ref/ 1130 usart2_idle_pins_b: usart2-idle-1 { 1131 pins1 { 1132 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ 1133 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ 1134 }; 1135 pins2 { 1136 pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ 1137 bias-disable; 1138 drive-push-pull; 1139 slew-rate = <0>; 1140 }; 1141 pins3 { 1142 pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ 1143 bias-disable; 1144 }; 1145 }; 1146 1147 /omit-if-no-ref/ 1148 usart2_sleep_pins_b: usart2-sleep-1 { 1149 pins { 1150 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ 1151 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ 1152 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ 1153 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ 1154 }; 1155 }; 1156}; 1157