1/* 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "../armv7-m.dtsi" 44#include <dt-bindings/clock/stm32fx-clock.h> 45#include <dt-bindings/mfd/stm32f7-rcc.h> 46 47/ { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 clocks { 52 clk_hse: clk-hse { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <0>; 56 }; 57 58 clk-lse { 59 #clock-cells = <0>; 60 compatible = "fixed-clock"; 61 clock-frequency = <32768>; 62 }; 63 64 clk-lsi { 65 #clock-cells = <0>; 66 compatible = "fixed-clock"; 67 clock-frequency = <32000>; 68 }; 69 70 clk_i2s_ckin: clk-i2s-ckin { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <48000000>; 74 }; 75 }; 76 77 soc { 78 timers2: timers@40000000 { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 compatible = "st,stm32-timers"; 82 reg = <0x40000000 0x400>; 83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 84 clock-names = "int"; 85 status = "disabled"; 86 87 pwm { 88 compatible = "st,stm32-pwm"; 89 #pwm-cells = <3>; 90 status = "disabled"; 91 }; 92 93 timer@1 { 94 compatible = "st,stm32-timer-trigger"; 95 reg = <1>; 96 status = "disabled"; 97 }; 98 }; 99 100 timers3: timers@40000400 { 101 #address-cells = <1>; 102 #size-cells = <0>; 103 compatible = "st,stm32-timers"; 104 reg = <0x40000400 0x400>; 105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; 106 clock-names = "int"; 107 status = "disabled"; 108 109 pwm { 110 compatible = "st,stm32-pwm"; 111 #pwm-cells = <3>; 112 status = "disabled"; 113 }; 114 115 timer@2 { 116 compatible = "st,stm32-timer-trigger"; 117 reg = <2>; 118 status = "disabled"; 119 }; 120 }; 121 122 timers4: timers@40000800 { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 compatible = "st,stm32-timers"; 126 reg = <0x40000800 0x400>; 127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; 128 clock-names = "int"; 129 status = "disabled"; 130 131 pwm { 132 compatible = "st,stm32-pwm"; 133 #pwm-cells = <3>; 134 status = "disabled"; 135 }; 136 137 timer@3 { 138 compatible = "st,stm32-timer-trigger"; 139 reg = <3>; 140 status = "disabled"; 141 }; 142 }; 143 144 timers5: timers@40000c00 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 compatible = "st,stm32-timers"; 148 reg = <0x40000C00 0x400>; 149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 150 clock-names = "int"; 151 status = "disabled"; 152 153 pwm { 154 compatible = "st,stm32-pwm"; 155 #pwm-cells = <3>; 156 status = "disabled"; 157 }; 158 159 timer@4 { 160 compatible = "st,stm32-timer-trigger"; 161 reg = <4>; 162 status = "disabled"; 163 }; 164 }; 165 166 timers6: timers@40001000 { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 compatible = "st,stm32-timers"; 170 reg = <0x40001000 0x400>; 171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; 172 clock-names = "int"; 173 status = "disabled"; 174 175 timer@5 { 176 compatible = "st,stm32-timer-trigger"; 177 reg = <5>; 178 status = "disabled"; 179 }; 180 }; 181 182 timers7: timers@40001400 { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 compatible = "st,stm32-timers"; 186 reg = <0x40001400 0x400>; 187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; 188 clock-names = "int"; 189 status = "disabled"; 190 191 timer@6 { 192 compatible = "st,stm32-timer-trigger"; 193 reg = <6>; 194 status = "disabled"; 195 }; 196 }; 197 198 timers12: timers@40001800 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 compatible = "st,stm32-timers"; 202 reg = <0x40001800 0x400>; 203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; 204 clock-names = "int"; 205 status = "disabled"; 206 207 pwm { 208 compatible = "st,stm32-pwm"; 209 #pwm-cells = <3>; 210 status = "disabled"; 211 }; 212 213 timer@11 { 214 compatible = "st,stm32-timer-trigger"; 215 reg = <11>; 216 status = "disabled"; 217 }; 218 }; 219 220 timers13: timers@40001c00 { 221 compatible = "st,stm32-timers"; 222 reg = <0x40001C00 0x400>; 223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; 224 clock-names = "int"; 225 status = "disabled"; 226 227 pwm { 228 compatible = "st,stm32-pwm"; 229 #pwm-cells = <3>; 230 status = "disabled"; 231 }; 232 }; 233 234 timers14: timers@40002000 { 235 compatible = "st,stm32-timers"; 236 reg = <0x40002000 0x400>; 237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; 238 clock-names = "int"; 239 status = "disabled"; 240 241 pwm { 242 compatible = "st,stm32-pwm"; 243 #pwm-cells = <3>; 244 status = "disabled"; 245 }; 246 }; 247 248 rtc: rtc@40002800 { 249 compatible = "st,stm32-rtc"; 250 reg = <0x40002800 0x400>; 251 clocks = <&rcc 1 CLK_RTC>; 252 assigned-clocks = <&rcc 1 CLK_RTC>; 253 assigned-clock-parents = <&rcc 1 CLK_LSE>; 254 interrupt-parent = <&exti>; 255 interrupts = <17 1>; 256 st,syscfg = <&pwrcfg 0x00 0x100>; 257 status = "disabled"; 258 }; 259 260 can3: can@40003400 { 261 compatible = "st,stm32f4-bxcan"; 262 reg = <0x40003400 0x200>; 263 interrupts = <104>, <105>, <106>, <107>; 264 interrupt-names = "tx", "rx0", "rx1", "sce"; 265 resets = <&rcc STM32F7_APB1_RESET(CAN3)>; 266 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; 267 st,gcan = <&gcan3>; 268 status = "disabled"; 269 }; 270 271 gcan3: gcan@40003600 { 272 compatible = "st,stm32f4-gcan", "syscon"; 273 reg = <0x40003600 0x200>; 274 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; 275 }; 276 277 spi2: spi@40003800 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 compatible = "st,stm32f7-spi"; 281 reg = <0x40003800 0x400>; 282 interrupts = <36>; 283 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>; 284 status = "disabled"; 285 }; 286 287 spi3: spi@40003c00 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 compatible = "st,stm32f7-spi"; 291 reg = <0x40003c00 0x400>; 292 interrupts = <51>; 293 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>; 294 status = "disabled"; 295 }; 296 297 usart2: serial@40004400 { 298 compatible = "st,stm32f7-uart"; 299 reg = <0x40004400 0x400>; 300 interrupts = <38>; 301 clocks = <&rcc 1 CLK_USART2>; 302 status = "disabled"; 303 }; 304 305 usart3: serial@40004800 { 306 compatible = "st,stm32f7-uart"; 307 reg = <0x40004800 0x400>; 308 interrupts = <39>; 309 clocks = <&rcc 1 CLK_USART3>; 310 status = "disabled"; 311 }; 312 313 usart4: serial@40004c00 { 314 compatible = "st,stm32f7-uart"; 315 reg = <0x40004c00 0x400>; 316 interrupts = <52>; 317 clocks = <&rcc 1 CLK_UART4>; 318 status = "disabled"; 319 }; 320 321 usart5: serial@40005000 { 322 compatible = "st,stm32f7-uart"; 323 reg = <0x40005000 0x400>; 324 interrupts = <53>; 325 clocks = <&rcc 1 CLK_UART5>; 326 status = "disabled"; 327 }; 328 329 i2c1: i2c@40005400 { 330 compatible = "st,stm32f7-i2c"; 331 reg = <0x40005400 0x400>; 332 interrupts = <31>, 333 <32>; 334 resets = <&rcc STM32F7_APB1_RESET(I2C1)>; 335 clocks = <&rcc 1 CLK_I2C1>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 status = "disabled"; 339 }; 340 341 i2c2: i2c@40005800 { 342 compatible = "st,stm32f7-i2c"; 343 reg = <0x40005800 0x400>; 344 interrupts = <33>, 345 <34>; 346 resets = <&rcc STM32F7_APB1_RESET(I2C2)>; 347 clocks = <&rcc 1 CLK_I2C2>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 status = "disabled"; 351 }; 352 353 i2c3: i2c@40005c00 { 354 compatible = "st,stm32f7-i2c"; 355 reg = <0x40005c00 0x400>; 356 interrupts = <72>, 357 <73>; 358 resets = <&rcc STM32F7_APB1_RESET(I2C3)>; 359 clocks = <&rcc 1 CLK_I2C3>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 status = "disabled"; 363 }; 364 365 i2c4: i2c@40006000 { 366 compatible = "st,stm32f7-i2c"; 367 reg = <0x40006000 0x400>; 368 interrupts = <95>, 369 <96>; 370 resets = <&rcc STM32F7_APB1_RESET(I2C4)>; 371 clocks = <&rcc 1 CLK_I2C4>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 status = "disabled"; 375 }; 376 377 can1: can@40006400 { 378 compatible = "st,stm32f4-bxcan"; 379 reg = <0x40006400 0x200>; 380 interrupts = <19>, <20>, <21>, <22>; 381 interrupt-names = "tx", "rx0", "rx1", "sce"; 382 resets = <&rcc STM32F7_APB1_RESET(CAN1)>; 383 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; 384 st,can-primary; 385 st,gcan = <&gcan1>; 386 status = "disabled"; 387 }; 388 389 gcan1: gcan@40006600 { 390 compatible = "st,stm32f4-gcan", "syscon"; 391 reg = <0x40006600 0x200>; 392 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; 393 }; 394 395 can2: can@40006800 { 396 compatible = "st,stm32f4-bxcan"; 397 reg = <0x40006800 0x200>; 398 interrupts = <63>, <64>, <65>, <66>; 399 interrupt-names = "tx", "rx0", "rx1", "sce"; 400 resets = <&rcc STM32F7_APB1_RESET(CAN2)>; 401 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; 402 st,can-secondary; 403 st,gcan = <&gcan1>; 404 status = "disabled"; 405 }; 406 407 cec: cec@40006c00 { 408 compatible = "st,stm32-cec"; 409 reg = <0x40006C00 0x400>; 410 interrupts = <94>; 411 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; 412 clock-names = "cec", "hdmi-cec"; 413 status = "disabled"; 414 }; 415 416 usart7: serial@40007800 { 417 compatible = "st,stm32f7-uart"; 418 reg = <0x40007800 0x400>; 419 interrupts = <82>; 420 clocks = <&rcc 1 CLK_UART7>; 421 status = "disabled"; 422 }; 423 424 usart8: serial@40007c00 { 425 compatible = "st,stm32f7-uart"; 426 reg = <0x40007c00 0x400>; 427 interrupts = <83>; 428 clocks = <&rcc 1 CLK_UART8>; 429 status = "disabled"; 430 }; 431 432 timers1: timers@40010000 { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 compatible = "st,stm32-timers"; 436 reg = <0x40010000 0x400>; 437 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; 438 clock-names = "int"; 439 status = "disabled"; 440 441 pwm { 442 compatible = "st,stm32-pwm"; 443 #pwm-cells = <3>; 444 status = "disabled"; 445 }; 446 447 timer@0 { 448 compatible = "st,stm32-timer-trigger"; 449 reg = <0>; 450 status = "disabled"; 451 }; 452 }; 453 454 timers8: timers@40010400 { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 compatible = "st,stm32-timers"; 458 reg = <0x40010400 0x400>; 459 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; 460 clock-names = "int"; 461 status = "disabled"; 462 463 pwm { 464 compatible = "st,stm32-pwm"; 465 #pwm-cells = <3>; 466 status = "disabled"; 467 }; 468 469 timer@7 { 470 compatible = "st,stm32-timer-trigger"; 471 reg = <7>; 472 status = "disabled"; 473 }; 474 }; 475 476 usart1: serial@40011000 { 477 compatible = "st,stm32f7-uart"; 478 reg = <0x40011000 0x400>; 479 interrupts = <37>; 480 clocks = <&rcc 1 CLK_USART1>; 481 status = "disabled"; 482 }; 483 484 usart6: serial@40011400 { 485 compatible = "st,stm32f7-uart"; 486 reg = <0x40011400 0x400>; 487 interrupts = <71>; 488 clocks = <&rcc 1 CLK_USART6>; 489 status = "disabled"; 490 }; 491 492 sdio2: mmc@40011c00 { 493 compatible = "arm,pl180", "arm,primecell"; 494 arm,primecell-periphid = <0x00880180>; 495 reg = <0x40011c00 0x400>; 496 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; 497 clock-names = "apb_pclk"; 498 interrupts = <103>; 499 max-frequency = <48000000>; 500 status = "disabled"; 501 }; 502 503 sdio1: mmc@40012c00 { 504 compatible = "arm,pl180", "arm,primecell"; 505 arm,primecell-periphid = <0x00880180>; 506 reg = <0x40012c00 0x400>; 507 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; 508 clock-names = "apb_pclk"; 509 interrupts = <49>; 510 max-frequency = <48000000>; 511 status = "disabled"; 512 }; 513 514 spi1: spi@40013000 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 compatible = "st,stm32f7-spi"; 518 reg = <0x40013000 0x400>; 519 interrupts = <35>; 520 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>; 521 status = "disabled"; 522 }; 523 524 spi4: spi@40013400 { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 compatible = "st,stm32f7-spi"; 528 reg = <0x40013400 0x400>; 529 interrupts = <84>; 530 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>; 531 status = "disabled"; 532 }; 533 534 syscfg: syscon@40013800 { 535 compatible = "st,stm32-syscfg", "syscon"; 536 reg = <0x40013800 0x400>; 537 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>; 538 }; 539 540 exti: interrupt-controller@40013c00 { 541 compatible = "st,stm32-exti"; 542 interrupt-controller; 543 #interrupt-cells = <2>; 544 reg = <0x40013C00 0x400>; 545 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 546 }; 547 548 timers9: timers@40014000 { 549 #address-cells = <1>; 550 #size-cells = <0>; 551 compatible = "st,stm32-timers"; 552 reg = <0x40014000 0x400>; 553 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; 554 clock-names = "int"; 555 status = "disabled"; 556 557 pwm { 558 compatible = "st,stm32-pwm"; 559 #pwm-cells = <3>; 560 status = "disabled"; 561 }; 562 563 timer@8 { 564 compatible = "st,stm32-timer-trigger"; 565 reg = <8>; 566 status = "disabled"; 567 }; 568 }; 569 570 timers10: timers@40014400 { 571 compatible = "st,stm32-timers"; 572 reg = <0x40014400 0x400>; 573 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; 574 clock-names = "int"; 575 status = "disabled"; 576 577 pwm { 578 compatible = "st,stm32-pwm"; 579 #pwm-cells = <3>; 580 status = "disabled"; 581 }; 582 }; 583 584 timers11: timers@40014800 { 585 compatible = "st,stm32-timers"; 586 reg = <0x40014800 0x400>; 587 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; 588 clock-names = "int"; 589 status = "disabled"; 590 591 pwm { 592 compatible = "st,stm32-pwm"; 593 #pwm-cells = <3>; 594 status = "disabled"; 595 }; 596 }; 597 598 spi5: spi@40015000 { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 compatible = "st,stm32f7-spi"; 602 reg = <0x40015000 0x400>; 603 interrupts = <85>; 604 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>; 605 status = "disabled"; 606 }; 607 608 spi6: spi@40015400 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 compatible = "st,stm32f7-spi"; 612 reg = <0x40015400 0x400>; 613 interrupts = <86>; 614 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>; 615 status = "disabled"; 616 }; 617 618 ltdc: display-controller@40016800 { 619 compatible = "st,stm32-ltdc"; 620 reg = <0x40016800 0x200>; 621 interrupts = <88>, <89>; 622 resets = <&rcc STM32F7_APB2_RESET(LTDC)>; 623 clocks = <&rcc 1 CLK_LCD>; 624 clock-names = "lcd"; 625 status = "disabled"; 626 }; 627 628 pwrcfg: power-config@40007000 { 629 compatible = "st,stm32-power-config", "syscon"; 630 reg = <0x40007000 0x400>; 631 }; 632 633 crc: crc@40023000 { 634 compatible = "st,stm32f7-crc"; 635 reg = <0x40023000 0x400>; 636 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; 637 status = "disabled"; 638 }; 639 640 rcc: rcc@40023800 { 641 #reset-cells = <1>; 642 #clock-cells = <2>; 643 compatible = "st,stm32f746-rcc", "st,stm32-rcc"; 644 reg = <0x40023800 0x400>; 645 clocks = <&clk_hse>, <&clk_i2s_ckin>; 646 st,syscfg = <&pwrcfg>; 647 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 648 assigned-clock-rates = <1000000>; 649 }; 650 651 dma1: dma-controller@40026000 { 652 compatible = "st,stm32-dma"; 653 reg = <0x40026000 0x400>; 654 interrupts = <11>, 655 <12>, 656 <13>, 657 <14>, 658 <15>, 659 <16>, 660 <17>, 661 <47>; 662 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; 663 #dma-cells = <4>; 664 status = "disabled"; 665 }; 666 667 dma2: dma-controller@40026400 { 668 compatible = "st,stm32-dma"; 669 reg = <0x40026400 0x400>; 670 interrupts = <56>, 671 <57>, 672 <58>, 673 <59>, 674 <60>, 675 <68>, 676 <69>, 677 <70>; 678 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; 679 #dma-cells = <4>; 680 st,mem2mem; 681 status = "disabled"; 682 }; 683 684 usbotg_hs: usb@40040000 { 685 compatible = "st,stm32f7-hsotg"; 686 reg = <0x40040000 0x40000>; 687 interrupts = <77>; 688 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; 689 clock-names = "otg"; 690 g-rx-fifo-size = <256>; 691 g-np-tx-fifo-size = <32>; 692 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 693 status = "disabled"; 694 }; 695 696 usbotg_fs: usb@50000000 { 697 compatible = "st,stm32f4x9-fsotg"; 698 reg = <0x50000000 0x40000>; 699 interrupts = <67>; 700 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; 701 clock-names = "otg"; 702 status = "disabled"; 703 }; 704 }; 705}; 706 707&systick { 708 clocks = <&rcc 1 0>; 709 status = "okay"; 710}; 711