1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2015 STMicroelectronics R&D Limited 4 */ 5#include <dt-bindings/clock/stih418-clks.h> 6/ { 7 /* 8 * Fixed 30MHz oscillator inputs to SoC 9 */ 10 clk_sysin: clk-sysin { 11 #clock-cells = <0>; 12 compatible = "fixed-clock"; 13 clock-frequency = <30000000>; 14 clock-output-names = "CLK_SYSIN"; 15 }; 16 17 clk_tmdsout_hdmi: clk-tmdsout-hdmi { 18 #clock-cells = <0>; 19 compatible = "fixed-clock"; 20 clock-frequency = <0>; 21 }; 22 23 clocks { 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges; 27 28 compatible = "st,stih418-clk", "simple-bus"; 29 30 /* 31 * A9 PLL. 32 */ 33 clockgen-a9@92b0000 { 34 compatible = "st,clkgen-c32"; 35 reg = <0x92b0000 0x10000>; 36 37 clockgen_a9_pll: clockgen-a9-pll { 38 #clock-cells = <1>; 39 compatible = "st,stih418-clkgen-plla9"; 40 41 clocks = <&clk_sysin>; 42 }; 43 44 /* 45 * ARM CPU related clocks. 46 */ 47 clk_m_a9: clk-m-a9 { 48 #clock-cells = <0>; 49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; 50 51 clocks = <&clockgen_a9_pll 0>, 52 <&clockgen_a9_pll 0>, 53 <&clk_s_c0_flexgen 13>, 54 <&clk_m_a9_ext2f_div2>; 55 56 /* 57 * ARM Peripheral clock for timers 58 */ 59 arm_periph_clk: clk-m-a9-periphs { 60 #clock-cells = <0>; 61 compatible = "fixed-factor-clock"; 62 clocks = <&clk_m_a9>; 63 clock-div = <2>; 64 clock-mult = <1>; 65 }; 66 }; 67 }; 68 69 clockgen-a@90ff000 { 70 compatible = "st,clkgen-c32"; 71 reg = <0x90ff000 0x1000>; 72 73 clk_s_a0_pll: clk-s-a0-pll { 74 #clock-cells = <1>; 75 compatible = "st,clkgen-pll0-a0"; 76 77 clocks = <&clk_sysin>; 78 }; 79 80 clk_s_a0_flexgen: clk-s-a0-flexgen { 81 compatible = "st,flexgen", "st,flexgen-stih410-a0"; 82 83 #clock-cells = <1>; 84 85 clocks = <&clk_s_a0_pll 0>, 86 <&clk_sysin>; 87 }; 88 }; 89 90 clk_s_c0: clockgen-c@9103000 { 91 compatible = "st,clkgen-c32"; 92 reg = <0x9103000 0x1000>; 93 94 clk_s_c0_pll0: clk-s-c0-pll0 { 95 #clock-cells = <1>; 96 compatible = "st,clkgen-pll0-c0"; 97 98 clocks = <&clk_sysin>; 99 }; 100 101 clk_s_c0_pll1: clk-s-c0-pll1 { 102 #clock-cells = <1>; 103 compatible = "st,clkgen-pll1-c0"; 104 105 clocks = <&clk_sysin>; 106 }; 107 108 clk_s_c0_quadfs: clk-s-c0-quadfs { 109 #clock-cells = <1>; 110 compatible = "st,quadfs-pll"; 111 112 clocks = <&clk_sysin>; 113 }; 114 115 clk_s_c0_flexgen: clk-s-c0-flexgen { 116 #clock-cells = <1>; 117 compatible = "st,flexgen", "st,flexgen-stih418-c0"; 118 119 clocks = <&clk_s_c0_pll0 0>, 120 <&clk_s_c0_pll1 0>, 121 <&clk_s_c0_quadfs 0>, 122 <&clk_s_c0_quadfs 1>, 123 <&clk_s_c0_quadfs 2>, 124 <&clk_s_c0_quadfs 3>, 125 <&clk_sysin>; 126 127 /* 128 * ARM Peripheral clock for timers 129 */ 130 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { 131 #clock-cells = <0>; 132 compatible = "fixed-factor-clock"; 133 134 clocks = <&clk_s_c0_flexgen 13>; 135 136 clock-output-names = "clk-m-a9-ext2f-div2"; 137 138 clock-div = <2>; 139 clock-mult = <1>; 140 }; 141 }; 142 }; 143 144 clockgen-d0@9104000 { 145 compatible = "st,clkgen-c32"; 146 reg = <0x9104000 0x1000>; 147 148 clk_s_d0_quadfs: clk-s-d0-quadfs { 149 #clock-cells = <1>; 150 compatible = "st,quadfs-d0"; 151 152 clocks = <&clk_sysin>; 153 }; 154 155 clk_s_d0_flexgen: clk-s-d0-flexgen { 156 #clock-cells = <1>; 157 compatible = "st,flexgen", "st,flexgen-stih410-d0"; 158 159 clocks = <&clk_s_d0_quadfs 0>, 160 <&clk_s_d0_quadfs 1>, 161 <&clk_s_d0_quadfs 2>, 162 <&clk_s_d0_quadfs 3>, 163 <&clk_sysin>; 164 }; 165 }; 166 167 clockgen-d2@9106000 { 168 compatible = "st,clkgen-c32"; 169 reg = <0x9106000 0x1000>; 170 171 clk_s_d2_quadfs: clk-s-d2-quadfs { 172 #clock-cells = <1>; 173 compatible = "st,quadfs-d2"; 174 175 clocks = <&clk_sysin>; 176 }; 177 178 clk_s_d2_flexgen: clk-s-d2-flexgen { 179 #clock-cells = <1>; 180 compatible = "st,flexgen", "st,flexgen-stih418-d2"; 181 182 clocks = <&clk_s_d2_quadfs 0>, 183 <&clk_s_d2_quadfs 1>, 184 <&clk_s_d2_quadfs 2>, 185 <&clk_s_d2_quadfs 3>, 186 <&clk_sysin>, 187 <&clk_sysin>, 188 <&clk_tmdsout_hdmi>; 189 }; 190 }; 191 192 clockgen-d3@9107000 { 193 compatible = "st,clkgen-c32"; 194 reg = <0x9107000 0x1000>; 195 196 clk_s_d3_quadfs: clk-s-d3-quadfs { 197 #clock-cells = <1>; 198 compatible = "st,quadfs-d3"; 199 200 clocks = <&clk_sysin>; 201 }; 202 203 clk_s_d3_flexgen: clk-s-d3-flexgen { 204 #clock-cells = <1>; 205 compatible = "st,flexgen", "st,flexgen-stih407-d3"; 206 207 clocks = <&clk_s_d3_quadfs 0>, 208 <&clk_s_d3_quadfs 1>, 209 <&clk_s_d3_quadfs 2>, 210 <&clk_s_d3_quadfs 3>, 211 <&clk_sysin>; 212 }; 213 }; 214 }; 215}; 216