1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014 STMicroelectronics Limited. 4 * Author: Peter Griffin <peter.griffin@linaro.org> 5 */ 6#include "stih410-clock.dtsi" 7#include "stih407-family.dtsi" 8#include "stih410-pinctrl.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10/ { 11 aliases { 12 bdisp0 = &bdisp0; 13 }; 14 15 usb2_picophy1: phy2 { 16 compatible = "st,stih407-usb2-phy"; 17 #phy-cells = <0>; 18 st,syscfg = <&syscfg_core 0xf8 0xf4>; 19 resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 20 <&picophyreset STIH407_PICOPHY0_RESET>; 21 reset-names = "global", "port"; 22 23 status = "disabled"; 24 }; 25 26 usb2_picophy2: phy3 { 27 compatible = "st,stih407-usb2-phy"; 28 #phy-cells = <0>; 29 st,syscfg = <&syscfg_core 0xfc 0xf4>; 30 resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 31 <&picophyreset STIH407_PICOPHY1_RESET>; 32 reset-names = "global", "port"; 33 34 status = "disabled"; 35 }; 36 37 display-subsystem { 38 compatible = "st,sti-display-subsystem"; 39 ports = <&compositor>, <&hqvdp>, <&tvout>, <&sti_hdmi>; 40 41 assigned-clocks = <&clk_s_d2_quadfs 0>, 42 <&clk_s_d2_quadfs 1>, 43 <&clk_s_c0_pll1 0>, 44 <&clk_s_c0_flexgen CLK_COMPO_DVP>, 45 <&clk_s_c0_flexgen CLK_MAIN_DISP>, 46 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, 47 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, 48 <&clk_s_d2_flexgen CLK_PIX_GDP1>, 49 <&clk_s_d2_flexgen CLK_PIX_GDP2>, 50 <&clk_s_d2_flexgen CLK_PIX_GDP3>, 51 <&clk_s_d2_flexgen CLK_PIX_GDP4>; 52 53 assigned-clock-parents = <0>, 54 <0>, 55 <0>, 56 <&clk_s_c0_pll1 0>, 57 <&clk_s_c0_pll1 0>, 58 <&clk_s_d2_quadfs 0>, 59 <&clk_s_d2_quadfs 1>, 60 <&clk_s_d2_quadfs 0>, 61 <&clk_s_d2_quadfs 0>, 62 <&clk_s_d2_quadfs 0>, 63 <&clk_s_d2_quadfs 0>; 64 65 assigned-clock-rates = <297000000>, 66 <297000000>, 67 <0>, 68 <400000000>, 69 <400000000>; 70 }; 71 72 soc { 73 ohci0: usb@9a03c00 { 74 compatible = "st,st-ohci-300x"; 75 reg = <0x9a03c00 0x100>; 76 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 77 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 78 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; 79 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, 80 <&softreset STIH407_USB2_PORT0_SOFTRESET>; 81 reset-names = "power", "softreset"; 82 phys = <&usb2_picophy1>; 83 phy-names = "usb"; 84 85 status = "disabled"; 86 }; 87 88 ehci0: usb@9a03e00 { 89 compatible = "st,st-ehci-300x"; 90 reg = <0x9a03e00 0x100>; 91 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_usb0>; 94 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 95 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; 96 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, 97 <&softreset STIH407_USB2_PORT0_SOFTRESET>; 98 reset-names = "power", "softreset"; 99 phys = <&usb2_picophy1>; 100 phy-names = "usb"; 101 102 status = "disabled"; 103 }; 104 105 ohci1: usb@9a83c00 { 106 compatible = "st,st-ohci-300x"; 107 reg = <0x9a83c00 0x100>; 108 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 109 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 110 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; 111 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, 112 <&softreset STIH407_USB2_PORT1_SOFTRESET>; 113 reset-names = "power", "softreset"; 114 phys = <&usb2_picophy2>; 115 phy-names = "usb"; 116 117 status = "disabled"; 118 }; 119 120 ehci1: usb@9a83e00 { 121 compatible = "st,st-ehci-300x"; 122 reg = <0x9a83e00 0x100>; 123 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_usb1>; 126 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 127 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; 128 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, 129 <&softreset STIH407_USB2_PORT1_SOFTRESET>; 130 reset-names = "power", "softreset"; 131 phys = <&usb2_picophy2>; 132 phy-names = "usb"; 133 134 status = "disabled"; 135 }; 136 137 compositor: display-controller@9d11000 { 138 compatible = "st,stih407-compositor"; 139 reg = <0x9d11000 0x1000>; 140 141 clock-names = "compo_main", 142 "compo_aux", 143 "pix_main", 144 "pix_aux", 145 "pix_gdp1", 146 "pix_gdp2", 147 "pix_gdp3", 148 "pix_gdp4", 149 "main_parent", 150 "aux_parent"; 151 152 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, 153 <&clk_s_c0_flexgen CLK_COMPO_DVP>, 154 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, 155 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, 156 <&clk_s_d2_flexgen CLK_PIX_GDP1>, 157 <&clk_s_d2_flexgen CLK_PIX_GDP2>, 158 <&clk_s_d2_flexgen CLK_PIX_GDP3>, 159 <&clk_s_d2_flexgen CLK_PIX_GDP4>, 160 <&clk_s_d2_quadfs 0>, 161 <&clk_s_d2_quadfs 1>; 162 163 reset-names = "compo-main", "compo-aux"; 164 resets = <&softreset STIH407_COMPO_SOFTRESET>, 165 <&softreset STIH407_COMPO_SOFTRESET>; 166 st,vtg = <&vtg_main>, <&vtg_aux>; 167 168 ports { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 port@0 { 173 reg = <0>; 174 compo_main_out: endpoint { 175 remote-endpoint = <&tvout_in0>; 176 }; 177 }; 178 179 port@1 { 180 reg = <1>; 181 compo_aux_out: endpoint { 182 remote-endpoint = <&tvout_in1>; 183 }; 184 }; 185 }; 186 }; 187 188 tvout: encoder@8d08000 { 189 compatible = "st,stih407-tvout"; 190 reg = <0x8d08000 0x1000>; 191 reg-names = "tvout-reg"; 192 reset-names = "tvout"; 193 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; 194 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, 195 <&clk_s_d2_flexgen CLK_TMDS_HDMI>, 196 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, 197 <&clk_s_d0_flexgen CLK_PCM_0>, 198 <&clk_s_d2_flexgen CLK_PIX_HDDAC>, 199 <&clk_s_d2_flexgen CLK_HDDAC>; 200 201 assigned-clock-parents = <&clk_s_d2_quadfs 0>, 202 <&clk_tmdsout_hdmi>, 203 <&clk_s_d2_quadfs 0>, 204 <&clk_s_d0_quadfs 0>, 205 <&clk_s_d2_quadfs 0>, 206 <&clk_s_d2_quadfs 0>; 207 208 ports { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 212 port@0 { 213 reg = <0>; 214 tvout_in0: endpoint { 215 remote-endpoint = <&compo_main_out>; 216 }; 217 }; 218 219 port@1 { 220 reg = <1>; 221 tvout_in1: endpoint { 222 remote-endpoint = <&compo_aux_out>; 223 }; 224 }; 225 226 port@2 { 227 reg = <2>; 228 tvout_out0: endpoint { 229 remote-endpoint = <&hdmi_in>; 230 }; 231 }; 232 233 port@3 { 234 reg = <3>; 235 tvout_out1: endpoint { 236 remote-endpoint = <&hda_in>; 237 }; 238 }; 239 }; 240 }; 241 242 sti_hdmi: hdmi@8d04000 { 243 compatible = "st,stih407-hdmi"; 244 reg = <0x8d04000 0x1000>; 245 reg-names = "hdmi-reg"; 246 #sound-dai-cells = <0>; 247 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 248 interrupt-names = "irq"; 249 clock-names = "pix", 250 "tmds", 251 "phy", 252 "audio", 253 "main_parent", 254 "aux_parent"; 255 256 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, 257 <&clk_s_d2_flexgen CLK_TMDS_HDMI>, 258 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, 259 <&clk_s_d0_flexgen CLK_PCM_0>, 260 <&clk_s_d2_quadfs 0>, 261 <&clk_s_d2_quadfs 1>; 262 263 hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; 264 reset-names = "hdmi"; 265 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; 266 ddc = <&hdmiddc>; 267 268 port { 269 hdmi_in: endpoint { 270 remote-endpoint = <&tvout_out0>; 271 }; 272 }; 273 }; 274 275 analog@8d02000 { 276 compatible = "st,stih407-hda"; 277 status = "disabled"; 278 reg = <0x8d02000 0x400>, <0x92b0120 0x4>; 279 reg-names = "hda-reg", "video-dacs-ctrl"; 280 clock-names = "pix", 281 "hddac", 282 "main_parent", 283 "aux_parent"; 284 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, 285 <&clk_s_d2_flexgen CLK_HDDAC>, 286 <&clk_s_d2_quadfs 0>, 287 <&clk_s_d2_quadfs 1>; 288 289 port { 290 hda_in: endpoint { 291 remote-endpoint = <&tvout_out1>; 292 }; 293 }; 294 }; 295 296 hqvdp: plane@9c00000 { 297 compatible = "st,stih407-hqvdp"; 298 reg = <0x9C00000 0x100000>; 299 clock-names = "hqvdp", "pix_main"; 300 clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, 301 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; 302 reset-names = "hqvdp"; 303 resets = <&softreset STIH407_HDQVDP_SOFTRESET>; 304 st,vtg = <&vtg_main>; 305 }; 306 307 bdisp0:bdisp@9f10000 { 308 compatible = "st,stih407-bdisp"; 309 reg = <0x9f10000 0x1000>; 310 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 311 clock-names = "bdisp"; 312 clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; 313 }; 314 315 hva@8c85000 { 316 compatible = "st,st-hva"; 317 reg = <0x8c85000 0x400>, <0x6000000 0x40000>; 318 reg-names = "hva_registers", "hva_esram"; 319 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 321 clock-names = "clk_hva"; 322 clocks = <&clk_s_c0_flexgen CLK_HVA>; 323 }; 324 325 thermal@91a0000 { 326 compatible = "st,stih407-thermal"; 327 reg = <0x91a0000 0x28>; 328 clock-names = "thermal"; 329 clocks = <&clk_sysin>; 330 interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; 331 #thermal-sensor-cells = <0>; 332 }; 333 334 cec@94a087c { 335 compatible = "st,stih-cec"; 336 reg = <0x94a087c 0x64>; 337 clocks = <&clk_sysin>; 338 clock-names = "cec-clk"; 339 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "cec-irq"; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_cec0_default>; 343 resets = <&softreset STIH407_LPM_SOFTRESET>; 344 hdmi-phandle = <&sti_hdmi>; 345 }; 346 347 gpu: gpu@9f00000 { 348 compatible = "st,stih410-mali", "arm,mali-400"; 349 reg = <0x9f00000 0x10000>; 350 /* LIMA driver needs 2 clocks, use the same for both */ 351 clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>, 352 <&clk_s_c0_flexgen CLK_ICN_GPU>; 353 clock-names = "bus", "core"; 354 assigned-clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>; 355 assigned-clock-rates = <400000000>; 356 resets = <&softreset STIH407_GPU_SOFTRESET>; 357 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 367 interrupt-names = "gp", 368 "gpmmu", 369 "pp0", 370 "ppmmu0", 371 "pp1", 372 "ppmmu1", 373 "pp2", 374 "ppmmu2", 375 "pp3", 376 "ppmmu3"; 377 378 status = "disabled"; 379 }; 380 }; 381}; 382