1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE) 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2021 Socionext Inc. 6*724ba675SRob Herring * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 7*724ba675SRob Herring */ 8*724ba675SRob Herring 9*724ba675SRob Herring/dts-v1/; 10*724ba675SRob Herring#include "uniphier-pro5.dtsi" 11*724ba675SRob Herring#include "uniphier-support-card.dtsi" 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring model = "UniPhier Pro5 EP-CORE Board"; 15*724ba675SRob Herring compatible = "socionext,uniphier-pro5-epcore", "socionext,uniphier-pro5"; 16*724ba675SRob Herring 17*724ba675SRob Herring chosen { 18*724ba675SRob Herring stdout-path = "serial0:115200n8"; 19*724ba675SRob Herring }; 20*724ba675SRob Herring 21*724ba675SRob Herring aliases { 22*724ba675SRob Herring serial0 = &serial0; 23*724ba675SRob Herring serial1 = &serial1; 24*724ba675SRob Herring serial2 = &serial2; 25*724ba675SRob Herring i2c0 = &i2c0; 26*724ba675SRob Herring }; 27*724ba675SRob Herring 28*724ba675SRob Herring memory@80000000 { 29*724ba675SRob Herring device_type = "memory"; 30*724ba675SRob Herring reg = <0x80000000 0x40000000>; 31*724ba675SRob Herring }; 32*724ba675SRob Herring}; 33*724ba675SRob Herring 34*724ba675SRob Herringðsc { 35*724ba675SRob Herring interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 36*724ba675SRob Herring}; 37*724ba675SRob Herring 38*724ba675SRob Herring&serialsc { 39*724ba675SRob Herring interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 40*724ba675SRob Herring}; 41*724ba675SRob Herring 42*724ba675SRob Herring&serial0 { 43*724ba675SRob Herring status = "okay"; 44*724ba675SRob Herring}; 45*724ba675SRob Herring 46*724ba675SRob Herring&serial1 { 47*724ba675SRob Herring status = "okay"; 48*724ba675SRob Herring}; 49*724ba675SRob Herring 50*724ba675SRob Herring&serial2 { 51*724ba675SRob Herring status = "okay"; 52*724ba675SRob Herring}; 53*724ba675SRob Herring 54*724ba675SRob Herring&i2c0 { 55*724ba675SRob Herring status = "okay"; 56*724ba675SRob Herring}; 57*724ba675SRob Herring 58*724ba675SRob Herring&usb0 { 59*724ba675SRob Herring status = "okay"; 60*724ba675SRob Herring}; 61*724ba675SRob Herring 62*724ba675SRob Herring&usb1 { 63*724ba675SRob Herring status = "okay"; 64*724ba675SRob Herring}; 65*724ba675SRob Herring 66*724ba675SRob Herring&emmc { 67*724ba675SRob Herring status = "okay"; 68*724ba675SRob Herring}; 69*724ba675SRob Herring 70*724ba675SRob Herring&sd { 71*724ba675SRob Herring status = "okay"; 72*724ba675SRob Herring}; 73*724ba675SRob Herring 74*724ba675SRob Herring&pcie_ep { 75*724ba675SRob Herring status = "okay"; 76*724ba675SRob Herring}; 77