1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2020 thingy.jp. 4*724ba675SRob Herring * Author: Daniel Palmer <daniel@thingy.jp> 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring#include "mstar-infinity.dtsi" 8*724ba675SRob Herring 9*724ba675SRob Herring&cpu0_opp_table { 10*724ba675SRob Herring opp-1000000000 { 11*724ba675SRob Herring opp-hz = /bits/ 64 <1000000000>; 12*724ba675SRob Herring opp-microvolt = <1000000>; 13*724ba675SRob Herring clock-latency-ns = <300000>; 14*724ba675SRob Herring }; 15*724ba675SRob Herring 16*724ba675SRob Herring opp-1200000000 { 17*724ba675SRob Herring opp-hz = /bits/ 64 <1200000000>; 18*724ba675SRob Herring opp-microvolt = <1000000>; 19*724ba675SRob Herring clock-latency-ns = <300000>; 20*724ba675SRob Herring }; 21*724ba675SRob Herring}; 22*724ba675SRob Herring 23*724ba675SRob Herring&cpus { 24*724ba675SRob Herring cpu1: cpu@1 { 25*724ba675SRob Herring device_type = "cpu"; 26*724ba675SRob Herring compatible = "arm,cortex-a7"; 27*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 28*724ba675SRob Herring reg = <0x1>; 29*724ba675SRob Herring clocks = <&cpupll>; 30*724ba675SRob Herring clock-names = "cpuclk"; 31*724ba675SRob Herring }; 32*724ba675SRob Herring}; 33*724ba675SRob Herring 34*724ba675SRob Herring&riu { 35*724ba675SRob Herring smpctrl: smpctrl@204000 { 36*724ba675SRob Herring reg = <0x204000 0x200>; 37*724ba675SRob Herring status = "disabled"; 38*724ba675SRob Herring }; 39*724ba675SRob Herring}; 40