xref: /linux/arch/arm/boot/dts/rockchip/rv1108.dtsi (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/rv1108-cru.h>
7#include <dt-bindings/pinctrl/rockchip.h>
8#include <dt-bindings/thermal/thermal.h>
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12
13	compatible = "rockchip,rv1108";
14
15	interrupt-parent = <&gic>;
16
17	aliases {
18		i2c0 = &i2c0;
19		i2c1 = &i2c1;
20		i2c2 = &i2c2;
21		i2c3 = &i2c3;
22		serial0 = &uart0;
23		serial1 = &uart1;
24		serial2 = &uart2;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu0: cpu@f00 {
32			device_type = "cpu";
33			compatible = "arm,cortex-a7";
34			reg = <0xf00>;
35			clock-latency = <40000>;
36			clocks = <&cru ARMCLK>;
37			#cooling-cells = <2>; /* min followed by max */
38			dynamic-power-coefficient = <75>;
39			operating-points-v2 = <&cpu_opp_table>;
40		};
41	};
42
43	cpu_opp_table: opp-table-0 {
44		compatible = "operating-points-v2";
45
46		opp-408000000 {
47			opp-hz = /bits/ 64 <408000000>;
48			opp-microvolt = <975000>;
49			clock-latency-ns = <40000>;
50		};
51		opp-600000000 {
52			opp-hz = /bits/ 64 <600000000>;
53			opp-microvolt = <975000>;
54			clock-latency-ns = <40000>;
55		};
56		opp-816000000 {
57			opp-hz = /bits/ 64 <816000000>;
58			opp-microvolt = <1025000>;
59			clock-latency-ns = <40000>;
60		};
61		opp-1008000000 {
62			opp-hz = /bits/ 64 <1008000000>;
63			opp-microvolt = <1150000>;
64			clock-latency-ns = <40000>;
65		};
66	};
67
68	arm-pmu {
69		compatible = "arm,cortex-a7-pmu";
70		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
71	};
72
73	timer {
74		compatible = "arm,armv7-timer";
75		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
77		arm,cpu-registers-not-fw-configured;
78		clock-frequency = <24000000>;
79	};
80
81	xin24m: oscillator {
82		compatible = "fixed-clock";
83		clock-frequency = <24000000>;
84		clock-output-names = "xin24m";
85		#clock-cells = <0>;
86	};
87
88	bus_intmem: sram@10080000 {
89		compatible = "mmio-sram";
90		reg = <0x10080000 0x2000>;
91		#address-cells = <1>;
92		#size-cells = <1>;
93		ranges = <0 0x10080000 0x2000>;
94	};
95
96	uart2: serial@10210000 {
97		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
98		reg = <0x10210000 0x100>;
99		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
100		reg-shift = <2>;
101		reg-io-width = <4>;
102		clock-frequency = <24000000>;
103		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
104		clock-names = "baudclk", "apb_pclk";
105		dmas = <&pdma 6>, <&pdma 7>;
106		pinctrl-names = "default";
107		pinctrl-0 = <&uart2m0_xfer>;
108		status = "disabled";
109	};
110
111	uart1: serial@10220000 {
112		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
113		reg = <0x10220000 0x100>;
114		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
115		reg-shift = <2>;
116		reg-io-width = <4>;
117		clock-frequency = <24000000>;
118		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
119		clock-names = "baudclk", "apb_pclk";
120		dmas = <&pdma 4>, <&pdma 5>;
121		pinctrl-names = "default";
122		pinctrl-0 = <&uart1_xfer>;
123		status = "disabled";
124	};
125
126	uart0: serial@10230000 {
127		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
128		reg = <0x10230000 0x100>;
129		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
130		reg-shift = <2>;
131		reg-io-width = <4>;
132		clock-frequency = <24000000>;
133		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
134		clock-names = "baudclk", "apb_pclk";
135		dmas = <&pdma 2>, <&pdma 3>;
136		pinctrl-names = "default";
137		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
138		status = "disabled";
139	};
140
141	i2c1: i2c@10240000 {
142		compatible = "rockchip,rv1108-i2c";
143		reg = <0x10240000 0x1000>;
144		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
145		#address-cells = <1>;
146		#size-cells = <0>;
147		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
148		clock-names = "i2c", "pclk";
149		pinctrl-names = "default";
150		pinctrl-0 = <&i2c1_xfer>;
151		rockchip,grf = <&grf>;
152		status = "disabled";
153	};
154
155	i2c2: i2c@10250000 {
156		compatible = "rockchip,rv1108-i2c";
157		reg = <0x10250000 0x1000>;
158		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
159		#address-cells = <1>;
160		#size-cells = <0>;
161		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
162		clock-names = "i2c", "pclk";
163		pinctrl-names = "default";
164		pinctrl-0 = <&i2c2m1_xfer>;
165		rockchip,grf = <&grf>;
166		status = "disabled";
167	};
168
169	i2c3: i2c@10260000 {
170		compatible = "rockchip,rv1108-i2c";
171		reg = <0x10260000 0x1000>;
172		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
173		#address-cells = <1>;
174		#size-cells = <0>;
175		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
176		clock-names = "i2c", "pclk";
177		pinctrl-names = "default";
178		pinctrl-0 = <&i2c3_xfer>;
179		rockchip,grf = <&grf>;
180		status = "disabled";
181	};
182
183	spi: spi@10270000 {
184		compatible = "rockchip,rv1108-spi";
185		reg = <0x10270000 0x1000>;
186		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
187		clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
188		clock-names = "spiclk", "apb_pclk";
189		dmas = <&pdma 8>, <&pdma 9>;
190		dma-names = "tx", "rx";
191		#address-cells = <1>;
192		#size-cells = <0>;
193		status = "disabled";
194	};
195
196	pwm4: pwm@10280000 {
197		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
198		reg = <0x10280000 0x10>;
199		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
200		clock-names = "pwm", "pclk";
201		pinctrl-names = "default";
202		pinctrl-0 = <&pwm4_pin>;
203		#pwm-cells = <3>;
204		status = "disabled";
205	};
206
207	pwm5: pwm@10280010 {
208		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
209		reg = <0x10280010 0x10>;
210		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
211		clock-names = "pwm", "pclk";
212		pinctrl-names = "default";
213		pinctrl-0 = <&pwm5_pin>;
214		#pwm-cells = <3>;
215		status = "disabled";
216	};
217
218	pwm6: pwm@10280020 {
219		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
220		reg = <0x10280020 0x10>;
221		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
222		clock-names = "pwm", "pclk";
223		pinctrl-names = "default";
224		pinctrl-0 = <&pwm6_pin>;
225		#pwm-cells = <3>;
226		status = "disabled";
227	};
228
229	pwm7: pwm@10280030 {
230		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
231		reg = <0x10280030 0x10>;
232		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
233		clock-names = "pwm", "pclk";
234		pinctrl-names = "default";
235		pinctrl-0 = <&pwm7_pin>;
236		#pwm-cells = <3>;
237		status = "disabled";
238	};
239
240	pdma: dma-controller@102a0000 {
241		compatible = "arm,pl330", "arm,primecell";
242		reg = <0x102a0000 0x4000>;
243		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
244		#dma-cells = <1>;
245		arm,pl330-broken-no-flushp;
246		arm,pl330-periph-burst;
247		clocks = <&cru ACLK_DMAC>;
248		clock-names = "apb_pclk";
249	};
250
251	grf: syscon@10300000 {
252		compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
253		reg = <0x10300000 0x1000>;
254		#address-cells = <1>;
255		#size-cells = <1>;
256
257		io_domains: io-domains {
258			compatible = "rockchip,rv1108-io-voltage-domain";
259			status = "disabled";
260		};
261
262		u2phy: usb2phy@100 {
263			compatible = "rockchip,rv1108-usb2phy";
264			reg = <0x100 0x0c>;
265			clocks = <&cru SCLK_USBPHY>;
266			clock-names = "phyclk";
267			#clock-cells = <0>;
268			clock-output-names = "usbphy";
269			rockchip,usbgrf = <&usbgrf>;
270			status = "disabled";
271
272			u2phy_otg: otg-port {
273				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
274				interrupt-names = "otg-mux";
275				#phy-cells = <0>;
276				status = "disabled";
277			};
278
279			u2phy_host: host-port {
280				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
281				interrupt-names = "linestate";
282				#phy-cells = <0>;
283				status = "disabled";
284			};
285		};
286	};
287
288	timer: timer@10350000 {
289		compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
290		reg = <0x10350000 0x20>;
291		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
292		clocks = <&cru PCLK_TIMER>, <&xin24m>;
293		clock-names = "pclk", "timer";
294	};
295
296	watchdog: watchdog@10360000 {
297		compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
298		reg = <0x10360000 0x100>;
299		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
300		clocks = <&cru PCLK_WDT>;
301		status = "disabled";
302	};
303
304	thermal-zones {
305		soc_thermal: soc-thermal {
306			polling-delay-passive = <20>;
307			polling-delay = <1000>;
308			sustainable-power = <50>;
309			thermal-sensors = <&tsadc 0>;
310
311			trips {
312				threshold: trip-point0 {
313					temperature = <70000>;
314					hysteresis = <2000>;
315					type = "passive";
316				};
317				target: trip-point1 {
318					temperature = <85000>;
319					hysteresis = <2000>;
320					type = "passive";
321				};
322				soc_crit: soc-crit {
323					temperature = <95000>;
324					hysteresis = <2000>;
325					type = "critical";
326				};
327			};
328
329			cooling-maps {
330				map0 {
331					trip = <&target>;
332					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
333					contribution = <4096>;
334				};
335			};
336		};
337	};
338
339	tsadc: tsadc@10370000 {
340		compatible = "rockchip,rv1108-tsadc";
341		reg = <0x10370000 0x100>;
342		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
343		assigned-clocks = <&cru SCLK_TSADC>;
344		assigned-clock-rates = <750000>;
345		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
346		clock-names = "tsadc", "apb_pclk";
347		pinctrl-names = "init", "default", "sleep";
348		pinctrl-0 = <&otp_pin>;
349		pinctrl-1 = <&otp_out>;
350		pinctrl-2 = <&otp_pin>;
351		resets = <&cru SRST_TSADC>;
352		reset-names = "tsadc-apb";
353		rockchip,hw-tshut-temp = <120000>;
354		#thermal-sensor-cells = <1>;
355		status = "disabled";
356	};
357
358	adc: adc@1038c000 {
359		compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
360		reg = <0x1038c000 0x100>;
361		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
362		#io-channel-cells = <1>;
363		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
364		clock-names = "saradc", "apb_pclk";
365		status = "disabled";
366	};
367
368	i2c0: i2c@20000000 {
369		compatible = "rockchip,rv1108-i2c";
370		reg = <0x20000000 0x1000>;
371		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
372		#address-cells = <1>;
373		#size-cells = <0>;
374		clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
375		clock-names = "i2c", "pclk";
376		pinctrl-names = "default";
377		pinctrl-0 = <&i2c0_xfer>;
378		rockchip,grf = <&grf>;
379		status = "disabled";
380	};
381
382	pwm0: pwm@20040000 {
383		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
384		reg = <0x20040000 0x10>;
385		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
386		clock-names = "pwm", "pclk";
387		pinctrl-names = "default";
388		pinctrl-0 = <&pwm0_pin>;
389		#pwm-cells = <3>;
390		status = "disabled";
391	};
392
393	pwm1: pwm@20040010 {
394		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
395		reg = <0x20040010 0x10>;
396		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
397		clock-names = "pwm", "pclk";
398		pinctrl-names = "default";
399		pinctrl-0 = <&pwm1_pin>;
400		#pwm-cells = <3>;
401		status = "disabled";
402	};
403
404	pwm2: pwm@20040020 {
405		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
406		reg = <0x20040020 0x10>;
407		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
408		clock-names = "pwm", "pclk";
409		pinctrl-names = "default";
410		pinctrl-0 = <&pwm2_pin>;
411		#pwm-cells = <3>;
412		status = "disabled";
413	};
414
415	pwm3: pwm@20040030 {
416		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
417		reg = <0x20040030 0x10>;
418		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
419		clock-names = "pwm", "pclk";
420		pinctrl-names = "default";
421		pinctrl-0 = <&pwm3_pin>;
422		#pwm-cells = <3>;
423		status = "disabled";
424	};
425
426	pmugrf: syscon@20060000 {
427		compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
428		reg = <0x20060000 0x1000>;
429
430		pmu_io_domains: io-domains {
431			compatible = "rockchip,rv1108-pmu-io-voltage-domain";
432			status = "disabled";
433		};
434	};
435
436	usbgrf: syscon@202a0000 {
437		compatible = "rockchip,rv1108-usbgrf", "syscon";
438		reg = <0x202a0000 0x1000>;
439	};
440
441	cru: clock-controller@20200000 {
442		compatible = "rockchip,rv1108-cru";
443		reg = <0x20200000 0x1000>;
444		clocks = <&xin24m>;
445		clock-names = "xin24m";
446		rockchip,grf = <&grf>;
447		#clock-cells = <1>;
448		#reset-cells = <1>;
449	};
450
451	nfc: nand-controller@30100000 {
452		compatible = "rockchip,rv1108-nfc";
453		reg = <0x30100000  0x1000>;
454		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
455		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
456		clock-names = "ahb", "nfc";
457		assigned-clocks = <&cru SCLK_NANDC>;
458		assigned-clock-rates = <150000000>;
459		status = "disabled";
460	};
461
462	emmc: mmc@30110000 {
463		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
464		reg = <0x30110000 0x4000>;
465		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
466		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
467			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
468		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
469		fifo-depth = <0x100>;
470		max-frequency = <150000000>;
471		status = "disabled";
472	};
473
474	sdio: mmc@30120000 {
475		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
476		reg = <0x30120000 0x4000>;
477		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
478		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
479			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
480		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
481		fifo-depth = <0x100>;
482		max-frequency = <150000000>;
483		status = "disabled";
484	};
485
486	sdmmc: mmc@30130000 {
487		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
488		reg = <0x30130000 0x4000>;
489		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
490		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
491			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
492		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
493		fifo-depth = <0x100>;
494		max-frequency = <100000000>;
495		pinctrl-names = "default";
496		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
497		status = "disabled";
498	};
499
500	usb_host_ehci: usb@30140000 {
501		compatible = "generic-ehci";
502		reg = <0x30140000 0x20000>;
503		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
504		clocks = <&cru HCLK_HOST0>, <&u2phy>;
505		phys = <&u2phy_host>;
506		phy-names = "usb";
507		status = "disabled";
508	};
509
510	usb_host_ohci: usb@30160000 {
511		compatible = "generic-ohci";
512		reg = <0x30160000 0x20000>;
513		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
514		clocks = <&cru HCLK_HOST0>, <&u2phy>;
515		phys = <&u2phy_host>;
516		phy-names = "usb";
517		status = "disabled";
518	};
519
520	usb_otg: usb@30180000 {
521		compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
522			     "snps,dwc2";
523		reg = <0x30180000 0x40000>;
524		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
525		clocks = <&cru HCLK_OTG>;
526		clock-names = "otg";
527		dr_mode = "otg";
528		g-np-tx-fifo-size = <16>;
529		g-rx-fifo-size = <280>;
530		g-tx-fifo-size = <256 128 128 64 32 16>;
531		phys = <&u2phy_otg>;
532		phy-names = "usb2-phy";
533		status = "disabled";
534	};
535
536	sfc: spi@301c0000 {
537		compatible = "rockchip,sfc";
538		reg = <0x301c0000 0x4000>;
539		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
540		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
541		clock-names = "clk_sfc", "hclk_sfc";
542		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
543		pinctrl-names = "default";
544		status = "disabled";
545	};
546
547	gmac: ethernet@30200000 {
548		compatible = "rockchip,rv1108-gmac";
549		reg = <0x30200000 0x10000>;
550		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
551			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
552		interrupt-names = "macirq", "eth_wake_irq";
553		clocks = <&cru SCLK_MAC>,
554			<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
555			<&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
556			<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
557		clock-names = "stmmaceth",
558			"mac_clk_rx", "mac_clk_tx",
559			"clk_mac_ref", "clk_mac_refout",
560			"aclk_mac", "pclk_mac";
561		/* rv1108 only supports an rmii interface */
562		phy-mode = "rmii";
563		pinctrl-names = "default";
564		pinctrl-0 = <&rmii_pins>;
565		rockchip,grf = <&grf>;
566		status = "disabled";
567	};
568
569	gic: interrupt-controller@32010000 {
570		compatible = "arm,gic-400";
571		interrupt-controller;
572		#interrupt-cells = <3>;
573		#address-cells = <0>;
574
575		reg = <0x32011000 0x1000>,
576		      <0x32012000 0x2000>,
577		      <0x32014000 0x2000>,
578		      <0x32016000 0x2000>;
579		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
580	};
581
582	pinctrl: pinctrl {
583		compatible = "rockchip,rv1108-pinctrl";
584		rockchip,grf = <&grf>;
585		rockchip,pmu = <&pmugrf>;
586		#address-cells = <1>;
587		#size-cells = <1>;
588		ranges;
589
590		gpio0: gpio@20030000 {
591			compatible = "rockchip,gpio-bank";
592			reg = <0x20030000 0x100>;
593			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
594			clocks = <&cru PCLK_GPIO0_PMU>;
595
596			gpio-controller;
597			#gpio-cells = <2>;
598
599			interrupt-controller;
600			#interrupt-cells = <2>;
601		};
602
603		gpio1: gpio@10310000 {
604			compatible = "rockchip,gpio-bank";
605			reg = <0x10310000 0x100>;
606			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
607			clocks = <&cru PCLK_GPIO1>;
608
609			gpio-controller;
610			#gpio-cells = <2>;
611
612			interrupt-controller;
613			#interrupt-cells = <2>;
614		};
615
616		gpio2: gpio@10320000 {
617			compatible = "rockchip,gpio-bank";
618			reg = <0x10320000 0x100>;
619			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
620			clocks = <&cru PCLK_GPIO2>;
621
622			gpio-controller;
623			#gpio-cells = <2>;
624
625			interrupt-controller;
626			#interrupt-cells = <2>;
627		};
628
629		gpio3: gpio@10330000 {
630			compatible = "rockchip,gpio-bank";
631			reg = <0x10330000 0x100>;
632			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
633			clocks = <&cru PCLK_GPIO3>;
634
635			gpio-controller;
636			#gpio-cells = <2>;
637
638			interrupt-controller;
639			#interrupt-cells = <2>;
640		};
641
642		pcfg_pull_up: pcfg-pull-up {
643			bias-pull-up;
644		};
645
646		pcfg_pull_down: pcfg-pull-down {
647			bias-pull-down;
648		};
649
650		pcfg_pull_none: pcfg-pull-none {
651			bias-disable;
652		};
653
654		pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
655			drive-strength = <8>;
656		};
657
658		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
659			drive-strength = <12>;
660		};
661
662		pcfg_pull_none_smt: pcfg-pull-none-smt {
663			bias-disable;
664			input-schmitt-enable;
665		};
666
667		pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
668			bias-pull-up;
669			drive-strength = <8>;
670		};
671
672		pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
673			drive-strength = <4>;
674		};
675
676		pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
677			bias-pull-up;
678			drive-strength = <4>;
679		};
680
681		pcfg_output_high: pcfg-output-high {
682			output-high;
683		};
684
685		pcfg_output_low: pcfg-output-low {
686			output-low;
687		};
688
689		pcfg_input_high: pcfg-input-high {
690			bias-pull-up;
691			input-enable;
692		};
693
694		emmc {
695			emmc_bus8: emmc-bus8 {
696				rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
697						<2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
698						<2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
699						<2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
700						<2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
701						<2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
702						<2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
703						<2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
704			};
705
706			emmc_clk: emmc-clk {
707				rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
708			};
709
710			emmc_cmd: emmc-cmd {
711				rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
712			};
713		};
714
715		sfc {
716			sfc_bus4: sfc-bus4 {
717				rockchip,pins =
718					<2 RK_PA0 3 &pcfg_pull_none>,
719					<2 RK_PA1 3 &pcfg_pull_none>,
720					<2 RK_PA2 3 &pcfg_pull_none>,
721					<2 RK_PA3 3 &pcfg_pull_none>;
722			};
723
724			sfc_bus2: sfc-bus2 {
725				rockchip,pins =
726					<2 RK_PA0 3 &pcfg_pull_none>,
727					<2 RK_PA1 3 &pcfg_pull_none>;
728			};
729
730			sfc_cs0: sfc-cs0 {
731				rockchip,pins =
732					<2 RK_PB4 3 &pcfg_pull_none>;
733			};
734
735			sfc_clk: sfc-clk {
736				rockchip,pins =
737					<2 RK_PB7 2 &pcfg_pull_none>;
738			};
739		};
740
741		gmac {
742			rmii_pins: rmii-pins {
743				rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
744						<1 RK_PC3 2 &pcfg_pull_none>,
745						<1 RK_PC4 2 &pcfg_pull_none>,
746						<1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
747						<1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
748						<1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
749						<1 RK_PB5 3 &pcfg_pull_none>,
750						<1 RK_PB6 3 &pcfg_pull_none>,
751						<1 RK_PB7 3 &pcfg_pull_none>,
752						<1 RK_PC2 3 &pcfg_pull_none>;
753			};
754		};
755
756		i2c0 {
757			i2c0_xfer: i2c0-xfer {
758				rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
759						<0 RK_PB2 1 &pcfg_pull_none_smt>;
760			};
761		};
762
763		i2c1 {
764			i2c1_xfer: i2c1-xfer {
765				rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
766						<2 RK_PD4 1 &pcfg_pull_up>;
767			};
768		};
769
770		i2c2m1 {
771			i2c2m1_xfer: i2c2m1-xfer {
772				rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
773						<0 RK_PC6 3 &pcfg_pull_none>;
774			};
775
776			i2c2m1_pins: i2c2m1-pins {
777				rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
778						<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
779			};
780		};
781
782		i2c2m05v {
783			i2c2m05v_xfer: i2c2m05v-xfer {
784				rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
785						<1 RK_PD4 2 &pcfg_pull_none>;
786			};
787
788			i2c2m05v_pins: i2c2m05v-pins {
789				rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
790						<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
791			};
792		};
793
794		i2c3 {
795			i2c3_xfer: i2c3-xfer {
796				rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
797						<0 RK_PC4 2 &pcfg_pull_none>;
798			};
799		};
800
801		pwm0 {
802			pwm0_pin: pwm0-pin {
803				rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
804			};
805		};
806
807		pwm1 {
808			pwm1_pin: pwm1-pin {
809				rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
810			};
811		};
812
813		pwm2 {
814			pwm2_pin: pwm2-pin {
815				rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
816			};
817		};
818
819		pwm3 {
820			pwm3_pin: pwm3-pin {
821				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
822			};
823		};
824
825		pwm4 {
826			pwm4_pin: pwm4-pin {
827				rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
828			};
829		};
830
831		pwm5 {
832			pwm5_pin: pwm5-pin {
833				rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
834			};
835		};
836
837		pwm6 {
838			pwm6_pin: pwm6-pin {
839				rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
840			};
841		};
842
843		pwm7 {
844			pwm7_pin: pwm7-pin {
845				rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
846			};
847		};
848
849		sdmmc {
850			sdmmc_clk: sdmmc-clk {
851				rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
852			};
853
854			sdmmc_cmd: sdmmc-cmd {
855				rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
856			};
857
858			sdmmc_cd: sdmmc-cd {
859				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
860			};
861
862			sdmmc_bus1: sdmmc-bus1 {
863				rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
864			};
865
866			sdmmc_bus4: sdmmc-bus4 {
867				rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
868						<3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
869						<3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
870						<3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
871			};
872		};
873
874		spim0 {
875			spim0_clk: spim0-clk {
876				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
877			};
878
879			spim0_cs0: spim0-cs0 {
880				rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
881			};
882
883			spim0_tx: spim0-tx {
884				rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
885			};
886
887			spim0_rx: spim0-rx {
888				rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
889			};
890		};
891
892		spim1 {
893			spim1_clk: spim1-clk {
894				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
895			};
896
897			spim1_cs0: spim1-cs0 {
898				rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
899			};
900
901			spim1_rx: spim1-rx {
902				rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
903			};
904
905			spim1_tx: spim1-tx {
906				rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
907			};
908		};
909
910		tsadc {
911			otp_out: otp-out {
912				rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
913			};
914
915			otp_pin: otp-pin {
916				rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
917			};
918		};
919
920		uart0 {
921			uart0_xfer: uart0-xfer {
922				rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
923						<3 RK_PA5 1 &pcfg_pull_none>;
924			};
925
926			uart0_cts: uart0-cts {
927				rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
928			};
929
930			uart0_rts: uart0-rts {
931				rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
932			};
933
934			uart0_rts_pin: uart0-rts-pin {
935				rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
936			};
937		};
938
939		uart1 {
940			uart1_xfer: uart1-xfer {
941				rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
942						<1 RK_PD2 1 &pcfg_pull_none>;
943			};
944
945			uart1_cts: uart1-cts {
946				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
947			};
948
949			uart1_rts: uart1-rts {
950				rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
951			};
952		};
953
954		uart2m0 {
955			uart2m0_xfer: uart2m0-xfer {
956				rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
957						<2 RK_PD1 1 &pcfg_pull_none>;
958			};
959		};
960
961		uart2m1 {
962			uart2m1_xfer: uart2m1-xfer {
963				rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
964						<3 RK_PC2 2 &pcfg_pull_none>;
965			};
966		};
967
968		uart2_5v {
969			uart2_5v_cts: uart2_5v-cts {
970				rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
971			};
972
973			uart2_5v_rts: uart2_5v-rts {
974				rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
975			};
976		};
977	};
978};
979