1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3288-cru.h> 8#include <dt-bindings/power/rk3288-power.h> 9#include <dt-bindings/thermal/thermal.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 ethernet0 = &gmac; 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 gpio5 = &gpio5; 28 gpio6 = &gpio6; 29 gpio7 = &gpio7; 30 gpio8 = &gpio8; 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 mshc0 = &emmc; 38 mshc1 = &sdmmc; 39 mshc2 = &sdio0; 40 mshc3 = &sdio1; 41 serial0 = &uart0; 42 serial1 = &uart1; 43 serial2 = &uart2; 44 serial3 = &uart3; 45 serial4 = &uart4; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi2 = &spi2; 49 }; 50 51 arm-pmu { 52 compatible = "arm,cortex-a12-pmu"; 53 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 57 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 enable-method = "rockchip,rk3066-smp"; 64 rockchip,pmu = <&pmu>; 65 66 cpu0: cpu@500 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a12"; 69 reg = <0x500>; 70 resets = <&cru SRST_CORE0>; 71 operating-points-v2 = <&cpu_opp_table>; 72 #cooling-cells = <2>; /* min followed by max */ 73 clock-latency = <40000>; 74 clocks = <&cru ARMCLK>; 75 dynamic-power-coefficient = <370>; 76 }; 77 cpu1: cpu@501 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a12"; 80 reg = <0x501>; 81 resets = <&cru SRST_CORE1>; 82 operating-points-v2 = <&cpu_opp_table>; 83 #cooling-cells = <2>; /* min followed by max */ 84 clock-latency = <40000>; 85 clocks = <&cru ARMCLK>; 86 dynamic-power-coefficient = <370>; 87 }; 88 cpu2: cpu@502 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a12"; 91 reg = <0x502>; 92 resets = <&cru SRST_CORE2>; 93 operating-points-v2 = <&cpu_opp_table>; 94 #cooling-cells = <2>; /* min followed by max */ 95 clock-latency = <40000>; 96 clocks = <&cru ARMCLK>; 97 dynamic-power-coefficient = <370>; 98 }; 99 cpu3: cpu@503 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a12"; 102 reg = <0x503>; 103 resets = <&cru SRST_CORE3>; 104 operating-points-v2 = <&cpu_opp_table>; 105 #cooling-cells = <2>; /* min followed by max */ 106 clock-latency = <40000>; 107 clocks = <&cru ARMCLK>; 108 dynamic-power-coefficient = <370>; 109 }; 110 }; 111 112 cpu_opp_table: opp-table-0 { 113 compatible = "operating-points-v2"; 114 opp-shared; 115 116 opp-126000000 { 117 opp-hz = /bits/ 64 <126000000>; 118 opp-microvolt = <900000>; 119 }; 120 opp-216000000 { 121 opp-hz = /bits/ 64 <216000000>; 122 opp-microvolt = <900000>; 123 }; 124 opp-312000000 { 125 opp-hz = /bits/ 64 <312000000>; 126 opp-microvolt = <900000>; 127 }; 128 opp-408000000 { 129 opp-hz = /bits/ 64 <408000000>; 130 opp-microvolt = <900000>; 131 }; 132 opp-600000000 { 133 opp-hz = /bits/ 64 <600000000>; 134 opp-microvolt = <900000>; 135 }; 136 opp-696000000 { 137 opp-hz = /bits/ 64 <696000000>; 138 opp-microvolt = <950000>; 139 }; 140 opp-816000000 { 141 opp-hz = /bits/ 64 <816000000>; 142 opp-microvolt = <1000000>; 143 }; 144 opp-1008000000 { 145 opp-hz = /bits/ 64 <1008000000>; 146 opp-microvolt = <1050000>; 147 }; 148 opp-1200000000 { 149 opp-hz = /bits/ 64 <1200000000>; 150 opp-microvolt = <1100000>; 151 }; 152 opp-1416000000 { 153 opp-hz = /bits/ 64 <1416000000>; 154 opp-microvolt = <1200000>; 155 }; 156 opp-1512000000 { 157 opp-hz = /bits/ 64 <1512000000>; 158 opp-microvolt = <1300000>; 159 }; 160 opp-1608000000 { 161 opp-hz = /bits/ 64 <1608000000>; 162 opp-microvolt = <1350000>; 163 }; 164 }; 165 166 reserved-memory { 167 #address-cells = <2>; 168 #size-cells = <2>; 169 ranges; 170 171 /* 172 * The rk3288 cannot use the memory area above 0xfe000000 173 * for dma operations for some reason. While there is 174 * probably a better solution available somewhere, we 175 * haven't found it yet and while devices with 2GB of ram 176 * are not affected, this issue prevents 4GB from booting. 177 * So to make these devices at least bootable, block 178 * this area for the time being until the real solution 179 * is found. 180 */ 181 dma-unusable@fe000000 { 182 reg = <0x0 0xfe000000 0x0 0x1000000>; 183 }; 184 }; 185 186 xin24m: oscillator { 187 compatible = "fixed-clock"; 188 clock-frequency = <24000000>; 189 clock-output-names = "xin24m"; 190 #clock-cells = <0>; 191 }; 192 193 timer { 194 compatible = "arm,armv7-timer"; 195 arm,cpu-registers-not-fw-configured; 196 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 197 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 198 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 199 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 200 clock-frequency = <24000000>; 201 arm,no-tick-in-suspend; 202 }; 203 204 timer: timer@ff810000 { 205 compatible = "rockchip,rk3288-timer"; 206 reg = <0x0 0xff810000 0x0 0x20>; 207 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&cru PCLK_TIMER>, <&xin24m>; 209 clock-names = "pclk", "timer"; 210 }; 211 212 display-subsystem { 213 compatible = "rockchip,display-subsystem"; 214 ports = <&vopl_out>, <&vopb_out>; 215 }; 216 217 sdmmc: mmc@ff0c0000 { 218 compatible = "rockchip,rk3288-dw-mshc"; 219 max-frequency = <150000000>; 220 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 221 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 222 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 223 fifo-depth = <0x100>; 224 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 225 reg = <0x0 0xff0c0000 0x0 0x4000>; 226 resets = <&cru SRST_MMC0>; 227 reset-names = "reset"; 228 status = "disabled"; 229 }; 230 231 sdio0: mmc@ff0d0000 { 232 compatible = "rockchip,rk3288-dw-mshc"; 233 max-frequency = <150000000>; 234 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 235 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 237 fifo-depth = <0x100>; 238 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 239 reg = <0x0 0xff0d0000 0x0 0x4000>; 240 resets = <&cru SRST_SDIO0>; 241 reset-names = "reset"; 242 status = "disabled"; 243 }; 244 245 sdio1: mmc@ff0e0000 { 246 compatible = "rockchip,rk3288-dw-mshc"; 247 max-frequency = <150000000>; 248 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 249 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 251 fifo-depth = <0x100>; 252 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 253 reg = <0x0 0xff0e0000 0x0 0x4000>; 254 resets = <&cru SRST_SDIO1>; 255 reset-names = "reset"; 256 status = "disabled"; 257 }; 258 259 emmc: mmc@ff0f0000 { 260 compatible = "rockchip,rk3288-dw-mshc"; 261 max-frequency = <150000000>; 262 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 263 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 265 fifo-depth = <0x100>; 266 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 267 reg = <0x0 0xff0f0000 0x0 0x4000>; 268 resets = <&cru SRST_EMMC>; 269 reset-names = "reset"; 270 status = "disabled"; 271 }; 272 273 saradc: saradc@ff100000 { 274 compatible = "rockchip,saradc"; 275 reg = <0x0 0xff100000 0x0 0x100>; 276 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 277 #io-channel-cells = <1>; 278 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 279 clock-names = "saradc", "apb_pclk"; 280 resets = <&cru SRST_SARADC>; 281 reset-names = "saradc-apb"; 282 status = "disabled"; 283 }; 284 285 spi0: spi@ff110000 { 286 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 287 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 288 clock-names = "spiclk", "apb_pclk"; 289 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 290 dma-names = "tx", "rx"; 291 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 294 reg = <0x0 0xff110000 0x0 0x1000>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 status = "disabled"; 298 }; 299 300 spi1: spi@ff120000 { 301 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 302 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 303 clock-names = "spiclk", "apb_pclk"; 304 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 305 dma-names = "tx", "rx"; 306 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 309 reg = <0x0 0xff120000 0x0 0x1000>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 spi2: spi@ff130000 { 316 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 317 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 318 clock-names = "spiclk", "apb_pclk"; 319 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 320 dma-names = "tx", "rx"; 321 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 324 reg = <0x0 0xff130000 0x0 0x1000>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 status = "disabled"; 328 }; 329 330 i2c1: i2c@ff140000 { 331 compatible = "rockchip,rk3288-i2c"; 332 reg = <0x0 0xff140000 0x0 0x1000>; 333 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 clock-names = "i2c"; 337 clocks = <&cru PCLK_I2C1>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&i2c1_xfer>; 340 status = "disabled"; 341 }; 342 343 i2c3: i2c@ff150000 { 344 compatible = "rockchip,rk3288-i2c"; 345 reg = <0x0 0xff150000 0x0 0x1000>; 346 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 clock-names = "i2c"; 350 clocks = <&cru PCLK_I2C3>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&i2c3_xfer>; 353 status = "disabled"; 354 }; 355 356 i2c4: i2c@ff160000 { 357 compatible = "rockchip,rk3288-i2c"; 358 reg = <0x0 0xff160000 0x0 0x1000>; 359 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 clock-names = "i2c"; 363 clocks = <&cru PCLK_I2C4>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&i2c4_xfer>; 366 status = "disabled"; 367 }; 368 369 i2c5: i2c@ff170000 { 370 compatible = "rockchip,rk3288-i2c"; 371 reg = <0x0 0xff170000 0x0 0x1000>; 372 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 clock-names = "i2c"; 376 clocks = <&cru PCLK_I2C5>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&i2c5_xfer>; 379 status = "disabled"; 380 }; 381 382 uart0: serial@ff180000 { 383 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 384 reg = <0x0 0xff180000 0x0 0x100>; 385 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 386 reg-shift = <2>; 387 reg-io-width = <4>; 388 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 389 clock-names = "baudclk", "apb_pclk"; 390 dmas = <&dmac_peri 1>, <&dmac_peri 2>; 391 dma-names = "tx", "rx"; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&uart0_xfer>; 394 status = "disabled"; 395 }; 396 397 uart1: serial@ff190000 { 398 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 399 reg = <0x0 0xff190000 0x0 0x100>; 400 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 401 reg-shift = <2>; 402 reg-io-width = <4>; 403 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 404 clock-names = "baudclk", "apb_pclk"; 405 dmas = <&dmac_peri 3>, <&dmac_peri 4>; 406 dma-names = "tx", "rx"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&uart1_xfer>; 409 status = "disabled"; 410 }; 411 412 uart2: serial@ff690000 { 413 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 414 reg = <0x0 0xff690000 0x0 0x100>; 415 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 416 reg-shift = <2>; 417 reg-io-width = <4>; 418 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 419 clock-names = "baudclk", "apb_pclk"; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&uart2_xfer>; 422 status = "disabled"; 423 }; 424 425 uart3: serial@ff1b0000 { 426 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 427 reg = <0x0 0xff1b0000 0x0 0x100>; 428 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 429 reg-shift = <2>; 430 reg-io-width = <4>; 431 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 432 clock-names = "baudclk", "apb_pclk"; 433 dmas = <&dmac_peri 7>, <&dmac_peri 8>; 434 dma-names = "tx", "rx"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&uart3_xfer>; 437 status = "disabled"; 438 }; 439 440 uart4: serial@ff1c0000 { 441 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 442 reg = <0x0 0xff1c0000 0x0 0x100>; 443 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 444 reg-shift = <2>; 445 reg-io-width = <4>; 446 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 447 clock-names = "baudclk", "apb_pclk"; 448 dmas = <&dmac_peri 9>, <&dmac_peri 10>; 449 dma-names = "tx", "rx"; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&uart4_xfer>; 452 status = "disabled"; 453 }; 454 455 dmac_peri: dma-controller@ff250000 { 456 compatible = "arm,pl330", "arm,primecell"; 457 reg = <0x0 0xff250000 0x0 0x4000>; 458 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 460 #dma-cells = <1>; 461 arm,pl330-broken-no-flushp; 462 arm,pl330-periph-burst; 463 clocks = <&cru ACLK_DMAC2>; 464 clock-names = "apb_pclk"; 465 }; 466 467 thermal-zones { 468 reserve_thermal: reserve-thermal { 469 polling-delay-passive = <1000>; /* milliseconds */ 470 polling-delay = <5000>; /* milliseconds */ 471 472 thermal-sensors = <&tsadc 0>; 473 }; 474 475 cpu_thermal: cpu-thermal { 476 polling-delay-passive = <100>; /* milliseconds */ 477 polling-delay = <5000>; /* milliseconds */ 478 479 thermal-sensors = <&tsadc 1>; 480 481 trips { 482 cpu_alert0: cpu_alert0 { 483 temperature = <70000>; /* millicelsius */ 484 hysteresis = <2000>; /* millicelsius */ 485 type = "passive"; 486 }; 487 cpu_alert1: cpu_alert1 { 488 temperature = <75000>; /* millicelsius */ 489 hysteresis = <2000>; /* millicelsius */ 490 type = "passive"; 491 }; 492 cpu_crit: cpu_crit { 493 temperature = <90000>; /* millicelsius */ 494 hysteresis = <2000>; /* millicelsius */ 495 type = "critical"; 496 }; 497 }; 498 499 cooling-maps { 500 map0 { 501 trip = <&cpu_alert0>; 502 cooling-device = 503 <&cpu0 THERMAL_NO_LIMIT 6>, 504 <&cpu1 THERMAL_NO_LIMIT 6>, 505 <&cpu2 THERMAL_NO_LIMIT 6>, 506 <&cpu3 THERMAL_NO_LIMIT 6>; 507 }; 508 map1 { 509 trip = <&cpu_alert1>; 510 cooling-device = 511 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 512 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 513 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 514 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 515 }; 516 }; 517 }; 518 519 gpu_thermal: gpu-thermal { 520 polling-delay-passive = <100>; /* milliseconds */ 521 polling-delay = <5000>; /* milliseconds */ 522 523 thermal-sensors = <&tsadc 2>; 524 525 trips { 526 gpu_alert0: gpu_alert0 { 527 temperature = <70000>; /* millicelsius */ 528 hysteresis = <2000>; /* millicelsius */ 529 type = "passive"; 530 }; 531 gpu_crit: gpu_crit { 532 temperature = <90000>; /* millicelsius */ 533 hysteresis = <2000>; /* millicelsius */ 534 type = "critical"; 535 }; 536 }; 537 538 cooling-maps { 539 map0 { 540 trip = <&gpu_alert0>; 541 cooling-device = 542 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 543 }; 544 }; 545 }; 546 }; 547 548 tsadc: tsadc@ff280000 { 549 compatible = "rockchip,rk3288-tsadc"; 550 reg = <0x0 0xff280000 0x0 0x100>; 551 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 553 clock-names = "tsadc", "apb_pclk"; 554 resets = <&cru SRST_TSADC>; 555 reset-names = "tsadc-apb"; 556 pinctrl-names = "init", "default", "sleep"; 557 pinctrl-0 = <&otp_pin>; 558 pinctrl-1 = <&otp_out>; 559 pinctrl-2 = <&otp_pin>; 560 #thermal-sensor-cells = <1>; 561 rockchip,grf = <&grf>; 562 rockchip,hw-tshut-temp = <95000>; 563 status = "disabled"; 564 }; 565 566 gmac: ethernet@ff290000 { 567 compatible = "rockchip,rk3288-gmac"; 568 reg = <0x0 0xff290000 0x0 0x10000>; 569 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 571 interrupt-names = "macirq", "eth_wake_irq"; 572 rockchip,grf = <&grf>; 573 clocks = <&cru SCLK_MAC>, 574 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 575 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 576 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 577 clock-names = "stmmaceth", 578 "mac_clk_rx", "mac_clk_tx", 579 "clk_mac_ref", "clk_mac_refout", 580 "aclk_mac", "pclk_mac"; 581 resets = <&cru SRST_MAC>; 582 reset-names = "stmmaceth"; 583 status = "disabled"; 584 }; 585 586 usb_host0_ehci: usb@ff500000 { 587 compatible = "generic-ehci"; 588 reg = <0x0 0xff500000 0x0 0x100>; 589 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&cru HCLK_USBHOST0>; 591 phys = <&usbphy1>; 592 phy-names = "usb"; 593 status = "disabled"; 594 }; 595 596 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ 597 usb_host0_ohci: usb@ff520000 { 598 compatible = "generic-ohci"; 599 reg = <0x0 0xff520000 0x0 0x100>; 600 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&cru HCLK_USBHOST0>; 602 phys = <&usbphy1>; 603 phy-names = "usb"; 604 status = "disabled"; 605 }; 606 607 usb_host1: usb@ff540000 { 608 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 609 "snps,dwc2"; 610 reg = <0x0 0xff540000 0x0 0x40000>; 611 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cru HCLK_USBHOST1>; 613 clock-names = "otg"; 614 dr_mode = "host"; 615 phys = <&usbphy2>; 616 phy-names = "usb2-phy"; 617 snps,reset-phy-on-wake; 618 status = "disabled"; 619 }; 620 621 usb_otg: usb@ff580000 { 622 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 623 "snps,dwc2"; 624 reg = <0x0 0xff580000 0x0 0x40000>; 625 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cru HCLK_OTG0>; 627 clock-names = "otg"; 628 dr_mode = "otg"; 629 g-np-tx-fifo-size = <16>; 630 g-rx-fifo-size = <275>; 631 g-tx-fifo-size = <256 128 128 64 64 32>; 632 phys = <&usbphy0>; 633 phy-names = "usb2-phy"; 634 status = "disabled"; 635 }; 636 637 usb_hsic: usb@ff5c0000 { 638 compatible = "generic-ehci"; 639 reg = <0x0 0xff5c0000 0x0 0x100>; 640 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&cru HCLK_HSIC>; 642 status = "disabled"; 643 }; 644 645 dmac_bus_ns: dma-controller@ff600000 { 646 compatible = "arm,pl330", "arm,primecell"; 647 reg = <0x0 0xff600000 0x0 0x4000>; 648 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 650 #dma-cells = <1>; 651 arm,pl330-broken-no-flushp; 652 arm,pl330-periph-burst; 653 clocks = <&cru ACLK_DMAC1>; 654 clock-names = "apb_pclk"; 655 status = "disabled"; 656 }; 657 658 i2c0: i2c@ff650000 { 659 compatible = "rockchip,rk3288-i2c"; 660 reg = <0x0 0xff650000 0x0 0x1000>; 661 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 clock-names = "i2c"; 665 clocks = <&cru PCLK_I2C0>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&i2c0_xfer>; 668 status = "disabled"; 669 }; 670 671 i2c2: i2c@ff660000 { 672 compatible = "rockchip,rk3288-i2c"; 673 reg = <0x0 0xff660000 0x0 0x1000>; 674 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 clock-names = "i2c"; 678 clocks = <&cru PCLK_I2C2>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&i2c2_xfer>; 681 status = "disabled"; 682 }; 683 684 pwm0: pwm@ff680000 { 685 compatible = "rockchip,rk3288-pwm"; 686 reg = <0x0 0xff680000 0x0 0x10>; 687 #pwm-cells = <3>; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&pwm0_pin>; 690 clocks = <&cru PCLK_RKPWM>; 691 status = "disabled"; 692 }; 693 694 pwm1: pwm@ff680010 { 695 compatible = "rockchip,rk3288-pwm"; 696 reg = <0x0 0xff680010 0x0 0x10>; 697 #pwm-cells = <3>; 698 pinctrl-names = "default"; 699 pinctrl-0 = <&pwm1_pin>; 700 clocks = <&cru PCLK_RKPWM>; 701 status = "disabled"; 702 }; 703 704 pwm2: pwm@ff680020 { 705 compatible = "rockchip,rk3288-pwm"; 706 reg = <0x0 0xff680020 0x0 0x10>; 707 #pwm-cells = <3>; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&pwm2_pin>; 710 clocks = <&cru PCLK_RKPWM>; 711 status = "disabled"; 712 }; 713 714 pwm3: pwm@ff680030 { 715 compatible = "rockchip,rk3288-pwm"; 716 reg = <0x0 0xff680030 0x0 0x10>; 717 #pwm-cells = <3>; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&pwm3_pin>; 720 clocks = <&cru PCLK_RKPWM>; 721 status = "disabled"; 722 }; 723 724 bus_intmem: sram@ff700000 { 725 compatible = "mmio-sram"; 726 reg = <0x0 0xff700000 0x0 0x18000>; 727 #address-cells = <1>; 728 #size-cells = <1>; 729 ranges = <0 0x0 0xff700000 0x18000>; 730 smp-sram@0 { 731 compatible = "rockchip,rk3066-smp-sram"; 732 reg = <0x00 0x10>; 733 }; 734 }; 735 736 pmu_sram: sram@ff720000 { 737 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 738 reg = <0x0 0xff720000 0x0 0x1000>; 739 }; 740 741 pmu: power-management@ff730000 { 742 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; 743 reg = <0x0 0xff730000 0x0 0x100>; 744 745 power: power-controller { 746 compatible = "rockchip,rk3288-power-controller"; 747 #power-domain-cells = <1>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 751 assigned-clocks = <&cru SCLK_EDP_24M>; 752 assigned-clock-parents = <&xin24m>; 753 754 /* 755 * Note: Although SCLK_* are the working clocks 756 * of device without including on the NOC, needed for 757 * synchronous reset. 758 * 759 * The clocks on the which NOC: 760 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. 761 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. 762 * ACLK_RGA is on ACLK_RGA_NIU. 763 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. 764 * 765 * Which clock are device clocks: 766 * clocks devices 767 * *_IEP IEP:Image Enhancement Processor 768 * *_ISP ISP:Image Signal Processing 769 * *_VIP VIP:Video Input Processor 770 * *_VOP* VOP:Visual Output Processor 771 * *_RGA RGA 772 * *_EDP* EDP 773 * *_LVDS_* LVDS 774 * *_HDMI HDMI 775 * *_MIPI_* MIPI 776 */ 777 power-domain@RK3288_PD_VIO { 778 reg = <RK3288_PD_VIO>; 779 clocks = <&cru ACLK_IEP>, 780 <&cru ACLK_ISP>, 781 <&cru ACLK_RGA>, 782 <&cru ACLK_VIP>, 783 <&cru ACLK_VOP0>, 784 <&cru ACLK_VOP1>, 785 <&cru DCLK_VOP0>, 786 <&cru DCLK_VOP1>, 787 <&cru HCLK_IEP>, 788 <&cru HCLK_ISP>, 789 <&cru HCLK_RGA>, 790 <&cru HCLK_VIP>, 791 <&cru HCLK_VOP0>, 792 <&cru HCLK_VOP1>, 793 <&cru PCLK_EDP_CTRL>, 794 <&cru PCLK_HDMI_CTRL>, 795 <&cru PCLK_LVDS_PHY>, 796 <&cru PCLK_MIPI_CSI>, 797 <&cru PCLK_MIPI_DSI0>, 798 <&cru PCLK_MIPI_DSI1>, 799 <&cru SCLK_EDP_24M>, 800 <&cru SCLK_EDP>, 801 <&cru SCLK_ISP_JPE>, 802 <&cru SCLK_ISP>, 803 <&cru SCLK_RGA>; 804 pm_qos = <&qos_vio0_iep>, 805 <&qos_vio1_vop>, 806 <&qos_vio1_isp_w0>, 807 <&qos_vio1_isp_w1>, 808 <&qos_vio0_vop>, 809 <&qos_vio0_vip>, 810 <&qos_vio2_rga_r>, 811 <&qos_vio2_rga_w>, 812 <&qos_vio1_isp_r>; 813 #power-domain-cells = <0>; 814 }; 815 816 /* 817 * Note: The following 3 are HEVC(H.265) clocks, 818 * and on the ACLK_HEVC_NIU (NOC). 819 */ 820 power-domain@RK3288_PD_HEVC { 821 reg = <RK3288_PD_HEVC>; 822 clocks = <&cru ACLK_HEVC>, 823 <&cru SCLK_HEVC_CABAC>, 824 <&cru SCLK_HEVC_CORE>; 825 pm_qos = <&qos_hevc_r>, 826 <&qos_hevc_w>; 827 #power-domain-cells = <0>; 828 }; 829 830 /* 831 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC 832 * (video endecoder & decoder) clocks that on the 833 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). 834 */ 835 power-domain@RK3288_PD_VIDEO { 836 reg = <RK3288_PD_VIDEO>; 837 clocks = <&cru ACLK_VCODEC>, 838 <&cru HCLK_VCODEC>; 839 pm_qos = <&qos_video>; 840 #power-domain-cells = <0>; 841 }; 842 843 /* 844 * Note: ACLK_GPU is the GPU clock, 845 * and on the ACLK_GPU_NIU (NOC). 846 */ 847 power-domain@RK3288_PD_GPU { 848 reg = <RK3288_PD_GPU>; 849 clocks = <&cru ACLK_GPU>; 850 pm_qos = <&qos_gpu_r>, 851 <&qos_gpu_w>; 852 #power-domain-cells = <0>; 853 }; 854 }; 855 856 reboot-mode { 857 compatible = "syscon-reboot-mode"; 858 offset = <0x94>; 859 mode-normal = <BOOT_NORMAL>; 860 mode-recovery = <BOOT_RECOVERY>; 861 mode-bootloader = <BOOT_FASTBOOT>; 862 mode-loader = <BOOT_BL_DOWNLOAD>; 863 }; 864 }; 865 866 sgrf: syscon@ff740000 { 867 compatible = "rockchip,rk3288-sgrf", "syscon"; 868 reg = <0x0 0xff740000 0x0 0x1000>; 869 }; 870 871 cru: clock-controller@ff760000 { 872 compatible = "rockchip,rk3288-cru"; 873 reg = <0x0 0xff760000 0x0 0x1000>; 874 clocks = <&xin24m>; 875 clock-names = "xin24m"; 876 rockchip,grf = <&grf>; 877 #clock-cells = <1>; 878 #reset-cells = <1>; 879 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 880 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 881 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 882 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 883 <&cru PCLK_PERI>; 884 assigned-clock-rates = <594000000>, <400000000>, 885 <500000000>, <300000000>, 886 <150000000>, <75000000>, 887 <300000000>, <150000000>, 888 <75000000>; 889 }; 890 891 grf: syscon@ff770000 { 892 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 893 reg = <0x0 0xff770000 0x0 0x1000>; 894 895 edp_phy: edp-phy { 896 compatible = "rockchip,rk3288-dp-phy"; 897 clocks = <&cru SCLK_EDP_24M>; 898 clock-names = "24m"; 899 #phy-cells = <0>; 900 status = "disabled"; 901 }; 902 903 io_domains: io-domains { 904 compatible = "rockchip,rk3288-io-voltage-domain"; 905 status = "disabled"; 906 }; 907 908 usbphy: usbphy { 909 compatible = "rockchip,rk3288-usb-phy"; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 status = "disabled"; 913 914 usbphy0: usb-phy@320 { 915 #phy-cells = <0>; 916 reg = <0x320>; 917 clocks = <&cru SCLK_OTGPHY0>; 918 clock-names = "phyclk"; 919 #clock-cells = <0>; 920 resets = <&cru SRST_USBOTG_PHY>; 921 reset-names = "phy-reset"; 922 }; 923 924 usbphy1: usb-phy@334 { 925 #phy-cells = <0>; 926 reg = <0x334>; 927 clocks = <&cru SCLK_OTGPHY1>; 928 clock-names = "phyclk"; 929 #clock-cells = <0>; 930 resets = <&cru SRST_USBHOST0_PHY>; 931 reset-names = "phy-reset"; 932 }; 933 934 usbphy2: usb-phy@348 { 935 #phy-cells = <0>; 936 reg = <0x348>; 937 clocks = <&cru SCLK_OTGPHY2>; 938 clock-names = "phyclk"; 939 #clock-cells = <0>; 940 resets = <&cru SRST_USBHOST1_PHY>; 941 reset-names = "phy-reset"; 942 }; 943 }; 944 }; 945 946 wdt: watchdog@ff800000 { 947 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 948 reg = <0x0 0xff800000 0x0 0x100>; 949 clocks = <&cru PCLK_WDT>; 950 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 951 status = "disabled"; 952 }; 953 954 spdif: sound@ff8b0000 { 955 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 956 reg = <0x0 0xff8b0000 0x0 0x10000>; 957 #sound-dai-cells = <0>; 958 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; 959 clock-names = "mclk", "hclk"; 960 dmas = <&dmac_bus_s 3>; 961 dma-names = "tx"; 962 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&spdif_tx>; 965 rockchip,grf = <&grf>; 966 status = "disabled"; 967 }; 968 969 i2s: i2s@ff890000 { 970 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 971 reg = <0x0 0xff890000 0x0 0x10000>; 972 #sound-dai-cells = <0>; 973 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 975 clock-names = "i2s_clk", "i2s_hclk"; 976 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 977 dma-names = "tx", "rx"; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&i2s0_bus>; 980 rockchip,playback-channels = <8>; 981 rockchip,capture-channels = <2>; 982 status = "disabled"; 983 }; 984 985 crypto: crypto@ff8a0000 { 986 compatible = "rockchip,rk3288-crypto"; 987 reg = <0x0 0xff8a0000 0x0 0x4000>; 988 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 990 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; 991 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 992 resets = <&cru SRST_CRYPTO>; 993 reset-names = "crypto-rst"; 994 }; 995 996 iep_mmu: iommu@ff900800 { 997 compatible = "rockchip,iommu"; 998 reg = <0x0 0xff900800 0x0 0x40>; 999 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1001 clock-names = "aclk", "iface"; 1002 #iommu-cells = <0>; 1003 status = "disabled"; 1004 }; 1005 1006 isp_mmu: iommu@ff914000 { 1007 compatible = "rockchip,iommu"; 1008 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1009 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1011 clock-names = "aclk", "iface"; 1012 #iommu-cells = <0>; 1013 rockchip,disable-mmu-reset; 1014 status = "disabled"; 1015 }; 1016 1017 rga: rga@ff920000 { 1018 compatible = "rockchip,rk3288-rga"; 1019 reg = <0x0 0xff920000 0x0 0x180>; 1020 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 1022 clock-names = "aclk", "hclk", "sclk"; 1023 power-domains = <&power RK3288_PD_VIO>; 1024 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; 1025 reset-names = "core", "axi", "ahb"; 1026 }; 1027 1028 vopb: vop@ff930000 { 1029 compatible = "rockchip,rk3288-vop"; 1030 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; 1031 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1033 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1034 power-domains = <&power RK3288_PD_VIO>; 1035 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 1036 reset-names = "axi", "ahb", "dclk"; 1037 iommus = <&vopb_mmu>; 1038 status = "disabled"; 1039 1040 vopb_out: port { 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 1044 vopb_out_hdmi: endpoint@0 { 1045 reg = <0>; 1046 remote-endpoint = <&hdmi_in_vopb>; 1047 }; 1048 1049 vopb_out_edp: endpoint@1 { 1050 reg = <1>; 1051 remote-endpoint = <&edp_in_vopb>; 1052 }; 1053 1054 vopb_out_mipi: endpoint@2 { 1055 reg = <2>; 1056 remote-endpoint = <&mipi_in_vopb>; 1057 }; 1058 1059 vopb_out_lvds: endpoint@3 { 1060 reg = <3>; 1061 remote-endpoint = <&lvds_in_vopb>; 1062 }; 1063 }; 1064 }; 1065 1066 vopb_mmu: iommu@ff930300 { 1067 compatible = "rockchip,iommu"; 1068 reg = <0x0 0xff930300 0x0 0x100>; 1069 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1071 clock-names = "aclk", "iface"; 1072 power-domains = <&power RK3288_PD_VIO>; 1073 #iommu-cells = <0>; 1074 status = "disabled"; 1075 }; 1076 1077 vopl: vop@ff940000 { 1078 compatible = "rockchip,rk3288-vop"; 1079 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; 1080 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1082 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1083 power-domains = <&power RK3288_PD_VIO>; 1084 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 1085 reset-names = "axi", "ahb", "dclk"; 1086 iommus = <&vopl_mmu>; 1087 status = "disabled"; 1088 1089 vopl_out: port { 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 1093 vopl_out_hdmi: endpoint@0 { 1094 reg = <0>; 1095 remote-endpoint = <&hdmi_in_vopl>; 1096 }; 1097 1098 vopl_out_edp: endpoint@1 { 1099 reg = <1>; 1100 remote-endpoint = <&edp_in_vopl>; 1101 }; 1102 1103 vopl_out_mipi: endpoint@2 { 1104 reg = <2>; 1105 remote-endpoint = <&mipi_in_vopl>; 1106 }; 1107 1108 vopl_out_lvds: endpoint@3 { 1109 reg = <3>; 1110 remote-endpoint = <&lvds_in_vopl>; 1111 }; 1112 }; 1113 }; 1114 1115 vopl_mmu: iommu@ff940300 { 1116 compatible = "rockchip,iommu"; 1117 reg = <0x0 0xff940300 0x0 0x100>; 1118 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1120 clock-names = "aclk", "iface"; 1121 power-domains = <&power RK3288_PD_VIO>; 1122 #iommu-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 mipi_dsi: dsi@ff960000 { 1127 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 1128 reg = <0x0 0xff960000 0x0 0x4000>; 1129 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 1131 clock-names = "ref", "pclk"; 1132 power-domains = <&power RK3288_PD_VIO>; 1133 rockchip,grf = <&grf>; 1134 status = "disabled"; 1135 1136 ports { 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 1140 mipi_in: port@0 { 1141 reg = <0>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 1145 mipi_in_vopb: endpoint@0 { 1146 reg = <0>; 1147 remote-endpoint = <&vopb_out_mipi>; 1148 }; 1149 1150 mipi_in_vopl: endpoint@1 { 1151 reg = <1>; 1152 remote-endpoint = <&vopl_out_mipi>; 1153 }; 1154 }; 1155 1156 mipi_out: port@1 { 1157 reg = <1>; 1158 }; 1159 }; 1160 }; 1161 1162 lvds: lvds@ff96c000 { 1163 compatible = "rockchip,rk3288-lvds"; 1164 reg = <0x0 0xff96c000 0x0 0x4000>; 1165 clocks = <&cru PCLK_LVDS_PHY>; 1166 clock-names = "pclk_lvds"; 1167 pinctrl-names = "lcdc"; 1168 pinctrl-0 = <&lcdc_ctl>; 1169 power-domains = <&power RK3288_PD_VIO>; 1170 rockchip,grf = <&grf>; 1171 status = "disabled"; 1172 1173 ports { 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 1177 lvds_in: port@0 { 1178 reg = <0>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 1182 lvds_in_vopb: endpoint@0 { 1183 reg = <0>; 1184 remote-endpoint = <&vopb_out_lvds>; 1185 }; 1186 1187 lvds_in_vopl: endpoint@1 { 1188 reg = <1>; 1189 remote-endpoint = <&vopl_out_lvds>; 1190 }; 1191 }; 1192 1193 lvds_out: port@1 { 1194 reg = <1>; 1195 }; 1196 }; 1197 }; 1198 1199 edp: dp@ff970000 { 1200 compatible = "rockchip,rk3288-dp"; 1201 reg = <0x0 0xff970000 0x0 0x4000>; 1202 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1204 clock-names = "dp", "pclk"; 1205 phys = <&edp_phy>; 1206 phy-names = "dp"; 1207 power-domains = <&power RK3288_PD_VIO>; 1208 resets = <&cru SRST_EDP>; 1209 reset-names = "dp"; 1210 rockchip,grf = <&grf>; 1211 status = "disabled"; 1212 1213 ports { 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 1217 edp_in: port@0 { 1218 reg = <0>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 1222 edp_in_vopb: endpoint@0 { 1223 reg = <0>; 1224 remote-endpoint = <&vopb_out_edp>; 1225 }; 1226 1227 edp_in_vopl: endpoint@1 { 1228 reg = <1>; 1229 remote-endpoint = <&vopl_out_edp>; 1230 }; 1231 }; 1232 1233 edp_out: port@1 { 1234 reg = <1>; 1235 }; 1236 }; 1237 }; 1238 1239 hdmi: hdmi@ff980000 { 1240 compatible = "rockchip,rk3288-dw-hdmi"; 1241 reg = <0x0 0xff980000 0x0 0x20000>; 1242 reg-io-width = <4>; 1243 #sound-dai-cells = <0>; 1244 rockchip,grf = <&grf>; 1245 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 1247 clock-names = "iahb", "isfr", "cec"; 1248 power-domains = <&power RK3288_PD_VIO>; 1249 status = "disabled"; 1250 1251 ports { 1252 hdmi_in: port { 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 hdmi_in_vopb: endpoint@0 { 1256 reg = <0>; 1257 remote-endpoint = <&vopb_out_hdmi>; 1258 }; 1259 hdmi_in_vopl: endpoint@1 { 1260 reg = <1>; 1261 remote-endpoint = <&vopl_out_hdmi>; 1262 }; 1263 }; 1264 }; 1265 }; 1266 1267 vpu: video-codec@ff9a0000 { 1268 compatible = "rockchip,rk3288-vpu"; 1269 reg = <0x0 0xff9a0000 0x0 0x800>; 1270 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1272 interrupt-names = "vepu", "vdpu"; 1273 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1274 clock-names = "aclk", "hclk"; 1275 iommus = <&vpu_mmu>; 1276 power-domains = <&power RK3288_PD_VIDEO>; 1277 }; 1278 1279 vpu_mmu: iommu@ff9a0800 { 1280 compatible = "rockchip,iommu"; 1281 reg = <0x0 0xff9a0800 0x0 0x100>; 1282 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1284 clock-names = "aclk", "iface"; 1285 #iommu-cells = <0>; 1286 power-domains = <&power RK3288_PD_VIDEO>; 1287 }; 1288 1289 hevc_mmu: iommu@ff9c0440 { 1290 compatible = "rockchip,iommu"; 1291 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; 1292 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; 1294 clock-names = "aclk", "iface"; 1295 #iommu-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 gpu: gpu@ffa30000 { 1300 compatible = "rockchip,rk3288-mali", "arm,mali-t760"; 1301 reg = <0x0 0xffa30000 0x0 0x10000>; 1302 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1305 interrupt-names = "job", "mmu", "gpu"; 1306 clocks = <&cru ACLK_GPU>; 1307 operating-points-v2 = <&gpu_opp_table>; 1308 #cooling-cells = <2>; /* min followed by max */ 1309 power-domains = <&power RK3288_PD_GPU>; 1310 status = "disabled"; 1311 }; 1312 1313 gpu_opp_table: opp-table-1 { 1314 compatible = "operating-points-v2"; 1315 1316 opp-100000000 { 1317 opp-hz = /bits/ 64 <100000000>; 1318 opp-microvolt = <950000>; 1319 }; 1320 opp-200000000 { 1321 opp-hz = /bits/ 64 <200000000>; 1322 opp-microvolt = <950000>; 1323 }; 1324 opp-300000000 { 1325 opp-hz = /bits/ 64 <300000000>; 1326 opp-microvolt = <1000000>; 1327 }; 1328 opp-400000000 { 1329 opp-hz = /bits/ 64 <400000000>; 1330 opp-microvolt = <1100000>; 1331 }; 1332 opp-600000000 { 1333 opp-hz = /bits/ 64 <600000000>; 1334 opp-microvolt = <1250000>; 1335 }; 1336 }; 1337 1338 qos_gpu_r: qos@ffaa0000 { 1339 compatible = "rockchip,rk3288-qos", "syscon"; 1340 reg = <0x0 0xffaa0000 0x0 0x20>; 1341 }; 1342 1343 qos_gpu_w: qos@ffaa0080 { 1344 compatible = "rockchip,rk3288-qos", "syscon"; 1345 reg = <0x0 0xffaa0080 0x0 0x20>; 1346 }; 1347 1348 qos_vio1_vop: qos@ffad0000 { 1349 compatible = "rockchip,rk3288-qos", "syscon"; 1350 reg = <0x0 0xffad0000 0x0 0x20>; 1351 }; 1352 1353 qos_vio1_isp_w0: qos@ffad0100 { 1354 compatible = "rockchip,rk3288-qos", "syscon"; 1355 reg = <0x0 0xffad0100 0x0 0x20>; 1356 }; 1357 1358 qos_vio1_isp_w1: qos@ffad0180 { 1359 compatible = "rockchip,rk3288-qos", "syscon"; 1360 reg = <0x0 0xffad0180 0x0 0x20>; 1361 }; 1362 1363 qos_vio0_vop: qos@ffad0400 { 1364 compatible = "rockchip,rk3288-qos", "syscon"; 1365 reg = <0x0 0xffad0400 0x0 0x20>; 1366 }; 1367 1368 qos_vio0_vip: qos@ffad0480 { 1369 compatible = "rockchip,rk3288-qos", "syscon"; 1370 reg = <0x0 0xffad0480 0x0 0x20>; 1371 }; 1372 1373 qos_vio0_iep: qos@ffad0500 { 1374 compatible = "rockchip,rk3288-qos", "syscon"; 1375 reg = <0x0 0xffad0500 0x0 0x20>; 1376 }; 1377 1378 qos_vio2_rga_r: qos@ffad0800 { 1379 compatible = "rockchip,rk3288-qos", "syscon"; 1380 reg = <0x0 0xffad0800 0x0 0x20>; 1381 }; 1382 1383 qos_vio2_rga_w: qos@ffad0880 { 1384 compatible = "rockchip,rk3288-qos", "syscon"; 1385 reg = <0x0 0xffad0880 0x0 0x20>; 1386 }; 1387 1388 qos_vio1_isp_r: qos@ffad0900 { 1389 compatible = "rockchip,rk3288-qos", "syscon"; 1390 reg = <0x0 0xffad0900 0x0 0x20>; 1391 }; 1392 1393 qos_video: qos@ffae0000 { 1394 compatible = "rockchip,rk3288-qos", "syscon"; 1395 reg = <0x0 0xffae0000 0x0 0x20>; 1396 }; 1397 1398 qos_hevc_r: qos@ffaf0000 { 1399 compatible = "rockchip,rk3288-qos", "syscon"; 1400 reg = <0x0 0xffaf0000 0x0 0x20>; 1401 }; 1402 1403 qos_hevc_w: qos@ffaf0080 { 1404 compatible = "rockchip,rk3288-qos", "syscon"; 1405 reg = <0x0 0xffaf0080 0x0 0x20>; 1406 }; 1407 1408 dmac_bus_s: dma-controller@ffb20000 { 1409 compatible = "arm,pl330", "arm,primecell"; 1410 reg = <0x0 0xffb20000 0x0 0x4000>; 1411 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1413 #dma-cells = <1>; 1414 arm,pl330-broken-no-flushp; 1415 arm,pl330-periph-burst; 1416 clocks = <&cru ACLK_DMAC1>; 1417 clock-names = "apb_pclk"; 1418 }; 1419 1420 efuse: efuse@ffb40000 { 1421 compatible = "rockchip,rk3288-efuse"; 1422 reg = <0x0 0xffb40000 0x0 0x20>; 1423 #address-cells = <1>; 1424 #size-cells = <1>; 1425 clocks = <&cru PCLK_EFUSE256>; 1426 clock-names = "pclk_efuse"; 1427 1428 cpu_id: cpu-id@7 { 1429 reg = <0x07 0x10>; 1430 }; 1431 cpu_leakage: cpu_leakage@17 { 1432 reg = <0x17 0x1>; 1433 }; 1434 }; 1435 1436 gic: interrupt-controller@ffc01000 { 1437 compatible = "arm,gic-400"; 1438 interrupt-controller; 1439 #interrupt-cells = <3>; 1440 #address-cells = <0>; 1441 1442 reg = <0x0 0xffc01000 0x0 0x1000>, 1443 <0x0 0xffc02000 0x0 0x2000>, 1444 <0x0 0xffc04000 0x0 0x2000>, 1445 <0x0 0xffc06000 0x0 0x2000>; 1446 interrupts = <GIC_PPI 9 0xf04>; 1447 }; 1448 1449 pinctrl: pinctrl { 1450 compatible = "rockchip,rk3288-pinctrl"; 1451 rockchip,grf = <&grf>; 1452 rockchip,pmu = <&pmu>; 1453 #address-cells = <2>; 1454 #size-cells = <2>; 1455 ranges; 1456 1457 gpio0: gpio@ff750000 { 1458 compatible = "rockchip,gpio-bank"; 1459 reg = <0x0 0xff750000 0x0 0x100>; 1460 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1461 clocks = <&cru PCLK_GPIO0>; 1462 1463 gpio-controller; 1464 #gpio-cells = <2>; 1465 1466 interrupt-controller; 1467 #interrupt-cells = <2>; 1468 }; 1469 1470 gpio1: gpio@ff780000 { 1471 compatible = "rockchip,gpio-bank"; 1472 reg = <0x0 0xff780000 0x0 0x100>; 1473 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1474 clocks = <&cru PCLK_GPIO1>; 1475 1476 gpio-controller; 1477 #gpio-cells = <2>; 1478 1479 interrupt-controller; 1480 #interrupt-cells = <2>; 1481 }; 1482 1483 gpio2: gpio@ff790000 { 1484 compatible = "rockchip,gpio-bank"; 1485 reg = <0x0 0xff790000 0x0 0x100>; 1486 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1487 clocks = <&cru PCLK_GPIO2>; 1488 1489 gpio-controller; 1490 #gpio-cells = <2>; 1491 1492 interrupt-controller; 1493 #interrupt-cells = <2>; 1494 }; 1495 1496 gpio3: gpio@ff7a0000 { 1497 compatible = "rockchip,gpio-bank"; 1498 reg = <0x0 0xff7a0000 0x0 0x100>; 1499 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1500 clocks = <&cru PCLK_GPIO3>; 1501 1502 gpio-controller; 1503 #gpio-cells = <2>; 1504 1505 interrupt-controller; 1506 #interrupt-cells = <2>; 1507 }; 1508 1509 gpio4: gpio@ff7b0000 { 1510 compatible = "rockchip,gpio-bank"; 1511 reg = <0x0 0xff7b0000 0x0 0x100>; 1512 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1513 clocks = <&cru PCLK_GPIO4>; 1514 1515 gpio-controller; 1516 #gpio-cells = <2>; 1517 1518 interrupt-controller; 1519 #interrupt-cells = <2>; 1520 }; 1521 1522 gpio5: gpio@ff7c0000 { 1523 compatible = "rockchip,gpio-bank"; 1524 reg = <0x0 0xff7c0000 0x0 0x100>; 1525 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1526 clocks = <&cru PCLK_GPIO5>; 1527 1528 gpio-controller; 1529 #gpio-cells = <2>; 1530 1531 interrupt-controller; 1532 #interrupt-cells = <2>; 1533 }; 1534 1535 gpio6: gpio@ff7d0000 { 1536 compatible = "rockchip,gpio-bank"; 1537 reg = <0x0 0xff7d0000 0x0 0x100>; 1538 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1539 clocks = <&cru PCLK_GPIO6>; 1540 1541 gpio-controller; 1542 #gpio-cells = <2>; 1543 1544 interrupt-controller; 1545 #interrupt-cells = <2>; 1546 }; 1547 1548 gpio7: gpio@ff7e0000 { 1549 compatible = "rockchip,gpio-bank"; 1550 reg = <0x0 0xff7e0000 0x0 0x100>; 1551 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1552 clocks = <&cru PCLK_GPIO7>; 1553 1554 gpio-controller; 1555 #gpio-cells = <2>; 1556 1557 interrupt-controller; 1558 #interrupt-cells = <2>; 1559 }; 1560 1561 gpio8: gpio@ff7f0000 { 1562 compatible = "rockchip,gpio-bank"; 1563 reg = <0x0 0xff7f0000 0x0 0x100>; 1564 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&cru PCLK_GPIO8>; 1566 1567 gpio-controller; 1568 #gpio-cells = <2>; 1569 1570 interrupt-controller; 1571 #interrupt-cells = <2>; 1572 }; 1573 1574 hdmi { 1575 hdmi_cec_c0: hdmi-cec-c0 { 1576 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; 1577 }; 1578 1579 hdmi_cec_c7: hdmi-cec-c7 { 1580 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; 1581 }; 1582 1583 hdmi_ddc: hdmi-ddc { 1584 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, 1585 <7 RK_PC4 2 &pcfg_pull_none>; 1586 }; 1587 1588 hdmi_ddc_unwedge: hdmi-ddc-unwedge { 1589 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, 1590 <7 RK_PC4 2 &pcfg_pull_none>; 1591 }; 1592 }; 1593 1594 pcfg_output_low: pcfg-output-low { 1595 output-low; 1596 }; 1597 1598 pcfg_pull_up: pcfg-pull-up { 1599 bias-pull-up; 1600 }; 1601 1602 pcfg_pull_down: pcfg-pull-down { 1603 bias-pull-down; 1604 }; 1605 1606 pcfg_pull_none: pcfg-pull-none { 1607 bias-disable; 1608 }; 1609 1610 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1611 bias-disable; 1612 drive-strength = <12>; 1613 }; 1614 1615 suspend { 1616 global_pwroff: global-pwroff { 1617 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; 1618 }; 1619 1620 ddrio_pwroff: ddrio-pwroff { 1621 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 1622 }; 1623 1624 ddr0_retention: ddr0-retention { 1625 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; 1626 }; 1627 1628 ddr1_retention: ddr1-retention { 1629 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; 1630 }; 1631 }; 1632 1633 edp { 1634 edp_hpd: edp-hpd { 1635 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; 1636 }; 1637 }; 1638 1639 i2c0 { 1640 i2c0_xfer: i2c0-xfer { 1641 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, 1642 <0 RK_PC0 1 &pcfg_pull_none>; 1643 }; 1644 }; 1645 1646 i2c1 { 1647 i2c1_xfer: i2c1-xfer { 1648 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, 1649 <8 RK_PA5 1 &pcfg_pull_none>; 1650 }; 1651 }; 1652 1653 i2c2 { 1654 i2c2_xfer: i2c2-xfer { 1655 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, 1656 <6 RK_PB2 1 &pcfg_pull_none>; 1657 }; 1658 }; 1659 1660 i2c3 { 1661 i2c3_xfer: i2c3-xfer { 1662 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, 1663 <2 RK_PC1 1 &pcfg_pull_none>; 1664 }; 1665 }; 1666 1667 i2c4 { 1668 i2c4_xfer: i2c4-xfer { 1669 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, 1670 <7 RK_PC2 1 &pcfg_pull_none>; 1671 }; 1672 }; 1673 1674 i2c5 { 1675 i2c5_xfer: i2c5-xfer { 1676 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, 1677 <7 RK_PC4 1 &pcfg_pull_none>; 1678 }; 1679 }; 1680 1681 i2s0 { 1682 i2s0_bus: i2s0-bus { 1683 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, 1684 <6 RK_PA1 1 &pcfg_pull_none>, 1685 <6 RK_PA2 1 &pcfg_pull_none>, 1686 <6 RK_PA3 1 &pcfg_pull_none>, 1687 <6 RK_PA4 1 &pcfg_pull_none>, 1688 <6 RK_PB0 1 &pcfg_pull_none>; 1689 }; 1690 }; 1691 1692 lcdc { 1693 lcdc_ctl: lcdc-ctl { 1694 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1695 <1 RK_PD1 1 &pcfg_pull_none>, 1696 <1 RK_PD2 1 &pcfg_pull_none>, 1697 <1 RK_PD3 1 &pcfg_pull_none>; 1698 }; 1699 }; 1700 1701 sdmmc { 1702 sdmmc_clk: sdmmc-clk { 1703 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; 1704 }; 1705 1706 sdmmc_cmd: sdmmc-cmd { 1707 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; 1708 }; 1709 1710 sdmmc_cd: sdmmc-cd { 1711 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; 1712 }; 1713 1714 sdmmc_bus1: sdmmc-bus1 { 1715 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; 1716 }; 1717 1718 sdmmc_bus4: sdmmc-bus4 { 1719 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, 1720 <6 RK_PC1 1 &pcfg_pull_up>, 1721 <6 RK_PC2 1 &pcfg_pull_up>, 1722 <6 RK_PC3 1 &pcfg_pull_up>; 1723 }; 1724 }; 1725 1726 sdio0 { 1727 sdio0_bus1: sdio0-bus1 { 1728 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; 1729 }; 1730 1731 sdio0_bus4: sdio0-bus4 { 1732 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, 1733 <4 RK_PC5 1 &pcfg_pull_up>, 1734 <4 RK_PC6 1 &pcfg_pull_up>, 1735 <4 RK_PC7 1 &pcfg_pull_up>; 1736 }; 1737 1738 sdio0_cmd: sdio0-cmd { 1739 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; 1740 }; 1741 1742 sdio0_clk: sdio0-clk { 1743 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; 1744 }; 1745 1746 sdio0_cd: sdio0-cd { 1747 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; 1748 }; 1749 1750 sdio0_wp: sdio0-wp { 1751 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; 1752 }; 1753 1754 sdio0_pwr: sdio0-pwr { 1755 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; 1756 }; 1757 1758 sdio0_bkpwr: sdio0-bkpwr { 1759 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; 1760 }; 1761 1762 sdio0_int: sdio0-int { 1763 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; 1764 }; 1765 }; 1766 1767 sdio1 { 1768 sdio1_bus1: sdio1-bus1 { 1769 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; 1770 }; 1771 1772 sdio1_bus4: sdio1-bus4 { 1773 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, 1774 <3 RK_PD1 4 &pcfg_pull_up>, 1775 <3 RK_PD2 4 &pcfg_pull_up>, 1776 <3 RK_PD3 4 &pcfg_pull_up>; 1777 }; 1778 1779 sdio1_cd: sdio1-cd { 1780 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; 1781 }; 1782 1783 sdio1_wp: sdio1-wp { 1784 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; 1785 }; 1786 1787 sdio1_bkpwr: sdio1-bkpwr { 1788 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; 1789 }; 1790 1791 sdio1_int: sdio1-int { 1792 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; 1793 }; 1794 1795 sdio1_cmd: sdio1-cmd { 1796 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; 1797 }; 1798 1799 sdio1_clk: sdio1-clk { 1800 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; 1801 }; 1802 1803 sdio1_pwr: sdio1-pwr { 1804 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; 1805 }; 1806 }; 1807 1808 emmc { 1809 emmc_clk: emmc-clk { 1810 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; 1811 }; 1812 1813 emmc_cmd: emmc-cmd { 1814 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; 1815 }; 1816 1817 emmc_pwr: emmc-pwr { 1818 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; 1819 }; 1820 1821 emmc_bus1: emmc-bus1 { 1822 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; 1823 }; 1824 1825 emmc_bus4: emmc-bus4 { 1826 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1827 <3 RK_PA1 2 &pcfg_pull_up>, 1828 <3 RK_PA2 2 &pcfg_pull_up>, 1829 <3 RK_PA3 2 &pcfg_pull_up>; 1830 }; 1831 1832 emmc_bus8: emmc-bus8 { 1833 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1834 <3 RK_PA1 2 &pcfg_pull_up>, 1835 <3 RK_PA2 2 &pcfg_pull_up>, 1836 <3 RK_PA3 2 &pcfg_pull_up>, 1837 <3 RK_PA4 2 &pcfg_pull_up>, 1838 <3 RK_PA5 2 &pcfg_pull_up>, 1839 <3 RK_PA6 2 &pcfg_pull_up>, 1840 <3 RK_PA7 2 &pcfg_pull_up>; 1841 }; 1842 }; 1843 1844 spi0 { 1845 spi0_clk: spi0-clk { 1846 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; 1847 }; 1848 spi0_cs0: spi0-cs0 { 1849 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; 1850 }; 1851 spi0_tx: spi0-tx { 1852 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; 1853 }; 1854 spi0_rx: spi0-rx { 1855 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; 1856 }; 1857 spi0_cs1: spi0-cs1 { 1858 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; 1859 }; 1860 }; 1861 spi1 { 1862 spi1_clk: spi1-clk { 1863 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; 1864 }; 1865 spi1_cs0: spi1-cs0 { 1866 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; 1867 }; 1868 spi1_rx: spi1-rx { 1869 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; 1870 }; 1871 spi1_tx: spi1-tx { 1872 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; 1873 }; 1874 }; 1875 1876 spi2 { 1877 spi2_cs1: spi2-cs1 { 1878 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; 1879 }; 1880 spi2_clk: spi2-clk { 1881 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; 1882 }; 1883 spi2_cs0: spi2-cs0 { 1884 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; 1885 }; 1886 spi2_rx: spi2-rx { 1887 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; 1888 }; 1889 spi2_tx: spi2-tx { 1890 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; 1891 }; 1892 }; 1893 1894 uart0 { 1895 uart0_xfer: uart0-xfer { 1896 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, 1897 <4 RK_PC1 1 &pcfg_pull_none>; 1898 }; 1899 1900 uart0_cts: uart0-cts { 1901 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; 1902 }; 1903 1904 uart0_rts: uart0-rts { 1905 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; 1906 }; 1907 }; 1908 1909 uart1 { 1910 uart1_xfer: uart1-xfer { 1911 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, 1912 <5 RK_PB1 1 &pcfg_pull_none>; 1913 }; 1914 1915 uart1_cts: uart1-cts { 1916 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; 1917 }; 1918 1919 uart1_rts: uart1-rts { 1920 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; 1921 }; 1922 }; 1923 1924 uart2 { 1925 uart2_xfer: uart2-xfer { 1926 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, 1927 <7 RK_PC7 1 &pcfg_pull_none>; 1928 }; 1929 /* no rts / cts for uart2 */ 1930 }; 1931 1932 uart3 { 1933 uart3_xfer: uart3-xfer { 1934 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, 1935 <7 RK_PB0 1 &pcfg_pull_none>; 1936 }; 1937 1938 uart3_cts: uart3-cts { 1939 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; 1940 }; 1941 1942 uart3_rts: uart3-rts { 1943 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; 1944 }; 1945 }; 1946 1947 uart4 { 1948 uart4_xfer: uart4-xfer { 1949 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, 1950 <5 RK_PB6 3 &pcfg_pull_none>; 1951 }; 1952 1953 uart4_cts: uart4-cts { 1954 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; 1955 }; 1956 1957 uart4_rts: uart4-rts { 1958 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; 1959 }; 1960 }; 1961 1962 tsadc { 1963 otp_pin: otp-pin { 1964 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1965 }; 1966 1967 otp_out: otp-out { 1968 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; 1969 }; 1970 }; 1971 1972 pwm0 { 1973 pwm0_pin: pwm0-pin { 1974 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; 1975 }; 1976 }; 1977 1978 pwm1 { 1979 pwm1_pin: pwm1-pin { 1980 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; 1981 }; 1982 }; 1983 1984 pwm2 { 1985 pwm2_pin: pwm2-pin { 1986 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; 1987 }; 1988 }; 1989 1990 pwm3 { 1991 pwm3_pin: pwm3-pin { 1992 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; 1993 }; 1994 }; 1995 1996 gmac { 1997 rgmii_pins: rgmii-pins { 1998 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 1999 <3 RK_PD7 3 &pcfg_pull_none>, 2000 <3 RK_PD2 3 &pcfg_pull_none>, 2001 <3 RK_PD3 3 &pcfg_pull_none>, 2002 <3 RK_PD4 3 &pcfg_pull_none_12ma>, 2003 <3 RK_PD5 3 &pcfg_pull_none_12ma>, 2004 <3 RK_PD0 3 &pcfg_pull_none_12ma>, 2005 <3 RK_PD1 3 &pcfg_pull_none_12ma>, 2006 <4 RK_PA0 3 &pcfg_pull_none>, 2007 <4 RK_PA5 3 &pcfg_pull_none>, 2008 <4 RK_PA6 3 &pcfg_pull_none>, 2009 <4 RK_PB1 3 &pcfg_pull_none_12ma>, 2010 <4 RK_PA4 3 &pcfg_pull_none_12ma>, 2011 <4 RK_PA1 3 &pcfg_pull_none>, 2012 <4 RK_PA3 3 &pcfg_pull_none>; 2013 }; 2014 2015 rmii_pins: rmii-pins { 2016 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 2017 <3 RK_PD7 3 &pcfg_pull_none>, 2018 <3 RK_PD4 3 &pcfg_pull_none>, 2019 <3 RK_PD5 3 &pcfg_pull_none>, 2020 <4 RK_PA0 3 &pcfg_pull_none>, 2021 <4 RK_PA5 3 &pcfg_pull_none>, 2022 <4 RK_PA4 3 &pcfg_pull_none>, 2023 <4 RK_PA1 3 &pcfg_pull_none>, 2024 <4 RK_PA2 3 &pcfg_pull_none>, 2025 <4 RK_PA3 3 &pcfg_pull_none>; 2026 }; 2027 }; 2028 2029 spdif { 2030 spdif_tx: spdif-tx { 2031 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; 2032 }; 2033 }; 2034 }; 2035}; 2036