1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Veyron Mickey Rev 0 board device tree source 4 * 5 * Copyright 2015 Google, Inc 6 */ 7 8/dts-v1/; 9#include "rk3288-veyron.dtsi" 10#include "rk3288-veyron-broadcom-bluetooth.dtsi" 11 12/ { 13 model = "Google Mickey"; 14 compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", 15 "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", 16 "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", 17 "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", 18 "google,veyron-mickey-rev0", "google,veyron-mickey", 19 "google,veyron", "rockchip,rk3288"; 20 21 vcc_5v: vcc-5v { 22 vin-supply = <&vcc33_sys>; 23 }; 24 25 vcc33_io: vcc33_io { 26 compatible = "regulator-fixed"; 27 regulator-name = "vcc33_io"; 28 regulator-always-on; 29 regulator-boot-on; 30 vin-supply = <&vcc33_sys>; 31 }; 32 33 sound { 34 compatible = "rockchip,rockchip-audio-max98090"; 35 rockchip,model = "VEYRON-HDMI"; 36 rockchip,hdmi-codec = <&hdmi>; 37 rockchip,i2s-controller = <&i2s>; 38 }; 39}; 40 41&cpu_thermal { 42 /delete-node/ trips; 43 /delete-node/ cooling-maps; 44 45 trips { 46 cpu_alert_almost_warm: cpu_alert_almost_warm { 47 temperature = <63000>; /* millicelsius */ 48 hysteresis = <2000>; /* millicelsius */ 49 type = "passive"; 50 }; 51 cpu_alert_warm: cpu_alert_warm { 52 temperature = <65000>; /* millicelsius */ 53 hysteresis = <2000>; /* millicelsius */ 54 type = "passive"; 55 }; 56 cpu_alert_almost_hot: cpu_alert_almost_hot { 57 temperature = <80000>; /* millicelsius */ 58 hysteresis = <2000>; /* millicelsius */ 59 type = "passive"; 60 }; 61 cpu_alert_hot: cpu_alert_hot { 62 temperature = <82000>; /* millicelsius */ 63 hysteresis = <2000>; /* millicelsius */ 64 type = "passive"; 65 }; 66 cpu_alert_hotter: cpu_alert_hotter { 67 temperature = <84000>; /* millicelsius */ 68 hysteresis = <2000>; /* millicelsius */ 69 type = "passive"; 70 }; 71 cpu_alert_very_hot: cpu_alert_very_hot { 72 temperature = <85000>; /* millicelsius */ 73 hysteresis = <2000>; /* millicelsius */ 74 type = "passive"; 75 }; 76 cpu_crit: cpu_crit { 77 temperature = <90000>; /* millicelsius */ 78 hysteresis = <2000>; /* millicelsius */ 79 type = "critical"; 80 }; 81 }; 82 83 cooling-maps { 84 /* 85 * After 1st level, throttle the CPU down to as low as 1.4 GHz 86 * and don't let the GPU go faster than 400 MHz. 87 */ 88 cpu_warm_limit_cpu { 89 trip = <&cpu_alert_warm>; 90 cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>, 91 <&cpu1 THERMAL_NO_LIMIT 4>, 92 <&cpu2 THERMAL_NO_LIMIT 4>, 93 <&cpu3 THERMAL_NO_LIMIT 4>; 94 }; 95 cpu_warm_limit_gpu { 96 trip = <&cpu_alert_warm>; 97 cooling-device = <&gpu 1 1>; 98 }; 99 100 /* 101 * Add some discrete steps to help throttling system deal 102 * with the fact that there are two passive cooling devices: 103 * the CPU and the GPU. 104 * 105 * - 1.2 GHz - 1.0 GHz (almost hot) 106 * - 800 MHz (hot) 107 * - 800 MHz - 696 MHz (hotter) 108 * - 696 MHz - min (very hot) 109 * 110 * Note: 111 * - 800 MHz appears to be a "sweet spot" for me. I can run 112 * some pretty serious workload here and be happy. 113 * - After 696 MHz we stop lowering voltage, so throttling 114 * past there is less effective. 115 */ 116 cpu_almost_hot_limit_cpu { 117 trip = <&cpu_alert_almost_hot>; 118 cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>, 119 <&cpu3 5 6>; 120 }; 121 cpu_hot_limit_cpu { 122 trip = <&cpu_alert_hot>; 123 cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>, 124 <&cpu3 7 7>; 125 }; 126 cpu_hotter_limit_cpu { 127 trip = <&cpu_alert_hotter>; 128 cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>, 129 <&cpu3 7 8>; 130 }; 131 cpu_very_hot_limit_cpu { 132 trip = <&cpu_alert_very_hot>; 133 cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>, 134 <&cpu1 8 THERMAL_NO_LIMIT>, 135 <&cpu2 8 THERMAL_NO_LIMIT>, 136 <&cpu3 8 THERMAL_NO_LIMIT>; 137 }; 138 139 /* At very hot, don't let GPU go over 300 MHz */ 140 cpu_very_hot_limit_gpu { 141 trip = <&cpu_alert_very_hot>; 142 cooling-device = <&gpu 2 2>; 143 }; 144 }; 145}; 146 147&gpu_thermal { 148 /delete-node/ trips; 149 /delete-node/ cooling-maps; 150 151 trips { 152 gpu_alert_warmish: gpu_alert_warmish { 153 temperature = <60000>; /* millicelsius */ 154 hysteresis = <2000>; /* millicelsius */ 155 type = "passive"; 156 }; 157 gpu_alert_warm: gpu_alert_warm { 158 temperature = <65000>; /* millicelsius */ 159 hysteresis = <2000>; /* millicelsius */ 160 type = "passive"; 161 }; 162 gpu_alert_hotter: gpu_alert_hotter { 163 temperature = <84000>; /* millicelsius */ 164 hysteresis = <2000>; /* millicelsius */ 165 type = "passive"; 166 }; 167 gpu_alert_very_very_hot: gpu_alert_very_very_hot { 168 temperature = <86000>; /* millicelsius */ 169 hysteresis = <2000>; /* millicelsius */ 170 type = "passive"; 171 }; 172 gpu_crit: gpu_crit { 173 temperature = <90000>; /* millicelsius */ 174 hysteresis = <2000>; /* millicelsius */ 175 type = "critical"; 176 }; 177 }; 178 179 cooling-maps { 180 /* After 1st level throttle the GPU down to as low as 400 MHz */ 181 gpu_warmish_limit_gpu { 182 trip = <&gpu_alert_warmish>; 183 cooling-device = <&gpu THERMAL_NO_LIMIT 1>; 184 }; 185 186 /* 187 * Slightly after we throttle the GPU, we'll also make sure that 188 * the CPU can't go faster than 1.4 GHz. Note that we won't 189 * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll 190 * let the CPU do the rest itself. 191 */ 192 gpu_warm_limit_cpu { 193 trip = <&gpu_alert_warm>; 194 cooling-device = <&cpu0 4 4>, 195 <&cpu1 4 4>, 196 <&cpu2 4 4>, 197 <&cpu3 4 4>; 198 }; 199 200 /* When hot, GPU goes down to 300 MHz */ 201 gpu_hotter_limit_gpu { 202 trip = <&gpu_alert_hotter>; 203 cooling-device = <&gpu 2 2>; 204 }; 205 206 /* When really hot, don't let GPU go _above_ 300 MHz */ 207 gpu_very_very_hot_limit_gpu { 208 trip = <&gpu_alert_very_very_hot>; 209 cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; 210 }; 211 }; 212}; 213 214&i2c2 { 215 status = "disabled"; 216}; 217 218&i2c4 { 219 status = "disabled"; 220}; 221 222&i2s { 223 status = "okay"; 224}; 225 226&rk808 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; 229 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, 230 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; 231 232 /delete-property/ vcc6-supply; 233 /delete-property/ vcc12-supply; 234 235 vcc11-supply = <&vcc33_sys>; 236 237 regulators { 238 /* vcc33_io is sourced directly from vcc33_sys */ 239 /delete-node/ LDO_REG1; 240 /delete-node/ LDO_REG7; 241 242 /* This is not a pwren anymore, but the real power supply */ 243 vdd10_lcd: LDO_REG7 { 244 regulator-always-on; 245 regulator-boot-on; 246 regulator-min-microvolt = <1000000>; 247 regulator-max-microvolt = <1000000>; 248 regulator-name = "vdd10_lcd"; 249 regulator-suspend-mem-disabled; 250 }; 251 252 vcc18_lcd: LDO_REG8 { 253 regulator-always-on; 254 regulator-boot-on; 255 regulator-min-microvolt = <1800000>; 256 regulator-max-microvolt = <1800000>; 257 regulator-name = "vcc18_lcd"; 258 regulator-suspend-mem-disabled; 259 }; 260 }; 261}; 262 263&gpio0 { 264 gpio-line-names = "PMIC_SLEEP_AP", 265 "", 266 "", 267 "", 268 "PMIC_INT_L", 269 "POWER_BUTTON_L", 270 "", 271 "", 272 273 "", 274 /* 275 * RECOVERY_SW_L is Chrome OS ABI. Schematics call 276 * it REC_MODE_L. 277 */ 278 "RECOVERY_SW_L", 279 "OT_RESET", 280 "", 281 "", 282 "AP_WARM_RESET_H", 283 "", 284 "I2C0_SDA_PMIC", 285 286 "I2C0_SCL_PMIC", 287 "", 288 "nFALUT"; 289}; 290 291&gpio2 { 292 gpio-line-names = "CONFIG0", 293 "CONFIG1", 294 "CONFIG2", 295 "", 296 "", 297 "", 298 "", 299 "CONFIG3", 300 301 "", 302 "EMMC_RST_L"; 303}; 304 305&gpio3 { 306 gpio-line-names = "FLASH0_D0", 307 "FLASH0_D1", 308 "FLASH0_D2", 309 "FLASH0_D3", 310 "FLASH0_D4", 311 "FLASH0_D5", 312 "FLASH0_D6", 313 "FLASH0_D7", 314 315 "", 316 "", 317 "", 318 "", 319 "", 320 "", 321 "", 322 "", 323 324 "FLASH0_CS2/EMMC_CMD", 325 "", 326 "FLASH0_DQS/EMMC_CLKO"; 327}; 328 329&gpio4 { 330 gpio-line-names = "", 331 "", 332 "", 333 "", 334 "", 335 "", 336 "", 337 "", 338 339 "", 340 "", 341 "", 342 "", 343 "", 344 "", 345 "", 346 "", 347 348 "UART0_RXD", 349 "UART0_TXD", 350 "UART0_CTS_L", 351 "UART0_RTS_L", 352 "SDIO0_D0", 353 "SDIO0_D1", 354 "SDIO0_D2", 355 "SDIO0_D3", 356 357 "SDIO0_CMD", 358 "SDIO0_CLK", 359 "BT_DEV_WAKE", 360 "", 361 "WIFI_ENABLE_H", 362 "BT_ENABLE_L", 363 "WIFI_HOST_WAKE", 364 "BT_HOST_WAKE"; 365}; 366 367&gpio7 { 368 gpio-line-names = "", 369 "PWM_LOG", 370 "", 371 "", 372 "TPM_INT_H", 373 "SDMMC_DET_L", 374 /* 375 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call 376 * it FW_WP_AP. 377 */ 378 "AP_FLASH_WP_L", 379 "", 380 381 "CPU_NMI", 382 "DVSOK", 383 "HDMI_WAKE", 384 "POWER_HDMI_ON", 385 "DVS1", 386 "", 387 "", 388 "DVS2", 389 390 "HDMI_CEC", 391 "", 392 "", 393 "I2C5_SDA_HDMI", 394 "I2C5_SCL_HDMI", 395 "", 396 "UART2_RXD", 397 "UART2_TXD"; 398}; 399 400&gpio8 { 401 gpio-line-names = "RAM_ID0", 402 "RAM_ID1", 403 "RAM_ID2", 404 "RAM_ID3", 405 "I2C1_SDA_TPM", 406 "I2C1_SCL_TPM", 407 "SPI2_CLK", 408 "SPI2_CS0", 409 410 "SPI2_RXD", 411 "SPI2_TXD"; 412}; 413 414&pinctrl { 415 pinctrl-names = "default"; 416 pinctrl-0 = < 417 /* Common for sleep and wake, but no owners */ 418 &ddr0_retention 419 &ddrio_pwroff 420 &global_pwroff 421 >; 422 423 hdmi { 424 power_hdmi_on: power-hdmi-on { 425 rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 426 }; 427 }; 428 429 pmic { 430 dvs_1: dvs-1 { 431 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; 432 }; 433 434 dvs_2: dvs-2 { 435 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; 436 }; 437 }; 438}; 439 440&usb_host0_ehci { 441 status = "disabled"; 442}; 443 444&usb_host1 { 445 status = "disabled"; 446}; 447 448&vcc50_hdmi { 449 enable-active-high; 450 gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&power_hdmi_on>; 453}; 454