1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3128-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3128-power.h> 12 13/ { 14 compatible = "rockchip,rk3128"; 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 }; 32 33 arm-pmu { 34 compatible = "arm,cortex-a7-pmu"; 35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 enable-method = "rockchip,rk3036-smp"; 46 47 cpu0: cpu@f00 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a7"; 50 reg = <0xf00>; 51 clock-latency = <40000>; 52 clocks = <&cru ARMCLK>; 53 resets = <&cru SRST_CORE0>; 54 operating-points-v2 = <&cpu_opp_table>; 55 #cooling-cells = <2>; /* min followed by max */ 56 }; 57 58 cpu1: cpu@f01 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0xf01>; 62 resets = <&cru SRST_CORE1>; 63 operating-points-v2 = <&cpu_opp_table>; 64 }; 65 66 cpu2: cpu@f02 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a7"; 69 reg = <0xf02>; 70 resets = <&cru SRST_CORE2>; 71 operating-points-v2 = <&cpu_opp_table>; 72 }; 73 74 cpu3: cpu@f03 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 reg = <0xf03>; 78 resets = <&cru SRST_CORE3>; 79 operating-points-v2 = <&cpu_opp_table>; 80 }; 81 }; 82 83 cpu_opp_table: opp-table-0 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-216000000 { 88 opp-hz = /bits/ 64 <216000000>; 89 opp-microvolt = <950000 950000 1325000>; 90 }; 91 opp-408000000 { 92 opp-hz = /bits/ 64 <408000000>; 93 opp-microvolt = <950000 950000 1325000>; 94 }; 95 opp-600000000 { 96 opp-hz = /bits/ 64 <600000000>; 97 opp-microvolt = <950000 950000 1325000>; 98 }; 99 opp-696000000 { 100 opp-hz = /bits/ 64 <696000000>; 101 opp-microvolt = <975000 975000 1325000>; 102 }; 103 opp-816000000 { 104 opp-hz = /bits/ 64 <816000000>; 105 opp-microvolt = <1075000 1075000 1325000>; 106 opp-suspend; 107 }; 108 opp-1008000000 { 109 opp-hz = /bits/ 64 <1008000000>; 110 opp-microvolt = <1200000 1200000 1325000>; 111 }; 112 opp-1200000000 { 113 opp-hz = /bits/ 64 <1200000000>; 114 opp-microvolt = <1325000 1325000 1325000>; 115 }; 116 }; 117 118 display_subsystem: display-subsystem { 119 compatible = "rockchip,display-subsystem"; 120 ports = <&vop_out>; 121 status = "disabled"; 122 }; 123 124 gpu_opp_table: opp-table-1 { 125 compatible = "operating-points-v2"; 126 127 opp-200000000 { 128 opp-hz = /bits/ 64 <200000000>; 129 opp-microvolt = <975000 975000 1250000>; 130 }; 131 opp-300000000 { 132 opp-hz = /bits/ 64 <300000000>; 133 opp-microvolt = <1050000 1050000 1250000>; 134 }; 135 opp-400000000 { 136 opp-hz = /bits/ 64 <400000000>; 137 opp-microvolt = <1150000 1150000 1250000>; 138 }; 139 opp-480000000 { 140 opp-hz = /bits/ 64 <480000000>; 141 opp-microvolt = <1250000 1250000 1250000>; 142 }; 143 }; 144 145 timer { 146 compatible = "arm,armv7-timer"; 147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 151 arm,cpu-registers-not-fw-configured; 152 clock-frequency = <24000000>; 153 }; 154 155 xin24m: oscillator { 156 compatible = "fixed-clock"; 157 clock-frequency = <24000000>; 158 clock-output-names = "xin24m"; 159 #clock-cells = <0>; 160 }; 161 162 imem: sram@10080000 { 163 compatible = "mmio-sram"; 164 reg = <0x10080000 0x2000>; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges = <0 0x10080000 0x2000>; 168 169 smp-sram@0 { 170 compatible = "rockchip,rk3066-smp-sram"; 171 reg = <0x00 0x10>; 172 }; 173 }; 174 175 gpu: gpu@10090000 { 176 compatible = "rockchip,rk3128-mali", "arm,mali-400"; 177 reg = <0x10090000 0x10000>; 178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "gp", 185 "gpmmu", 186 "pp0", 187 "ppmmu0", 188 "pp1", 189 "ppmmu1"; 190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 191 clock-names = "bus", "core"; 192 operating-points-v2 = <&gpu_opp_table>; 193 resets = <&cru SRST_GPU>; 194 power-domains = <&power RK3128_PD_GPU>; 195 status = "disabled"; 196 }; 197 198 pmu: syscon@100a0000 { 199 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 200 reg = <0x100a0000 0x1000>; 201 202 power: power-controller { 203 compatible = "rockchip,rk3128-power-controller"; 204 #power-domain-cells = <1>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 power-domain@RK3128_PD_VIO { 209 reg = <RK3128_PD_VIO>; 210 clocks = <&cru ACLK_CIF>, 211 <&cru HCLK_CIF>, 212 <&cru DCLK_EBC>, 213 <&cru HCLK_EBC>, 214 <&cru ACLK_IEP>, 215 <&cru HCLK_IEP>, 216 <&cru ACLK_LCDC0>, 217 <&cru HCLK_LCDC0>, 218 <&cru PCLK_MIPI>, 219 <&cru ACLK_RGA>, 220 <&cru HCLK_RGA>, 221 <&cru ACLK_VIO0>, 222 <&cru ACLK_VIO1>, 223 <&cru HCLK_VIO>, 224 <&cru HCLK_VIO_H2P>, 225 <&cru DCLK_VOP>, 226 <&cru SCLK_VOP>; 227 pm_qos = <&qos_ebc>, 228 <&qos_iep>, 229 <&qos_lcdc>, 230 <&qos_rga>, 231 <&qos_vip>; 232 #power-domain-cells = <0>; 233 }; 234 235 power-domain@RK3128_PD_VIDEO { 236 reg = <RK3128_PD_VIDEO>; 237 clocks = <&cru ACLK_VDPU>, 238 <&cru HCLK_VDPU>, 239 <&cru ACLK_VEPU>, 240 <&cru HCLK_VEPU>, 241 <&cru SCLK_HEVC_CORE>; 242 pm_qos = <&qos_vpu>; 243 #power-domain-cells = <0>; 244 }; 245 246 power-domain@RK3128_PD_GPU { 247 reg = <RK3128_PD_GPU>; 248 clocks = <&cru ACLK_GPU>; 249 pm_qos = <&qos_gpu>; 250 #power-domain-cells = <0>; 251 }; 252 }; 253 }; 254 255 vop: vop@1010e000 { 256 compatible = "rockchip,rk3126-vop"; 257 reg = <0x1010e000 0x300>; 258 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, 260 <&cru HCLK_LCDC0>; 261 clock-names = "aclk_vop", "dclk_vop", 262 "hclk_vop"; 263 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, 264 <&cru SRST_VOP_D>; 265 reset-names = "axi", "ahb", 266 "dclk"; 267 power-domains = <&power RK3128_PD_VIO>; 268 status = "disabled"; 269 270 vop_out: port { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 vop_out_hdmi: endpoint@0 { 275 reg = <0>; 276 remote-endpoint = <&hdmi_in_vop>; 277 }; 278 }; 279 }; 280 281 qos_gpu: qos@1012d000 { 282 compatible = "rockchip,rk3128-qos", "syscon"; 283 reg = <0x1012d000 0x20>; 284 }; 285 286 qos_vpu: qos@1012e000 { 287 compatible = "rockchip,rk3128-qos", "syscon"; 288 reg = <0x1012e000 0x20>; 289 }; 290 291 qos_rga: qos@1012f000 { 292 compatible = "rockchip,rk3128-qos", "syscon"; 293 reg = <0x1012f000 0x20>; 294 }; 295 296 qos_ebc: qos@1012f080 { 297 compatible = "rockchip,rk3128-qos", "syscon"; 298 reg = <0x1012f080 0x20>; 299 }; 300 301 qos_iep: qos@1012f100 { 302 compatible = "rockchip,rk3128-qos", "syscon"; 303 reg = <0x1012f100 0x20>; 304 }; 305 306 qos_lcdc: qos@1012f180 { 307 compatible = "rockchip,rk3128-qos", "syscon"; 308 reg = <0x1012f180 0x20>; 309 }; 310 311 qos_vip: qos@1012f200 { 312 compatible = "rockchip,rk3128-qos", "syscon"; 313 reg = <0x1012f200 0x20>; 314 }; 315 316 gic: interrupt-controller@10139000 { 317 compatible = "arm,cortex-a7-gic"; 318 reg = <0x10139000 0x1000>, 319 <0x1013a000 0x1000>, 320 <0x1013c000 0x2000>, 321 <0x1013e000 0x2000>; 322 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 323 interrupt-controller; 324 #interrupt-cells = <3>; 325 #address-cells = <0>; 326 }; 327 328 usb_otg: usb@10180000 { 329 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 330 reg = <0x10180000 0x40000>; 331 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cru HCLK_OTG>; 333 clock-names = "otg"; 334 dr_mode = "otg"; 335 g-np-tx-fifo-size = <16>; 336 g-rx-fifo-size = <280>; 337 g-tx-fifo-size = <256 128 128 64 32 16>; 338 phys = <&usb2phy_otg>; 339 phy-names = "usb2-phy"; 340 status = "disabled"; 341 }; 342 343 usb_host_ehci: usb@101c0000 { 344 compatible = "generic-ehci"; 345 reg = <0x101c0000 0x20000>; 346 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&cru HCLK_HOST2>; 348 phys = <&usb2phy_host>; 349 phy-names = "usb"; 350 status = "disabled"; 351 }; 352 353 usb_host_ohci: usb@101e0000 { 354 compatible = "generic-ohci"; 355 reg = <0x101e0000 0x20000>; 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&cru HCLK_HOST2>; 358 phys = <&usb2phy_host>; 359 phy-names = "usb"; 360 status = "disabled"; 361 }; 362 363 sdmmc: mmc@10214000 { 364 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 365 reg = <0x10214000 0x4000>; 366 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 368 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 369 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 370 dmas = <&pdma 10>; 371 dma-names = "rx-tx"; 372 fifo-depth = <256>; 373 max-frequency = <150000000>; 374 resets = <&cru SRST_SDMMC>; 375 reset-names = "reset"; 376 status = "disabled"; 377 }; 378 379 sdio: mmc@10218000 { 380 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 381 reg = <0x10218000 0x4000>; 382 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 384 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 385 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 386 dmas = <&pdma 11>; 387 dma-names = "rx-tx"; 388 fifo-depth = <256>; 389 max-frequency = <150000000>; 390 resets = <&cru SRST_SDIO>; 391 reset-names = "reset"; 392 status = "disabled"; 393 }; 394 395 emmc: mmc@1021c000 { 396 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 397 reg = <0x1021c000 0x4000>; 398 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 400 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 401 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 402 dmas = <&pdma 12>; 403 dma-names = "rx-tx"; 404 fifo-depth = <256>; 405 max-frequency = <150000000>; 406 resets = <&cru SRST_EMMC>; 407 reset-names = "reset"; 408 status = "disabled"; 409 }; 410 411 nfc: nand-controller@10500000 { 412 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 413 reg = <0x10500000 0x4000>; 414 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 416 clock-names = "ahb", "nfc"; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 419 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 420 status = "disabled"; 421 }; 422 423 cru: clock-controller@20000000 { 424 compatible = "rockchip,rk3128-cru"; 425 reg = <0x20000000 0x1000>; 426 clocks = <&xin24m>; 427 clock-names = "xin24m"; 428 rockchip,grf = <&grf>; 429 #clock-cells = <1>; 430 #reset-cells = <1>; 431 assigned-clocks = <&cru PLL_GPLL>; 432 assigned-clock-rates = <594000000>; 433 }; 434 435 grf: syscon@20008000 { 436 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 437 reg = <0x20008000 0x1000>; 438 #address-cells = <1>; 439 #size-cells = <1>; 440 441 usb2phy: usb2phy@17c { 442 compatible = "rockchip,rk3128-usb2phy"; 443 reg = <0x017c 0x0c>; 444 clocks = <&cru SCLK_OTGPHY0>; 445 clock-names = "phyclk"; 446 clock-output-names = "usb480m_phy"; 447 assigned-clocks = <&cru SCLK_USB480M>; 448 assigned-clock-parents = <&usb2phy>; 449 #clock-cells = <0>; 450 status = "disabled"; 451 452 usb2phy_host: host-port { 453 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-names = "linestate"; 455 #phy-cells = <0>; 456 status = "disabled"; 457 }; 458 459 usb2phy_otg: otg-port { 460 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-names = "otg-bvalid", "otg-id", 464 "linestate"; 465 #phy-cells = <0>; 466 status = "disabled"; 467 }; 468 }; 469 }; 470 471 hdmi: hdmi@20034000 { 472 compatible = "rockchip,rk3128-inno-hdmi"; 473 reg = <0x20034000 0x4000>; 474 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>; 476 clock-names = "pclk", "ref"; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 479 power-domains = <&power RK3128_PD_VIO>; 480 status = "disabled"; 481 482 ports { 483 #address-cells = <1>; 484 #size-cells = <0>; 485 486 hdmi_in: port@0 { 487 reg = <0>; 488 hdmi_in_vop: endpoint { 489 remote-endpoint = <&vop_out_hdmi>; 490 }; 491 }; 492 493 hdmi_out: port@1 { 494 reg = <1>; 495 }; 496 }; 497 }; 498 499 timer0: timer@20044000 { 500 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 501 reg = <0x20044000 0x20>; 502 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 504 clock-names = "pclk", "timer"; 505 }; 506 507 timer1: timer@20044020 { 508 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 509 reg = <0x20044020 0x20>; 510 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 512 clock-names = "pclk", "timer"; 513 }; 514 515 timer2: timer@20044040 { 516 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 517 reg = <0x20044040 0x20>; 518 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 520 clock-names = "pclk", "timer"; 521 }; 522 523 timer3: timer@20044060 { 524 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 525 reg = <0x20044060 0x20>; 526 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 528 clock-names = "pclk", "timer"; 529 }; 530 531 timer4: timer@20044080 { 532 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 533 reg = <0x20044080 0x20>; 534 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 536 clock-names = "pclk", "timer"; 537 }; 538 539 timer5: timer@200440a0 { 540 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 541 reg = <0x200440a0 0x20>; 542 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 544 clock-names = "pclk", "timer"; 545 }; 546 547 watchdog: watchdog@2004c000 { 548 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 549 reg = <0x2004c000 0x100>; 550 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cru PCLK_WDT>; 552 status = "disabled"; 553 }; 554 555 pwm0: pwm@20050000 { 556 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 557 reg = <0x20050000 0x10>; 558 clocks = <&cru PCLK_PWM>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&pwm0_pin>; 561 #pwm-cells = <3>; 562 status = "disabled"; 563 }; 564 565 pwm1: pwm@20050010 { 566 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 567 reg = <0x20050010 0x10>; 568 clocks = <&cru PCLK_PWM>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pwm1_pin>; 571 #pwm-cells = <3>; 572 status = "disabled"; 573 }; 574 575 pwm2: pwm@20050020 { 576 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 577 reg = <0x20050020 0x10>; 578 clocks = <&cru PCLK_PWM>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pwm2_pin>; 581 #pwm-cells = <3>; 582 status = "disabled"; 583 }; 584 585 pwm3: pwm@20050030 { 586 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 587 reg = <0x20050030 0x10>; 588 clocks = <&cru PCLK_PWM>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&pwm3_pin>; 591 #pwm-cells = <3>; 592 status = "disabled"; 593 }; 594 595 i2c1: i2c@20056000 { 596 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 597 reg = <0x20056000 0x1000>; 598 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 599 clock-names = "i2c"; 600 clocks = <&cru PCLK_I2C1>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&i2c1_xfer>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 status = "disabled"; 606 }; 607 608 i2c2: i2c@2005a000 { 609 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 610 reg = <0x2005a000 0x1000>; 611 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 612 clock-names = "i2c"; 613 clocks = <&cru PCLK_I2C2>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&i2c2_xfer>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619 }; 620 621 i2c3: i2c@2005e000 { 622 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 623 reg = <0x2005e000 0x1000>; 624 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 625 clock-names = "i2c"; 626 clocks = <&cru PCLK_I2C3>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&i2c3_xfer>; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 status = "disabled"; 632 }; 633 634 uart0: serial@20060000 { 635 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 636 reg = <0x20060000 0x100>; 637 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 638 clock-frequency = <24000000>; 639 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 640 clock-names = "baudclk", "apb_pclk"; 641 dmas = <&pdma 2>, <&pdma 3>; 642 dma-names = "tx", "rx"; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 645 reg-io-width = <4>; 646 reg-shift = <2>; 647 status = "disabled"; 648 }; 649 650 uart1: serial@20064000 { 651 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 652 reg = <0x20064000 0x100>; 653 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 654 clock-frequency = <24000000>; 655 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 656 clock-names = "baudclk", "apb_pclk"; 657 dmas = <&pdma 4>, <&pdma 5>; 658 dma-names = "tx", "rx"; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&uart1_xfer>; 661 reg-io-width = <4>; 662 reg-shift = <2>; 663 status = "disabled"; 664 }; 665 666 uart2: serial@20068000 { 667 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 668 reg = <0x20068000 0x100>; 669 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 670 clock-frequency = <24000000>; 671 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 672 clock-names = "baudclk", "apb_pclk"; 673 dmas = <&pdma 6>, <&pdma 7>; 674 dma-names = "tx", "rx"; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&uart2_xfer>; 677 reg-io-width = <4>; 678 reg-shift = <2>; 679 status = "disabled"; 680 }; 681 682 saradc: saradc@2006c000 { 683 compatible = "rockchip,saradc"; 684 reg = <0x2006c000 0x100>; 685 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 687 clock-names = "saradc", "apb_pclk"; 688 resets = <&cru SRST_SARADC>; 689 reset-names = "saradc-apb"; 690 #io-channel-cells = <1>; 691 status = "disabled"; 692 }; 693 694 i2c0: i2c@20072000 { 695 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 696 reg = <0x20072000 0x1000>; 697 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 698 clock-names = "i2c"; 699 clocks = <&cru PCLK_I2C0>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&i2c0_xfer>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 spi0: spi@20074000 { 708 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 709 reg = <0x20074000 0x1000>; 710 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 712 clock-names = "spiclk", "apb_pclk"; 713 dmas = <&pdma 8>, <&pdma 9>; 714 dma-names = "tx", "rx"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 pdma: dma-controller@20078000 { 723 compatible = "arm,pl330", "arm,primecell"; 724 reg = <0x20078000 0x4000>; 725 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 727 arm,pl330-broken-no-flushp; 728 arm,pl330-periph-burst; 729 clocks = <&cru ACLK_DMAC>; 730 clock-names = "apb_pclk"; 731 #dma-cells = <1>; 732 }; 733 734 gmac: ethernet@2008c000 { 735 compatible = "rockchip,rk3128-gmac"; 736 reg = <0x2008c000 0x4000>; 737 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 739 interrupt-names = "macirq", "eth_wake_irq"; 740 clocks = <&cru SCLK_MAC>, 741 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 742 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 743 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 744 clock-names = "stmmaceth", 745 "mac_clk_rx", "mac_clk_tx", 746 "clk_mac_ref", "clk_mac_refout", 747 "aclk_mac", "pclk_mac"; 748 resets = <&cru SRST_GMAC>; 749 reset-names = "stmmaceth"; 750 rockchip,grf = <&grf>; 751 rx-fifo-depth = <4096>; 752 tx-fifo-depth = <2048>; 753 status = "disabled"; 754 755 mdio: mdio { 756 compatible = "snps,dwmac-mdio"; 757 #address-cells = <0x1>; 758 #size-cells = <0x0>; 759 }; 760 }; 761 762 pinctrl: pinctrl { 763 compatible = "rockchip,rk3128-pinctrl"; 764 rockchip,grf = <&grf>; 765 #address-cells = <1>; 766 #size-cells = <1>; 767 ranges; 768 769 gpio0: gpio@2007c000 { 770 compatible = "rockchip,gpio-bank"; 771 reg = <0x2007c000 0x100>; 772 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&cru PCLK_GPIO0>; 774 gpio-controller; 775 #gpio-cells = <2>; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 }; 779 780 gpio1: gpio@20080000 { 781 compatible = "rockchip,gpio-bank"; 782 reg = <0x20080000 0x100>; 783 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&cru PCLK_GPIO1>; 785 gpio-controller; 786 #gpio-cells = <2>; 787 interrupt-controller; 788 #interrupt-cells = <2>; 789 }; 790 791 gpio2: gpio@20084000 { 792 compatible = "rockchip,gpio-bank"; 793 reg = <0x20084000 0x100>; 794 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&cru PCLK_GPIO2>; 796 gpio-controller; 797 #gpio-cells = <2>; 798 interrupt-controller; 799 #interrupt-cells = <2>; 800 }; 801 802 gpio3: gpio@20088000 { 803 compatible = "rockchip,gpio-bank"; 804 reg = <0x20088000 0x100>; 805 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&cru PCLK_GPIO3>; 807 gpio-controller; 808 #gpio-cells = <2>; 809 interrupt-controller; 810 #interrupt-cells = <2>; 811 }; 812 813 pcfg_pull_default: pcfg-pull-default { 814 bias-pull-pin-default; 815 }; 816 817 pcfg_pull_none: pcfg-pull-none { 818 bias-disable; 819 }; 820 821 emmc { 822 emmc_clk: emmc-clk { 823 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 824 }; 825 826 emmc_cmd: emmc-cmd { 827 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 828 }; 829 830 emmc_cmd1: emmc-cmd1 { 831 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 832 }; 833 834 emmc_pwr: emmc-pwr { 835 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 836 }; 837 838 emmc_bus1: emmc-bus1 { 839 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 840 }; 841 842 emmc_bus4: emmc-bus4 { 843 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 844 <1 RK_PD1 2 &pcfg_pull_default>, 845 <1 RK_PD2 2 &pcfg_pull_default>, 846 <1 RK_PD3 2 &pcfg_pull_default>; 847 }; 848 849 emmc_bus8: emmc-bus8 { 850 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 851 <1 RK_PD1 2 &pcfg_pull_default>, 852 <1 RK_PD2 2 &pcfg_pull_default>, 853 <1 RK_PD3 2 &pcfg_pull_default>, 854 <1 RK_PD4 2 &pcfg_pull_default>, 855 <1 RK_PD5 2 &pcfg_pull_default>, 856 <1 RK_PD6 2 &pcfg_pull_default>, 857 <1 RK_PD7 2 &pcfg_pull_default>; 858 }; 859 }; 860 861 gmac { 862 rgmii_pins: rgmii-pins { 863 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 864 <2 RK_PB1 3 &pcfg_pull_default>, 865 <2 RK_PB3 3 &pcfg_pull_default>, 866 <2 RK_PB4 3 &pcfg_pull_default>, 867 <2 RK_PB5 3 &pcfg_pull_default>, 868 <2 RK_PB6 3 &pcfg_pull_default>, 869 <2 RK_PC0 3 &pcfg_pull_default>, 870 <2 RK_PC1 3 &pcfg_pull_default>, 871 <2 RK_PC2 3 &pcfg_pull_default>, 872 <2 RK_PC3 3 &pcfg_pull_default>, 873 <2 RK_PD1 3 &pcfg_pull_default>, 874 <2 RK_PC4 4 &pcfg_pull_default>, 875 <2 RK_PC5 4 &pcfg_pull_default>, 876 <2 RK_PC6 4 &pcfg_pull_default>, 877 <2 RK_PC7 4 &pcfg_pull_default>; 878 }; 879 880 rmii_pins: rmii-pins { 881 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 882 <2 RK_PB4 3 &pcfg_pull_default>, 883 <2 RK_PB5 3 &pcfg_pull_default>, 884 <2 RK_PB6 3 &pcfg_pull_default>, 885 <2 RK_PB7 3 &pcfg_pull_default>, 886 <2 RK_PC0 3 &pcfg_pull_default>, 887 <2 RK_PC1 3 &pcfg_pull_default>, 888 <2 RK_PC2 3 &pcfg_pull_default>, 889 <2 RK_PC3 3 &pcfg_pull_default>, 890 <2 RK_PD1 3 &pcfg_pull_default>; 891 }; 892 }; 893 894 hdmi { 895 hdmii2c_xfer: hdmii2c-xfer { 896 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 897 <0 RK_PA7 2 &pcfg_pull_none>; 898 }; 899 900 hdmi_hpd: hdmi-hpd { 901 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 902 }; 903 904 hdmi_cec: hdmi-cec { 905 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 906 }; 907 }; 908 909 i2c0 { 910 i2c0_xfer: i2c0-xfer { 911 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 912 <0 RK_PA1 1 &pcfg_pull_none>; 913 }; 914 }; 915 916 i2c1 { 917 i2c1_xfer: i2c1-xfer { 918 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 919 <0 RK_PA3 1 &pcfg_pull_none>; 920 }; 921 }; 922 923 i2c2 { 924 i2c2_xfer: i2c2-xfer { 925 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 926 <2 RK_PC5 3 &pcfg_pull_none>; 927 }; 928 }; 929 930 i2c3 { 931 i2c3_xfer: i2c3-xfer { 932 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 933 <0 RK_PA7 1 &pcfg_pull_none>; 934 }; 935 }; 936 937 i2s { 938 i2s_bus: i2s-bus { 939 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 940 <0 RK_PB1 1 &pcfg_pull_none>, 941 <0 RK_PB3 1 &pcfg_pull_none>, 942 <0 RK_PB4 1 &pcfg_pull_none>, 943 <0 RK_PB5 1 &pcfg_pull_none>, 944 <0 RK_PB6 1 &pcfg_pull_none>; 945 }; 946 947 i2s1_bus: i2s1-bus { 948 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 949 <1 RK_PA1 1 &pcfg_pull_none>, 950 <1 RK_PA2 1 &pcfg_pull_none>, 951 <1 RK_PA3 1 &pcfg_pull_none>, 952 <1 RK_PA4 1 &pcfg_pull_none>, 953 <1 RK_PA5 1 &pcfg_pull_none>; 954 }; 955 }; 956 957 lcdc { 958 lcdc_dclk: lcdc-dclk { 959 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 960 }; 961 962 lcdc_den: lcdc-den { 963 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 964 }; 965 966 lcdc_hsync: lcdc-hsync { 967 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 968 }; 969 970 lcdc_vsync: lcdc-vsync { 971 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 972 }; 973 974 lcdc_rgb24: lcdc-rgb24 { 975 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 976 <2 RK_PB5 1 &pcfg_pull_none>, 977 <2 RK_PB6 1 &pcfg_pull_none>, 978 <2 RK_PB7 1 &pcfg_pull_none>, 979 <2 RK_PC0 1 &pcfg_pull_none>, 980 <2 RK_PC1 1 &pcfg_pull_none>, 981 <2 RK_PC2 1 &pcfg_pull_none>, 982 <2 RK_PC3 1 &pcfg_pull_none>, 983 <2 RK_PC4 1 &pcfg_pull_none>, 984 <2 RK_PC5 1 &pcfg_pull_none>, 985 <2 RK_PC6 1 &pcfg_pull_none>, 986 <2 RK_PC7 1 &pcfg_pull_none>, 987 <2 RK_PD0 1 &pcfg_pull_none>, 988 <2 RK_PD1 1 &pcfg_pull_none>; 989 }; 990 }; 991 992 nfc { 993 flash_ale: flash-ale { 994 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 995 }; 996 997 flash_cle: flash-cle { 998 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 999 }; 1000 1001 flash_wrn: flash-wrn { 1002 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1003 }; 1004 1005 flash_rdn: flash-rdn { 1006 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 1007 }; 1008 1009 flash_rdy: flash-rdy { 1010 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1011 }; 1012 1013 flash_cs0: flash-cs0 { 1014 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1015 }; 1016 1017 flash_dqs: flash-dqs { 1018 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 1019 }; 1020 1021 flash_bus8: flash-bus8 { 1022 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1023 <1 RK_PD1 1 &pcfg_pull_none>, 1024 <1 RK_PD2 1 &pcfg_pull_none>, 1025 <1 RK_PD3 1 &pcfg_pull_none>, 1026 <1 RK_PD4 1 &pcfg_pull_none>, 1027 <1 RK_PD5 1 &pcfg_pull_none>, 1028 <1 RK_PD6 1 &pcfg_pull_none>, 1029 <1 RK_PD7 1 &pcfg_pull_none>; 1030 }; 1031 }; 1032 1033 pwm0 { 1034 pwm0_pin: pwm0-pin { 1035 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 1036 }; 1037 }; 1038 1039 pwm1 { 1040 pwm1_pin: pwm1-pin { 1041 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1042 }; 1043 }; 1044 1045 pwm2 { 1046 pwm2_pin: pwm2-pin { 1047 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1048 }; 1049 }; 1050 1051 pwm3 { 1052 pwm3_pin: pwm3-pin { 1053 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 1054 }; 1055 }; 1056 1057 sdio { 1058 sdio_clk: sdio-clk { 1059 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 1060 }; 1061 1062 sdio_cmd: sdio-cmd { 1063 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 1064 }; 1065 1066 sdio_pwren: sdio-pwren { 1067 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 1068 }; 1069 1070 sdio_bus4: sdio-bus4 { 1071 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 1072 <1 RK_PA2 2 &pcfg_pull_default>, 1073 <1 RK_PA4 2 &pcfg_pull_default>, 1074 <1 RK_PA5 2 &pcfg_pull_default>; 1075 }; 1076 }; 1077 1078 sdmmc { 1079 sdmmc_clk: sdmmc-clk { 1080 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1081 }; 1082 1083 sdmmc_cmd: sdmmc-cmd { 1084 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1085 }; 1086 1087 sdmmc_det: sdmmc-det { 1088 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 1089 }; 1090 1091 sdmmc_wp: sdmmc-wp { 1092 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1093 }; 1094 1095 sdmmc_pwren: sdmmc-pwren { 1096 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; 1097 }; 1098 1099 sdmmc_bus4: sdmmc-bus4 { 1100 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1101 <1 RK_PC3 1 &pcfg_pull_default>, 1102 <1 RK_PC4 1 &pcfg_pull_default>, 1103 <1 RK_PC5 1 &pcfg_pull_default>; 1104 }; 1105 }; 1106 1107 spdif { 1108 spdif_tx: spdif-tx { 1109 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1110 }; 1111 }; 1112 1113 spi0 { 1114 spi0_clk: spi0-clk { 1115 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1116 }; 1117 1118 spi0_cs0: spi0-cs0 { 1119 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1120 }; 1121 1122 spi0_tx: spi0-tx { 1123 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1124 }; 1125 1126 spi0_rx: spi0-rx { 1127 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1128 }; 1129 1130 spi0_cs1: spi0-cs1 { 1131 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1132 }; 1133 1134 spi1_clk: spi1-clk { 1135 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1136 }; 1137 1138 spi1_cs0: spi1-cs0 { 1139 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1140 }; 1141 1142 spi1_tx: spi1-tx { 1143 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1144 }; 1145 1146 spi1_rx: spi1-rx { 1147 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1148 }; 1149 1150 spi1_cs1: spi1-cs1 { 1151 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1152 }; 1153 1154 spi2_clk: spi2-clk { 1155 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1156 }; 1157 1158 spi2_cs0: spi2-cs0 { 1159 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1160 }; 1161 1162 spi2_tx: spi2-tx { 1163 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1164 }; 1165 1166 spi2_rx: spi2-rx { 1167 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1168 }; 1169 }; 1170 1171 uart0 { 1172 uart0_xfer: uart0-xfer { 1173 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1174 <2 RK_PD3 2 &pcfg_pull_none>; 1175 }; 1176 1177 uart0_cts: uart0-cts { 1178 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1179 }; 1180 1181 uart0_rts: uart0-rts { 1182 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1183 }; 1184 }; 1185 1186 uart1 { 1187 uart1_xfer: uart1-xfer { 1188 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1189 <1 RK_PB2 2 &pcfg_pull_default>; 1190 }; 1191 1192 uart1_cts: uart1-cts { 1193 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1194 }; 1195 1196 uart1_rts: uart1-rts { 1197 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1198 }; 1199 }; 1200 1201 uart2 { 1202 uart2_xfer: uart2-xfer { 1203 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1204 <1 RK_PC3 2 &pcfg_pull_none>; 1205 }; 1206 1207 uart2_cts: uart2-cts { 1208 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1209 }; 1210 1211 uart2_rts: uart2-rts { 1212 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1213 }; 1214 }; 1215 }; 1216}; 1217