1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3036-cru.h> 8#include <dt-bindings/soc/rockchip,boot-mode.h> 9#include <dt-bindings/power/rk3036-power.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 compatible = "rockchip,rk3036"; 16 17 interrupt-parent = <&gic>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 mshc0 = &emmc; 27 mshc1 = &sdmmc; 28 mshc2 = &sdio; 29 serial0 = &uart0; 30 serial1 = &uart1; 31 serial2 = &uart2; 32 spi = &spi; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 enable-method = "rockchip,rk3036-smp"; 39 40 cpu0: cpu@f00 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a7"; 43 reg = <0xf00>; 44 resets = <&cru SRST_CORE0>; 45 operating-points = < 46 /* KHz uV */ 47 816000 1000000 48 >; 49 clock-latency = <40000>; 50 clocks = <&cru ARMCLK>; 51 }; 52 53 cpu1: cpu@f01 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0xf01>; 57 resets = <&cru SRST_CORE1>; 58 }; 59 }; 60 61 arm-pmu { 62 compatible = "arm,cortex-a7-pmu"; 63 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 65 interrupt-affinity = <&cpu0>, <&cpu1>; 66 }; 67 68 display-subsystem { 69 compatible = "rockchip,display-subsystem"; 70 ports = <&vop_out>; 71 }; 72 73 timer { 74 compatible = "arm,armv7-timer"; 75 arm,cpu-registers-not-fw-configured; 76 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 77 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 78 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 79 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 80 clock-frequency = <24000000>; 81 }; 82 83 xin24m: oscillator { 84 compatible = "fixed-clock"; 85 clock-frequency = <24000000>; 86 clock-output-names = "xin24m"; 87 #clock-cells = <0>; 88 }; 89 90 bus_intmem: sram@10080000 { 91 compatible = "mmio-sram"; 92 reg = <0x10080000 0x2000>; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges = <0 0x10080000 0x2000>; 96 97 smp-sram@0 { 98 compatible = "rockchip,rk3066-smp-sram"; 99 reg = <0x00 0x10>; 100 }; 101 }; 102 103 gpu: gpu@10090000 { 104 compatible = "rockchip,rk3036-mali", "arm,mali-400"; 105 reg = <0x10090000 0x10000>; 106 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 110 interrupt-names = "gp", 111 "gpmmu", 112 "pp0", 113 "ppmmu0"; 114 assigned-clocks = <&cru SCLK_GPU>; 115 assigned-clock-rates = <100000000>; 116 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; 117 clock-names = "bus", "core"; 118 power-domains = <&power RK3036_PD_GPU>; 119 resets = <&cru SRST_GPU>; 120 status = "disabled"; 121 }; 122 123 vpu: video-codec@10108000 { 124 compatible = "rockchip,rk3036-vpu"; 125 reg = <0x10108000 0x800>; 126 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-names = "vdpu"; 128 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 129 clock-names = "aclk", "hclk"; 130 iommus = <&vpu_mmu>; 131 power-domains = <&power RK3036_PD_VPU>; 132 }; 133 134 vpu_mmu: iommu@10108800 { 135 compatible = "rockchip,iommu"; 136 reg = <0x10108800 0x100>; 137 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 139 clock-names = "aclk", "iface"; 140 power-domains = <&power RK3036_PD_VPU>; 141 #iommu-cells = <0>; 142 }; 143 144 vop: vop@10118000 { 145 compatible = "rockchip,rk3036-vop"; 146 reg = <0x10118000 0x19c>; 147 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; 149 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 150 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; 151 reset-names = "axi", "ahb", "dclk"; 152 iommus = <&vop_mmu>; 153 power-domains = <&power RK3036_PD_VIO>; 154 status = "disabled"; 155 156 vop_out: port { 157 #address-cells = <1>; 158 #size-cells = <0>; 159 vop_out_hdmi: endpoint@0 { 160 reg = <0>; 161 remote-endpoint = <&hdmi_in_vop>; 162 }; 163 }; 164 }; 165 166 vop_mmu: iommu@10118300 { 167 compatible = "rockchip,iommu"; 168 reg = <0x10118300 0x100>; 169 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; 171 clock-names = "aclk", "iface"; 172 power-domains = <&power RK3036_PD_VIO>; 173 #iommu-cells = <0>; 174 status = "disabled"; 175 }; 176 177 qos_gpu: qos@1012d000 { 178 compatible = "rockchip,rk3036-qos", "syscon"; 179 reg = <0x1012d000 0x20>; 180 }; 181 182 qos_vpu: qos@1012e000 { 183 compatible = "rockchip,rk3036-qos", "syscon"; 184 reg = <0x1012e000 0x20>; 185 }; 186 187 qos_vio: qos@1012f000 { 188 compatible = "rockchip,rk3036-qos", "syscon"; 189 reg = <0x1012f000 0x20>; 190 }; 191 192 gic: interrupt-controller@10139000 { 193 compatible = "arm,gic-400"; 194 interrupt-controller; 195 #interrupt-cells = <3>; 196 #address-cells = <0>; 197 198 reg = <0x10139000 0x1000>, 199 <0x1013a000 0x2000>, 200 <0x1013c000 0x2000>, 201 <0x1013e000 0x2000>; 202 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 203 }; 204 205 usb_otg: usb@10180000 { 206 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 207 "snps,dwc2"; 208 reg = <0x10180000 0x40000>; 209 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&cru HCLK_OTG0>; 211 clock-names = "otg"; 212 dr_mode = "otg"; 213 g-np-tx-fifo-size = <16>; 214 g-rx-fifo-size = <275>; 215 g-tx-fifo-size = <256 128 128 64 64 32>; 216 status = "disabled"; 217 }; 218 219 usb_host: usb@101c0000 { 220 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 221 "snps,dwc2"; 222 reg = <0x101c0000 0x40000>; 223 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&cru HCLK_OTG1>; 225 clock-names = "otg"; 226 dr_mode = "host"; 227 status = "disabled"; 228 }; 229 230 emac: ethernet@10200000 { 231 compatible = "rockchip,rk3036-emac"; 232 reg = <0x10200000 0x4000>; 233 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 234 rockchip,grf = <&grf>; 235 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; 236 clock-names = "hclk", "macref", "macclk"; 237 /* 238 * Fix the emac parent clock is DPLL instead of APLL. 239 * since that will cause some unstable things if the cpufreq 240 * is working. (e.g: the accurate 50MHz what mac_ref need) 241 */ 242 assigned-clocks = <&cru SCLK_MACPLL>; 243 assigned-clock-parents = <&cru PLL_DPLL>; 244 max-speed = <100>; 245 phy-mode = "rmii"; 246 status = "disabled"; 247 }; 248 249 sdmmc: mmc@10214000 { 250 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 251 reg = <0x10214000 0x4000>; 252 clock-frequency = <37500000>; 253 max-frequency = <37500000>; 254 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 255 clock-names = "biu", "ciu"; 256 fifo-depth = <0x100>; 257 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 258 resets = <&cru SRST_MMC0>; 259 reset-names = "reset"; 260 status = "disabled"; 261 }; 262 263 sdio: mmc@10218000 { 264 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 265 reg = <0x10218000 0x4000>; 266 max-frequency = <37500000>; 267 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 268 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 269 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 270 fifo-depth = <0x100>; 271 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 272 resets = <&cru SRST_SDIO>; 273 reset-names = "reset"; 274 status = "disabled"; 275 }; 276 277 emmc: mmc@1021c000 { 278 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 279 reg = <0x1021c000 0x4000>; 280 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 281 bus-width = <8>; 282 cap-mmc-highspeed; 283 clock-frequency = <37500000>; 284 max-frequency = <37500000>; 285 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 286 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 287 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 288 rockchip,default-sample-phase = <158>; 289 disable-wp; 290 dmas = <&pdma 12>; 291 dma-names = "rx-tx"; 292 fifo-depth = <0x100>; 293 mmc-ddr-1_8v; 294 non-removable; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 297 resets = <&cru SRST_EMMC>; 298 reset-names = "reset"; 299 status = "disabled"; 300 }; 301 302 i2s: i2s@10220000 { 303 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; 304 reg = <0x10220000 0x4000>; 305 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 306 clock-names = "i2s_clk", "i2s_hclk"; 307 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; 308 dmas = <&pdma 0>, <&pdma 1>; 309 dma-names = "tx", "rx"; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&i2s_bus>; 312 #sound-dai-cells = <0>; 313 status = "disabled"; 314 }; 315 316 nfc: nand-controller@10500000 { 317 compatible = "rockchip,rk3036-nfc", 318 "rockchip,rk2928-nfc"; 319 reg = <0x10500000 0x4000>; 320 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 322 clock-names = "ahb", "nfc"; 323 assigned-clocks = <&cru SCLK_NANDC>; 324 assigned-clock-rates = <150000000>; 325 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 326 &flash_rdn &flash_rdy &flash_wrn>; 327 pinctrl-names = "default"; 328 status = "disabled"; 329 }; 330 331 cru: clock-controller@20000000 { 332 compatible = "rockchip,rk3036-cru"; 333 reg = <0x20000000 0x1000>; 334 clocks = <&xin24m>; 335 clock-names = "xin24m"; 336 rockchip,grf = <&grf>; 337 #clock-cells = <1>; 338 #reset-cells = <1>; 339 assigned-clocks = <&cru PLL_GPLL>; 340 assigned-clock-rates = <594000000>; 341 }; 342 343 grf: syscon@20008000 { 344 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; 345 reg = <0x20008000 0x1000>; 346 347 power: power-controller { 348 compatible = "rockchip,rk3036-power-controller"; 349 #power-domain-cells = <1>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 353 power-domain@RK3036_PD_VIO { 354 reg = <RK3036_PD_VIO>; 355 clocks = <&cru ACLK_LCDC>, 356 <&cru HCLK_LCDC>, 357 <&cru SCLK_LCDC>; 358 pm_qos = <&qos_vio>; 359 #power-domain-cells = <0>; 360 }; 361 362 power-domain@RK3036_PD_VPU { 363 reg = <RK3036_PD_VPU>; 364 clocks = <&cru ACLK_VCODEC>, 365 <&cru HCLK_VCODEC>; 366 pm_qos = <&qos_vpu>; 367 #power-domain-cells = <0>; 368 }; 369 370 power-domain@RK3036_PD_GPU { 371 reg = <RK3036_PD_GPU>; 372 clocks = <&cru SCLK_GPU>; 373 pm_qos = <&qos_gpu>; 374 #power-domain-cells = <0>; 375 }; 376 }; 377 378 reboot-mode { 379 compatible = "syscon-reboot-mode"; 380 offset = <0x1d8>; 381 mode-normal = <BOOT_NORMAL>; 382 mode-recovery = <BOOT_RECOVERY>; 383 mode-bootloader = <BOOT_FASTBOOT>; 384 mode-loader = <BOOT_BL_DOWNLOAD>; 385 }; 386 }; 387 388 acodec: acodec-ana@20030000 { 389 compatible = "rk3036-codec"; 390 reg = <0x20030000 0x4000>; 391 rockchip,grf = <&grf>; 392 clock-names = "acodec_pclk"; 393 clocks = <&cru PCLK_ACODEC>; 394 status = "disabled"; 395 }; 396 397 hdmi: hdmi@20034000 { 398 compatible = "rockchip,rk3036-inno-hdmi"; 399 reg = <0x20034000 0x4000>; 400 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cru PCLK_HDMI>; 402 clock-names = "pclk"; 403 rockchip,grf = <&grf>; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&hdmi_ctl>; 406 status = "disabled"; 407 408 hdmi_in: port { 409 #address-cells = <1>; 410 #size-cells = <0>; 411 hdmi_in_vop: endpoint@0 { 412 reg = <0>; 413 remote-endpoint = <&vop_out_hdmi>; 414 }; 415 }; 416 }; 417 418 timer: timer@20044000 { 419 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; 420 reg = <0x20044000 0x20>; 421 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&cru PCLK_TIMER>, <&xin24m>; 423 clock-names = "pclk", "timer"; 424 }; 425 426 pwm0: pwm@20050000 { 427 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 428 reg = <0x20050000 0x10>; 429 #pwm-cells = <3>; 430 clocks = <&cru PCLK_PWM>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pwm0_pin>; 433 status = "disabled"; 434 }; 435 436 pwm1: pwm@20050010 { 437 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 438 reg = <0x20050010 0x10>; 439 #pwm-cells = <3>; 440 clocks = <&cru PCLK_PWM>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pwm1_pin>; 443 status = "disabled"; 444 }; 445 446 pwm2: pwm@20050020 { 447 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 448 reg = <0x20050020 0x10>; 449 #pwm-cells = <3>; 450 clocks = <&cru PCLK_PWM>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pwm2_pin>; 453 status = "disabled"; 454 }; 455 456 pwm3: pwm@20050030 { 457 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 458 reg = <0x20050030 0x10>; 459 #pwm-cells = <2>; 460 clocks = <&cru PCLK_PWM>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pwm3_pin>; 463 status = "disabled"; 464 }; 465 466 i2c1: i2c@20056000 { 467 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 468 reg = <0x20056000 0x1000>; 469 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clock-names = "i2c"; 473 clocks = <&cru PCLK_I2C1>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&i2c1_xfer>; 476 status = "disabled"; 477 }; 478 479 i2c2: i2c@2005a000 { 480 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 481 reg = <0x2005a000 0x1000>; 482 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 clock-names = "i2c"; 486 clocks = <&cru PCLK_I2C2>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&i2c2_xfer>; 489 status = "disabled"; 490 }; 491 492 uart0: serial@20060000 { 493 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 494 reg = <0x20060000 0x100>; 495 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 496 reg-shift = <2>; 497 reg-io-width = <4>; 498 clock-frequency = <24000000>; 499 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 500 clock-names = "baudclk", "apb_pclk"; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 503 status = "disabled"; 504 }; 505 506 uart1: serial@20064000 { 507 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 508 reg = <0x20064000 0x100>; 509 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 510 reg-shift = <2>; 511 reg-io-width = <4>; 512 clock-frequency = <24000000>; 513 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 514 clock-names = "baudclk", "apb_pclk"; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&uart1_xfer>; 517 status = "disabled"; 518 }; 519 520 uart2: serial@20068000 { 521 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 522 reg = <0x20068000 0x100>; 523 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 524 reg-shift = <2>; 525 reg-io-width = <4>; 526 clock-frequency = <24000000>; 527 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 528 clock-names = "baudclk", "apb_pclk"; 529 pinctrl-names = "default"; 530 pinctrl-0 = <&uart2_xfer>; 531 status = "disabled"; 532 }; 533 534 i2c0: i2c@20072000 { 535 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 536 reg = <0x20072000 0x1000>; 537 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clock-names = "i2c"; 541 clocks = <&cru PCLK_I2C0>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&i2c0_xfer>; 544 status = "disabled"; 545 }; 546 547 spi: spi@20074000 { 548 compatible = "rockchip,rockchip-spi"; 549 reg = <0x20074000 0x1000>; 550 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>; 552 clock-names = "apb-pclk","spi_pclk"; 553 dmas = <&pdma 8>, <&pdma 9>; 554 dma-names = "tx", "rx"; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 status = "disabled"; 560 }; 561 562 pdma: dma-controller@20078000 { 563 compatible = "arm,pl330", "arm,primecell"; 564 reg = <0x20078000 0x4000>; 565 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 567 #dma-cells = <1>; 568 arm,pl330-broken-no-flushp; 569 arm,pl330-periph-burst; 570 clocks = <&cru ACLK_DMAC2>; 571 clock-names = "apb_pclk"; 572 }; 573 574 pinctrl: pinctrl { 575 compatible = "rockchip,rk3036-pinctrl"; 576 rockchip,grf = <&grf>; 577 #address-cells = <1>; 578 #size-cells = <1>; 579 ranges; 580 581 gpio0: gpio@2007c000 { 582 compatible = "rockchip,gpio-bank"; 583 reg = <0x2007c000 0x100>; 584 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&cru PCLK_GPIO0>; 586 587 gpio-controller; 588 #gpio-cells = <2>; 589 590 interrupt-controller; 591 #interrupt-cells = <2>; 592 }; 593 594 gpio1: gpio@20080000 { 595 compatible = "rockchip,gpio-bank"; 596 reg = <0x20080000 0x100>; 597 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cru PCLK_GPIO1>; 599 600 gpio-controller; 601 #gpio-cells = <2>; 602 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 }; 606 607 gpio2: gpio@20084000 { 608 compatible = "rockchip,gpio-bank"; 609 reg = <0x20084000 0x100>; 610 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cru PCLK_GPIO2>; 612 613 gpio-controller; 614 #gpio-cells = <2>; 615 616 interrupt-controller; 617 #interrupt-cells = <2>; 618 }; 619 620 pcfg_pull_default: pcfg-pull-default { 621 bias-pull-pin-default; 622 }; 623 624 pcfg_pull_none: pcfg-pull-none { 625 bias-disable; 626 }; 627 628 pwm0 { 629 pwm0_pin: pwm0-pin { 630 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 631 }; 632 }; 633 634 pwm1 { 635 pwm1_pin: pwm1-pin { 636 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; 637 }; 638 }; 639 640 pwm2 { 641 pwm2_pin: pwm2-pin { 642 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; 643 }; 644 }; 645 646 pwm3 { 647 pwm3_pin: pwm3-pin { 648 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 649 }; 650 }; 651 652 sdmmc { 653 sdmmc_clk: sdmmc-clk { 654 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 655 }; 656 657 sdmmc_cmd: sdmmc-cmd { 658 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 659 }; 660 661 sdmmc_cd: sdmmc-cd { 662 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 663 }; 664 665 sdmmc_bus1: sdmmc-bus1 { 666 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; 667 }; 668 669 sdmmc_bus4: sdmmc-bus4 { 670 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 671 <1 RK_PC3 1 &pcfg_pull_default>, 672 <1 RK_PC4 1 &pcfg_pull_default>, 673 <1 RK_PC5 1 &pcfg_pull_default>; 674 }; 675 }; 676 677 sdio { 678 sdio_bus1: sdio-bus1 { 679 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; 680 }; 681 682 sdio_bus4: sdio-bus4 { 683 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, 684 <0 RK_PB4 1 &pcfg_pull_default>, 685 <0 RK_PB5 1 &pcfg_pull_default>, 686 <0 RK_PB6 1 &pcfg_pull_default>; 687 }; 688 689 sdio_cmd: sdio-cmd { 690 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; 691 }; 692 693 sdio_clk: sdio-clk { 694 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; 695 }; 696 }; 697 698 emmc { 699 /* 700 * We run eMMC at max speed; bump up drive strength. 701 * We also have external pulls, so disable the internal ones. 702 */ 703 emmc_clk: emmc-clk { 704 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; 705 }; 706 707 emmc_cmd: emmc-cmd { 708 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; 709 }; 710 711 emmc_bus8: emmc-bus8 { 712 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 713 <1 RK_PD1 2 &pcfg_pull_default>, 714 <1 RK_PD2 2 &pcfg_pull_default>, 715 <1 RK_PD3 2 &pcfg_pull_default>, 716 <1 RK_PD4 2 &pcfg_pull_default>, 717 <1 RK_PD5 2 &pcfg_pull_default>, 718 <1 RK_PD6 2 &pcfg_pull_default>, 719 <1 RK_PD7 2 &pcfg_pull_default>; 720 }; 721 }; 722 723 nfc { 724 flash_ale: flash-ale { 725 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>; 726 }; 727 728 flash_bus8: flash-bus8 { 729 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>, 730 <1 RK_PD1 1 &pcfg_pull_default>, 731 <1 RK_PD2 1 &pcfg_pull_default>, 732 <1 RK_PD3 1 &pcfg_pull_default>, 733 <1 RK_PD4 1 &pcfg_pull_default>, 734 <1 RK_PD5 1 &pcfg_pull_default>, 735 <1 RK_PD6 1 &pcfg_pull_default>, 736 <1 RK_PD7 1 &pcfg_pull_default>; 737 }; 738 739 flash_cle: flash-cle { 740 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>; 741 }; 742 743 flash_csn0: flash-csn0 { 744 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>; 745 }; 746 747 flash_rdn: flash-rdn { 748 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>; 749 }; 750 751 flash_rdy: flash-rdy { 752 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>; 753 }; 754 755 flash_wrn: flash-wrn { 756 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>; 757 }; 758 }; 759 760 emac { 761 emac_xfer: emac-xfer { 762 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ 763 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ 764 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ 765 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ 766 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ 767 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ 768 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ 769 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ 770 }; 771 772 emac_mdio: emac-mdio { 773 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ 774 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ 775 }; 776 }; 777 778 i2c0 { 779 i2c0_xfer: i2c0-xfer { 780 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 781 <0 RK_PA1 1 &pcfg_pull_none>; 782 }; 783 }; 784 785 i2c1 { 786 i2c1_xfer: i2c1-xfer { 787 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 788 <0 RK_PA3 1 &pcfg_pull_none>; 789 }; 790 }; 791 792 i2c2 { 793 i2c2_xfer: i2c2-xfer { 794 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 795 <2 RK_PC5 1 &pcfg_pull_none>; 796 }; 797 }; 798 799 i2s { 800 i2s_bus: i2s-bus { 801 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 802 <1 RK_PA1 1 &pcfg_pull_default>, 803 <1 RK_PA2 1 &pcfg_pull_default>, 804 <1 RK_PA3 1 &pcfg_pull_default>, 805 <1 RK_PA4 1 &pcfg_pull_default>, 806 <1 RK_PA5 1 &pcfg_pull_default>; 807 }; 808 }; 809 810 hdmi { 811 hdmi_ctl: hdmi-ctl { 812 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, 813 <1 RK_PB1 1 &pcfg_pull_none>, 814 <1 RK_PB2 1 &pcfg_pull_none>, 815 <1 RK_PB3 1 &pcfg_pull_none>; 816 }; 817 }; 818 819 uart0 { 820 uart0_xfer: uart0-xfer { 821 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 822 <0 RK_PC1 1 &pcfg_pull_none>; 823 }; 824 825 uart0_cts: uart0-cts { 826 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; 827 }; 828 829 uart0_rts: uart0-rts { 830 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; 831 }; 832 }; 833 834 uart1 { 835 uart1_xfer: uart1-xfer { 836 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, 837 <2 RK_PC7 1 &pcfg_pull_none>; 838 }; 839 /* no rts / cts for uart1 */ 840 }; 841 842 uart2 { 843 uart2_xfer: uart2-xfer { 844 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 845 <1 RK_PC3 2 &pcfg_pull_none>; 846 }; 847 /* no rts / cts for uart2 */ 848 }; 849 850 spi-pins { 851 spi_txd:spi-txd { 852 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 853 }; 854 855 spi_rxd:spi-rxd { 856 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 857 }; 858 859 spi_clk:spi-clk { 860 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 861 }; 862 863 spi_cs0:spi-cs0 { 864 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 865 866 }; 867 868 spi_cs1:spi-cs1 { 869 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 870 871 }; 872 }; 873 }; 874}; 875