1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC 4 * 5 * Copyright (C) 2014-2015 Renesas Electronics Corporation 6 */ 7 8#include <dt-bindings/clock/r8a7793-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/power/r8a7793-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7793"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &i2c6; 26 i2c7 = &i2c7; 27 i2c8 = &i2c8; 28 spi0 = &qspi; 29 }; 30 31 /* 32 * The external audio clocks are configured as 0 Hz fixed frequency 33 * clocks by default. 34 * Boards that provide audio clocks should override them. 35 */ 36 audio_clk_a: audio_clk_a { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 audio_clk_b: audio_clk_b { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 audio_clk_c: audio_clk_c { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 }; 51 52 /* External CAN clock */ 53 can_clk: can { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 /* This value must be overridden by the board. */ 57 clock-frequency = <0>; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a15"; 67 reg = <0>; 68 clock-frequency = <1500000000>; 69 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 70 power-domains = <&sysc R8A7793_PD_CA15_CPU0>; 71 enable-method = "renesas,apmu"; 72 voltage-tolerance = <1>; /* 1% */ 73 clock-latency = <300000>; /* 300 us */ 74 75 /* kHz - uV - OPPs unknown yet */ 76 operating-points = <1500000 1000000>, 77 <1312500 1000000>, 78 <1125000 1000000>, 79 < 937500 1000000>, 80 < 750000 1000000>, 81 < 375000 1000000>; 82 next-level-cache = <&L2_CA15>; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a15"; 88 reg = <1>; 89 clock-frequency = <1500000000>; 90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 91 power-domains = <&sysc R8A7793_PD_CA15_CPU1>; 92 enable-method = "renesas,apmu"; 93 voltage-tolerance = <1>; /* 1% */ 94 clock-latency = <300000>; /* 300 us */ 95 96 /* kHz - uV - OPPs unknown yet */ 97 operating-points = <1500000 1000000>, 98 <1312500 1000000>, 99 <1125000 1000000>, 100 < 937500 1000000>, 101 < 750000 1000000>, 102 < 375000 1000000>; 103 next-level-cache = <&L2_CA15>; 104 }; 105 106 L2_CA15: cache-controller-0 { 107 compatible = "cache"; 108 power-domains = <&sysc R8A7793_PD_CA15_SCU>; 109 cache-unified; 110 cache-level = <2>; 111 }; 112 }; 113 114 /* External root clock */ 115 extal_clk: extal { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 /* This value must be overridden by the board. */ 119 clock-frequency = <0>; 120 }; 121 122 pmu { 123 compatible = "arm,cortex-a15-pmu"; 124 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 125 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 126 interrupt-affinity = <&cpu0>, <&cpu1>; 127 }; 128 129 /* External SCIF clock */ 130 scif_clk: scif { 131 compatible = "fixed-clock"; 132 #clock-cells = <0>; 133 /* This value must be overridden by the board. */ 134 clock-frequency = <0>; 135 }; 136 137 soc { 138 compatible = "simple-bus"; 139 interrupt-parent = <&gic>; 140 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 145 rwdt: watchdog@e6020000 { 146 compatible = "renesas,r8a7793-wdt", 147 "renesas,rcar-gen2-wdt"; 148 reg = <0 0xe6020000 0 0x0c>; 149 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&cpg CPG_MOD 402>; 151 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 152 resets = <&cpg 402>; 153 status = "disabled"; 154 }; 155 156 gpio0: gpio@e6050000 { 157 compatible = "renesas,gpio-r8a7793", 158 "renesas,rcar-gen2-gpio"; 159 reg = <0 0xe6050000 0 0x50>; 160 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 161 #gpio-cells = <2>; 162 gpio-controller; 163 gpio-ranges = <&pfc 0 0 32>; 164 #interrupt-cells = <2>; 165 interrupt-controller; 166 clocks = <&cpg CPG_MOD 912>; 167 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 168 resets = <&cpg 912>; 169 }; 170 171 gpio1: gpio@e6051000 { 172 compatible = "renesas,gpio-r8a7793", 173 "renesas,rcar-gen2-gpio"; 174 reg = <0 0xe6051000 0 0x50>; 175 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 176 #gpio-cells = <2>; 177 gpio-controller; 178 gpio-ranges = <&pfc 0 32 26>; 179 #interrupt-cells = <2>; 180 interrupt-controller; 181 clocks = <&cpg CPG_MOD 911>; 182 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 183 resets = <&cpg 911>; 184 }; 185 186 gpio2: gpio@e6052000 { 187 compatible = "renesas,gpio-r8a7793", 188 "renesas,rcar-gen2-gpio"; 189 reg = <0 0xe6052000 0 0x50>; 190 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 191 #gpio-cells = <2>; 192 gpio-controller; 193 gpio-ranges = <&pfc 0 64 32>; 194 #interrupt-cells = <2>; 195 interrupt-controller; 196 clocks = <&cpg CPG_MOD 910>; 197 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 198 resets = <&cpg 910>; 199 }; 200 201 gpio3: gpio@e6053000 { 202 compatible = "renesas,gpio-r8a7793", 203 "renesas,rcar-gen2-gpio"; 204 reg = <0 0xe6053000 0 0x50>; 205 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 206 #gpio-cells = <2>; 207 gpio-controller; 208 gpio-ranges = <&pfc 0 96 32>; 209 #interrupt-cells = <2>; 210 interrupt-controller; 211 clocks = <&cpg CPG_MOD 909>; 212 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 213 resets = <&cpg 909>; 214 }; 215 216 gpio4: gpio@e6054000 { 217 compatible = "renesas,gpio-r8a7793", 218 "renesas,rcar-gen2-gpio"; 219 reg = <0 0xe6054000 0 0x50>; 220 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 221 #gpio-cells = <2>; 222 gpio-controller; 223 gpio-ranges = <&pfc 0 128 32>; 224 #interrupt-cells = <2>; 225 interrupt-controller; 226 clocks = <&cpg CPG_MOD 908>; 227 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 228 resets = <&cpg 908>; 229 }; 230 231 gpio5: gpio@e6055000 { 232 compatible = "renesas,gpio-r8a7793", 233 "renesas,rcar-gen2-gpio"; 234 reg = <0 0xe6055000 0 0x50>; 235 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 236 #gpio-cells = <2>; 237 gpio-controller; 238 gpio-ranges = <&pfc 0 160 32>; 239 #interrupt-cells = <2>; 240 interrupt-controller; 241 clocks = <&cpg CPG_MOD 907>; 242 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 243 resets = <&cpg 907>; 244 }; 245 246 gpio6: gpio@e6055400 { 247 compatible = "renesas,gpio-r8a7793", 248 "renesas,rcar-gen2-gpio"; 249 reg = <0 0xe6055400 0 0x50>; 250 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 251 #gpio-cells = <2>; 252 gpio-controller; 253 gpio-ranges = <&pfc 0 192 32>; 254 #interrupt-cells = <2>; 255 interrupt-controller; 256 clocks = <&cpg CPG_MOD 905>; 257 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 258 resets = <&cpg 905>; 259 }; 260 261 gpio7: gpio@e6055800 { 262 compatible = "renesas,gpio-r8a7793", 263 "renesas,rcar-gen2-gpio"; 264 reg = <0 0xe6055800 0 0x50>; 265 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 266 #gpio-cells = <2>; 267 gpio-controller; 268 gpio-ranges = <&pfc 0 224 26>; 269 #interrupt-cells = <2>; 270 interrupt-controller; 271 clocks = <&cpg CPG_MOD 904>; 272 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 273 resets = <&cpg 904>; 274 }; 275 276 pfc: pinctrl@e6060000 { 277 compatible = "renesas,pfc-r8a7793"; 278 reg = <0 0xe6060000 0 0x250>; 279 }; 280 281 /* Special CPG clocks */ 282 cpg: clock-controller@e6150000 { 283 compatible = "renesas,r8a7793-cpg-mssr"; 284 reg = <0 0xe6150000 0 0x1000>; 285 clocks = <&extal_clk>, <&usb_extal_clk>; 286 clock-names = "extal", "usb_extal"; 287 #clock-cells = <2>; 288 #power-domain-cells = <0>; 289 #reset-cells = <1>; 290 }; 291 292 apmu@e6152000 { 293 compatible = "renesas,r8a7793-apmu", "renesas,apmu"; 294 reg = <0 0xe6152000 0 0x188>; 295 cpus = <&cpu0>, <&cpu1>; 296 }; 297 298 rst: reset-controller@e6160000 { 299 compatible = "renesas,r8a7793-rst"; 300 reg = <0 0xe6160000 0 0x0100>; 301 }; 302 303 sysc: system-controller@e6180000 { 304 compatible = "renesas,r8a7793-sysc"; 305 reg = <0 0xe6180000 0 0x0200>; 306 #power-domain-cells = <1>; 307 }; 308 309 irqc0: interrupt-controller@e61c0000 { 310 compatible = "renesas,irqc-r8a7793", "renesas,irqc"; 311 #interrupt-cells = <2>; 312 interrupt-controller; 313 reg = <0 0xe61c0000 0 0x200>; 314 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&cpg CPG_MOD 407>; 325 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 326 resets = <&cpg 407>; 327 }; 328 329 thermal: thermal@e61f0000 { 330 compatible = "renesas,thermal-r8a7793", 331 "renesas,rcar-gen2-thermal", 332 "renesas,rcar-thermal"; 333 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; 334 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&cpg CPG_MOD 522>; 336 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 337 resets = <&cpg 522>; 338 #thermal-sensor-cells = <0>; 339 }; 340 341 ipmmu_sy0: iommu@e6280000 { 342 compatible = "renesas,ipmmu-r8a7793", 343 "renesas,ipmmu-vmsa"; 344 reg = <0 0xe6280000 0 0x1000>; 345 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 347 #iommu-cells = <1>; 348 status = "disabled"; 349 }; 350 351 ipmmu_sy1: iommu@e6290000 { 352 compatible = "renesas,ipmmu-r8a7793", 353 "renesas,ipmmu-vmsa"; 354 reg = <0 0xe6290000 0 0x1000>; 355 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 356 #iommu-cells = <1>; 357 status = "disabled"; 358 }; 359 360 ipmmu_ds: iommu@e6740000 { 361 compatible = "renesas,ipmmu-r8a7793", 362 "renesas,ipmmu-vmsa"; 363 reg = <0 0xe6740000 0 0x1000>; 364 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 366 #iommu-cells = <1>; 367 status = "disabled"; 368 }; 369 370 ipmmu_mp: iommu@ec680000 { 371 compatible = "renesas,ipmmu-r8a7793", 372 "renesas,ipmmu-vmsa"; 373 reg = <0 0xec680000 0 0x1000>; 374 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 375 #iommu-cells = <1>; 376 status = "disabled"; 377 }; 378 379 ipmmu_mx: iommu@fe951000 { 380 compatible = "renesas,ipmmu-r8a7793", 381 "renesas,ipmmu-vmsa"; 382 reg = <0 0xfe951000 0 0x1000>; 383 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 385 #iommu-cells = <1>; 386 status = "disabled"; 387 }; 388 389 ipmmu_rt: iommu@ffc80000 { 390 compatible = "renesas,ipmmu-r8a7793", 391 "renesas,ipmmu-vmsa"; 392 reg = <0 0xffc80000 0 0x1000>; 393 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 394 #iommu-cells = <1>; 395 status = "disabled"; 396 }; 397 398 ipmmu_gp: iommu@e62a0000 { 399 compatible = "renesas,ipmmu-r8a7793", 400 "renesas,ipmmu-vmsa"; 401 reg = <0 0xe62a0000 0 0x1000>; 402 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 404 #iommu-cells = <1>; 405 status = "disabled"; 406 }; 407 408 icram0: sram@e63a0000 { 409 compatible = "mmio-sram"; 410 reg = <0 0xe63a0000 0 0x12000>; 411 #address-cells = <1>; 412 #size-cells = <1>; 413 ranges = <0 0 0xe63a0000 0x12000>; 414 }; 415 416 icram1: sram@e63c0000 { 417 compatible = "mmio-sram"; 418 reg = <0 0xe63c0000 0 0x1000>; 419 #address-cells = <1>; 420 #size-cells = <1>; 421 ranges = <0 0 0xe63c0000 0x1000>; 422 423 smp-sram@0 { 424 compatible = "renesas,smp-sram"; 425 reg = <0 0x100>; 426 }; 427 }; 428 429 /* The memory map in the User's Manual maps the cores to 430 * bus numbers 431 */ 432 i2c0: i2c@e6508000 { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 compatible = "renesas,i2c-r8a7793", 436 "renesas,rcar-gen2-i2c"; 437 reg = <0 0xe6508000 0 0x40>; 438 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&cpg CPG_MOD 931>; 440 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 441 resets = <&cpg 931>; 442 i2c-scl-internal-delay-ns = <6>; 443 status = "disabled"; 444 }; 445 446 i2c1: i2c@e6518000 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 compatible = "renesas,i2c-r8a7793", 450 "renesas,rcar-gen2-i2c"; 451 reg = <0 0xe6518000 0 0x40>; 452 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cpg CPG_MOD 930>; 454 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 455 resets = <&cpg 930>; 456 i2c-scl-internal-delay-ns = <6>; 457 status = "disabled"; 458 }; 459 460 i2c2: i2c@e6530000 { 461 #address-cells = <1>; 462 #size-cells = <0>; 463 compatible = "renesas,i2c-r8a7793", 464 "renesas,rcar-gen2-i2c"; 465 reg = <0 0xe6530000 0 0x40>; 466 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&cpg CPG_MOD 929>; 468 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 469 resets = <&cpg 929>; 470 i2c-scl-internal-delay-ns = <6>; 471 status = "disabled"; 472 }; 473 474 i2c3: i2c@e6540000 { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 compatible = "renesas,i2c-r8a7793", 478 "renesas,rcar-gen2-i2c"; 479 reg = <0 0xe6540000 0 0x40>; 480 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&cpg CPG_MOD 928>; 482 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 483 resets = <&cpg 928>; 484 i2c-scl-internal-delay-ns = <6>; 485 status = "disabled"; 486 }; 487 488 i2c4: i2c@e6520000 { 489 #address-cells = <1>; 490 #size-cells = <0>; 491 compatible = "renesas,i2c-r8a7793", 492 "renesas,rcar-gen2-i2c"; 493 reg = <0 0xe6520000 0 0x40>; 494 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&cpg CPG_MOD 927>; 496 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 497 resets = <&cpg 927>; 498 i2c-scl-internal-delay-ns = <6>; 499 status = "disabled"; 500 }; 501 502 i2c5: i2c@e6528000 { 503 /* doesn't need pinmux */ 504 #address-cells = <1>; 505 #size-cells = <0>; 506 compatible = "renesas,i2c-r8a7793", 507 "renesas,rcar-gen2-i2c"; 508 reg = <0 0xe6528000 0 0x40>; 509 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&cpg CPG_MOD 925>; 511 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 512 resets = <&cpg 925>; 513 i2c-scl-internal-delay-ns = <110>; 514 status = "disabled"; 515 }; 516 517 i2c6: i2c@e60b0000 { 518 /* doesn't need pinmux */ 519 #address-cells = <1>; 520 #size-cells = <0>; 521 compatible = "renesas,iic-r8a7793", 522 "renesas,rcar-gen2-iic", 523 "renesas,rmobile-iic"; 524 reg = <0 0xe60b0000 0 0x425>; 525 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&cpg CPG_MOD 926>; 527 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 528 <&dmac1 0x77>, <&dmac1 0x78>; 529 dma-names = "tx", "rx", "tx", "rx"; 530 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 531 resets = <&cpg 926>; 532 status = "disabled"; 533 }; 534 535 i2c7: i2c@e6500000 { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 compatible = "renesas,iic-r8a7793", 539 "renesas,rcar-gen2-iic", 540 "renesas,rmobile-iic"; 541 reg = <0 0xe6500000 0 0x425>; 542 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cpg CPG_MOD 318>; 544 dmas = <&dmac0 0x61>, <&dmac0 0x62>, 545 <&dmac1 0x61>, <&dmac1 0x62>; 546 dma-names = "tx", "rx", "tx", "rx"; 547 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 548 resets = <&cpg 318>; 549 status = "disabled"; 550 }; 551 552 i2c8: i2c@e6510000 { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 compatible = "renesas,iic-r8a7793", 556 "renesas,rcar-gen2-iic", 557 "renesas,rmobile-iic"; 558 reg = <0 0xe6510000 0 0x425>; 559 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&cpg CPG_MOD 323>; 561 dmas = <&dmac0 0x65>, <&dmac0 0x66>, 562 <&dmac1 0x65>, <&dmac1 0x66>; 563 dma-names = "tx", "rx", "tx", "rx"; 564 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 565 resets = <&cpg 323>; 566 status = "disabled"; 567 }; 568 569 dmac0: dma-controller@e6700000 { 570 compatible = "renesas,dmac-r8a7793", 571 "renesas,rcar-dmac"; 572 reg = <0 0xe6700000 0 0x20000>; 573 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 589 interrupt-names = "error", 590 "ch0", "ch1", "ch2", "ch3", 591 "ch4", "ch5", "ch6", "ch7", 592 "ch8", "ch9", "ch10", "ch11", 593 "ch12", "ch13", "ch14"; 594 clocks = <&cpg CPG_MOD 219>; 595 clock-names = "fck"; 596 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 597 resets = <&cpg 219>; 598 #dma-cells = <1>; 599 dma-channels = <15>; 600 }; 601 602 dmac1: dma-controller@e6720000 { 603 compatible = "renesas,dmac-r8a7793", 604 "renesas,rcar-dmac"; 605 reg = <0 0xe6720000 0 0x20000>; 606 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 622 interrupt-names = "error", 623 "ch0", "ch1", "ch2", "ch3", 624 "ch4", "ch5", "ch6", "ch7", 625 "ch8", "ch9", "ch10", "ch11", 626 "ch12", "ch13", "ch14"; 627 clocks = <&cpg CPG_MOD 218>; 628 clock-names = "fck"; 629 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 630 resets = <&cpg 218>; 631 #dma-cells = <1>; 632 dma-channels = <15>; 633 }; 634 635 qspi: spi@e6b10000 { 636 compatible = "renesas,qspi-r8a7793", "renesas,qspi"; 637 reg = <0 0xe6b10000 0 0x2c>; 638 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&cpg CPG_MOD 917>; 640 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 641 <&dmac1 0x17>, <&dmac1 0x18>; 642 dma-names = "tx", "rx", "tx", "rx"; 643 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 644 resets = <&cpg 917>; 645 num-cs = <1>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 scifa0: serial@e6c40000 { 652 compatible = "renesas,scifa-r8a7793", 653 "renesas,rcar-gen2-scifa", "renesas,scifa"; 654 reg = <0 0xe6c40000 0 64>; 655 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&cpg CPG_MOD 204>; 657 clock-names = "fck"; 658 dmas = <&dmac0 0x21>, <&dmac0 0x22>, 659 <&dmac1 0x21>, <&dmac1 0x22>; 660 dma-names = "tx", "rx", "tx", "rx"; 661 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 662 resets = <&cpg 204>; 663 status = "disabled"; 664 }; 665 666 scifa1: serial@e6c50000 { 667 compatible = "renesas,scifa-r8a7793", 668 "renesas,rcar-gen2-scifa", "renesas,scifa"; 669 reg = <0 0xe6c50000 0 64>; 670 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 203>; 672 clock-names = "fck"; 673 dmas = <&dmac0 0x25>, <&dmac0 0x26>, 674 <&dmac1 0x25>, <&dmac1 0x26>; 675 dma-names = "tx", "rx", "tx", "rx"; 676 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 677 resets = <&cpg 203>; 678 status = "disabled"; 679 }; 680 681 scifa2: serial@e6c60000 { 682 compatible = "renesas,scifa-r8a7793", 683 "renesas,rcar-gen2-scifa", "renesas,scifa"; 684 reg = <0 0xe6c60000 0 64>; 685 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&cpg CPG_MOD 202>; 687 clock-names = "fck"; 688 dmas = <&dmac0 0x27>, <&dmac0 0x28>, 689 <&dmac1 0x27>, <&dmac1 0x28>; 690 dma-names = "tx", "rx", "tx", "rx"; 691 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 692 resets = <&cpg 202>; 693 status = "disabled"; 694 }; 695 696 scifa3: serial@e6c70000 { 697 compatible = "renesas,scifa-r8a7793", 698 "renesas,rcar-gen2-scifa", "renesas,scifa"; 699 reg = <0 0xe6c70000 0 64>; 700 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cpg CPG_MOD 1106>; 702 clock-names = "fck"; 703 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, 704 <&dmac1 0x1b>, <&dmac1 0x1c>; 705 dma-names = "tx", "rx", "tx", "rx"; 706 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 707 resets = <&cpg 1106>; 708 status = "disabled"; 709 }; 710 711 scifa4: serial@e6c78000 { 712 compatible = "renesas,scifa-r8a7793", 713 "renesas,rcar-gen2-scifa", "renesas,scifa"; 714 reg = <0 0xe6c78000 0 64>; 715 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&cpg CPG_MOD 1107>; 717 clock-names = "fck"; 718 dmas = <&dmac0 0x1f>, <&dmac0 0x20>, 719 <&dmac1 0x1f>, <&dmac1 0x20>; 720 dma-names = "tx", "rx", "tx", "rx"; 721 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 722 resets = <&cpg 1107>; 723 status = "disabled"; 724 }; 725 726 scifa5: serial@e6c80000 { 727 compatible = "renesas,scifa-r8a7793", 728 "renesas,rcar-gen2-scifa", "renesas,scifa"; 729 reg = <0 0xe6c80000 0 64>; 730 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cpg CPG_MOD 1108>; 732 clock-names = "fck"; 733 dmas = <&dmac0 0x23>, <&dmac0 0x24>, 734 <&dmac1 0x23>, <&dmac1 0x24>; 735 dma-names = "tx", "rx", "tx", "rx"; 736 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 737 resets = <&cpg 1108>; 738 status = "disabled"; 739 }; 740 741 scifb0: serial@e6c20000 { 742 compatible = "renesas,scifb-r8a7793", 743 "renesas,rcar-gen2-scifb", "renesas,scifb"; 744 reg = <0 0xe6c20000 0 0x100>; 745 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&cpg CPG_MOD 206>; 747 clock-names = "fck"; 748 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 749 <&dmac1 0x3d>, <&dmac1 0x3e>; 750 dma-names = "tx", "rx", "tx", "rx"; 751 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 752 resets = <&cpg 206>; 753 status = "disabled"; 754 }; 755 756 scifb1: serial@e6c30000 { 757 compatible = "renesas,scifb-r8a7793", 758 "renesas,rcar-gen2-scifb", "renesas,scifb"; 759 reg = <0 0xe6c30000 0 0x100>; 760 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&cpg CPG_MOD 207>; 762 clock-names = "fck"; 763 dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 764 <&dmac1 0x19>, <&dmac1 0x1a>; 765 dma-names = "tx", "rx", "tx", "rx"; 766 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 767 resets = <&cpg 207>; 768 status = "disabled"; 769 }; 770 771 scifb2: serial@e6ce0000 { 772 compatible = "renesas,scifb-r8a7793", 773 "renesas,rcar-gen2-scifb", "renesas,scifb"; 774 reg = <0 0xe6ce0000 0 0x100>; 775 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&cpg CPG_MOD 216>; 777 clock-names = "fck"; 778 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 779 <&dmac1 0x1d>, <&dmac1 0x1e>; 780 dma-names = "tx", "rx", "tx", "rx"; 781 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 782 resets = <&cpg 216>; 783 status = "disabled"; 784 }; 785 786 scif0: serial@e6e60000 { 787 compatible = "renesas,scif-r8a7793", 788 "renesas,rcar-gen2-scif", "renesas,scif"; 789 reg = <0 0xe6e60000 0 64>; 790 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 792 <&scif_clk>; 793 clock-names = "fck", "brg_int", "scif_clk"; 794 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 795 <&dmac1 0x29>, <&dmac1 0x2a>; 796 dma-names = "tx", "rx", "tx", "rx"; 797 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 798 resets = <&cpg 721>; 799 status = "disabled"; 800 }; 801 802 scif1: serial@e6e68000 { 803 compatible = "renesas,scif-r8a7793", 804 "renesas,rcar-gen2-scif", "renesas,scif"; 805 reg = <0 0xe6e68000 0 64>; 806 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 808 <&scif_clk>; 809 clock-names = "fck", "brg_int", "scif_clk"; 810 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 811 <&dmac1 0x2d>, <&dmac1 0x2e>; 812 dma-names = "tx", "rx", "tx", "rx"; 813 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 814 resets = <&cpg 720>; 815 status = "disabled"; 816 }; 817 818 scif2: serial@e6e58000 { 819 compatible = "renesas,scif-r8a7793", 820 "renesas,rcar-gen2-scif", "renesas,scif"; 821 reg = <0 0xe6e58000 0 64>; 822 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 824 <&scif_clk>; 825 clock-names = "fck", "brg_int", "scif_clk"; 826 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 827 <&dmac1 0x2b>, <&dmac1 0x2c>; 828 dma-names = "tx", "rx", "tx", "rx"; 829 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 830 resets = <&cpg 719>; 831 status = "disabled"; 832 }; 833 834 scif3: serial@e6ea8000 { 835 compatible = "renesas,scif-r8a7793", 836 "renesas,rcar-gen2-scif", "renesas,scif"; 837 reg = <0 0xe6ea8000 0 64>; 838 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 840 <&scif_clk>; 841 clock-names = "fck", "brg_int", "scif_clk"; 842 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 843 <&dmac1 0x2f>, <&dmac1 0x30>; 844 dma-names = "tx", "rx", "tx", "rx"; 845 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 846 resets = <&cpg 718>; 847 status = "disabled"; 848 }; 849 850 scif4: serial@e6ee0000 { 851 compatible = "renesas,scif-r8a7793", 852 "renesas,rcar-gen2-scif", "renesas,scif"; 853 reg = <0 0xe6ee0000 0 64>; 854 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 856 <&scif_clk>; 857 clock-names = "fck", "brg_int", "scif_clk"; 858 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 859 <&dmac1 0xfb>, <&dmac1 0xfc>; 860 dma-names = "tx", "rx", "tx", "rx"; 861 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 862 resets = <&cpg 715>; 863 status = "disabled"; 864 }; 865 866 scif5: serial@e6ee8000 { 867 compatible = "renesas,scif-r8a7793", 868 "renesas,rcar-gen2-scif", "renesas,scif"; 869 reg = <0 0xe6ee8000 0 64>; 870 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 872 <&scif_clk>; 873 clock-names = "fck", "brg_int", "scif_clk"; 874 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 875 <&dmac1 0xfd>, <&dmac1 0xfe>; 876 dma-names = "tx", "rx", "tx", "rx"; 877 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 878 resets = <&cpg 714>; 879 status = "disabled"; 880 }; 881 882 hscif0: serial@e62c0000 { 883 compatible = "renesas,hscif-r8a7793", 884 "renesas,rcar-gen2-hscif", "renesas,hscif"; 885 reg = <0 0xe62c0000 0 96>; 886 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 888 <&scif_clk>; 889 clock-names = "fck", "brg_int", "scif_clk"; 890 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 891 <&dmac1 0x39>, <&dmac1 0x3a>; 892 dma-names = "tx", "rx", "tx", "rx"; 893 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 894 resets = <&cpg 717>; 895 status = "disabled"; 896 }; 897 898 hscif1: serial@e62c8000 { 899 compatible = "renesas,hscif-r8a7793", 900 "renesas,rcar-gen2-hscif", "renesas,hscif"; 901 reg = <0 0xe62c8000 0 96>; 902 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 904 <&scif_clk>; 905 clock-names = "fck", "brg_int", "scif_clk"; 906 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 907 <&dmac1 0x4d>, <&dmac1 0x4e>; 908 dma-names = "tx", "rx", "tx", "rx"; 909 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 910 resets = <&cpg 716>; 911 status = "disabled"; 912 }; 913 914 hscif2: serial@e62d0000 { 915 compatible = "renesas,hscif-r8a7793", 916 "renesas,rcar-gen2-hscif", "renesas,hscif"; 917 reg = <0 0xe62d0000 0 96>; 918 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 920 <&scif_clk>; 921 clock-names = "fck", "brg_int", "scif_clk"; 922 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, 923 <&dmac1 0x3b>, <&dmac1 0x3c>; 924 dma-names = "tx", "rx", "tx", "rx"; 925 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 926 resets = <&cpg 713>; 927 status = "disabled"; 928 }; 929 930 can0: can@e6e80000 { 931 compatible = "renesas,can-r8a7793", 932 "renesas,rcar-gen2-can"; 933 reg = <0 0xe6e80000 0 0x1000>; 934 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, 936 <&can_clk>; 937 clock-names = "clkp1", "clkp2", "can_clk"; 938 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 939 resets = <&cpg 916>; 940 status = "disabled"; 941 }; 942 943 can1: can@e6e88000 { 944 compatible = "renesas,can-r8a7793", 945 "renesas,rcar-gen2-can"; 946 reg = <0 0xe6e88000 0 0x1000>; 947 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, 949 <&can_clk>; 950 clock-names = "clkp1", "clkp2", "can_clk"; 951 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 952 resets = <&cpg 915>; 953 status = "disabled"; 954 }; 955 956 vin0: video@e6ef0000 { 957 compatible = "renesas,vin-r8a7793", 958 "renesas,rcar-gen2-vin"; 959 reg = <0 0xe6ef0000 0 0x1000>; 960 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&cpg CPG_MOD 811>; 962 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 963 resets = <&cpg 811>; 964 status = "disabled"; 965 }; 966 967 vin1: video@e6ef1000 { 968 compatible = "renesas,vin-r8a7793", 969 "renesas,rcar-gen2-vin"; 970 reg = <0 0xe6ef1000 0 0x1000>; 971 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&cpg CPG_MOD 810>; 973 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 974 resets = <&cpg 810>; 975 status = "disabled"; 976 }; 977 978 vin2: video@e6ef2000 { 979 compatible = "renesas,vin-r8a7793", 980 "renesas,rcar-gen2-vin"; 981 reg = <0 0xe6ef2000 0 0x1000>; 982 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cpg CPG_MOD 809>; 984 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 985 resets = <&cpg 809>; 986 status = "disabled"; 987 }; 988 989 rcar_sound: sound@ec500000 { 990 /* 991 * #sound-dai-cells is required if simple-card 992 * 993 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 994 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 995 */ 996 compatible = "renesas,rcar_sound-r8a7793", 997 "renesas,rcar_sound-gen2"; 998 reg = <0 0xec500000 0 0x1000>, /* SCU */ 999 <0 0xec5a0000 0 0x100>, /* ADG */ 1000 <0 0xec540000 0 0x1000>, /* SSIU */ 1001 <0 0xec541000 0 0x280>, /* SSI */ 1002 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1003 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1004 1005 clocks = <&cpg CPG_MOD 1005>, 1006 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1007 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1008 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1009 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1010 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1011 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1012 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1013 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1014 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1015 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1016 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1017 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, 1018 <&cpg CPG_CORE R8A7793_CLK_M2>; 1019 clock-names = "ssi-all", 1020 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1021 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1022 "ssi.1", "ssi.0", 1023 "src.9", "src.8", "src.7", "src.6", 1024 "src.5", "src.4", "src.3", "src.2", 1025 "src.1", "src.0", 1026 "dvc.0", "dvc.1", 1027 "clk_a", "clk_b", "clk_c", "clk_i"; 1028 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1029 resets = <&cpg 1005>, 1030 <&cpg 1006>, <&cpg 1007>, 1031 <&cpg 1008>, <&cpg 1009>, 1032 <&cpg 1010>, <&cpg 1011>, 1033 <&cpg 1012>, <&cpg 1013>, 1034 <&cpg 1014>, <&cpg 1015>; 1035 reset-names = "ssi-all", 1036 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1037 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1038 "ssi.1", "ssi.0"; 1039 1040 status = "disabled"; 1041 1042 rcar_sound,dvc { 1043 dvc0: dvc-0 { 1044 dmas = <&audma1 0xbc>; 1045 dma-names = "tx"; 1046 }; 1047 dvc1: dvc-1 { 1048 dmas = <&audma1 0xbe>; 1049 dma-names = "tx"; 1050 }; 1051 }; 1052 1053 rcar_sound,src { 1054 src0: src-0 { 1055 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1056 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1057 dma-names = "rx", "tx"; 1058 }; 1059 src1: src-1 { 1060 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1061 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1062 dma-names = "rx", "tx"; 1063 }; 1064 src2: src-2 { 1065 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1066 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1067 dma-names = "rx", "tx"; 1068 }; 1069 src3: src-3 { 1070 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1071 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1072 dma-names = "rx", "tx"; 1073 }; 1074 src4: src-4 { 1075 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1076 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1077 dma-names = "rx", "tx"; 1078 }; 1079 src5: src-5 { 1080 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1081 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1082 dma-names = "rx", "tx"; 1083 }; 1084 src6: src-6 { 1085 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1086 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1087 dma-names = "rx", "tx"; 1088 }; 1089 src7: src-7 { 1090 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1091 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1092 dma-names = "rx", "tx"; 1093 }; 1094 src8: src-8 { 1095 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1096 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1097 dma-names = "rx", "tx"; 1098 }; 1099 src9: src-9 { 1100 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1101 dmas = <&audma0 0x97>, <&audma1 0xba>; 1102 dma-names = "rx", "tx"; 1103 }; 1104 }; 1105 1106 rcar_sound,ssi { 1107 ssi0: ssi-0 { 1108 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1109 dmas = <&audma0 0x01>, <&audma1 0x02>, 1110 <&audma0 0x15>, <&audma1 0x16>; 1111 dma-names = "rx", "tx", "rxu", "txu"; 1112 }; 1113 ssi1: ssi-1 { 1114 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1115 dmas = <&audma0 0x03>, <&audma1 0x04>, 1116 <&audma0 0x49>, <&audma1 0x4a>; 1117 dma-names = "rx", "tx", "rxu", "txu"; 1118 }; 1119 ssi2: ssi-2 { 1120 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1121 dmas = <&audma0 0x05>, <&audma1 0x06>, 1122 <&audma0 0x63>, <&audma1 0x64>; 1123 dma-names = "rx", "tx", "rxu", "txu"; 1124 }; 1125 ssi3: ssi-3 { 1126 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1127 dmas = <&audma0 0x07>, <&audma1 0x08>, 1128 <&audma0 0x6f>, <&audma1 0x70>; 1129 dma-names = "rx", "tx", "rxu", "txu"; 1130 }; 1131 ssi4: ssi-4 { 1132 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1133 dmas = <&audma0 0x09>, <&audma1 0x0a>, 1134 <&audma0 0x71>, <&audma1 0x72>; 1135 dma-names = "rx", "tx", "rxu", "txu"; 1136 }; 1137 ssi5: ssi-5 { 1138 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1139 dmas = <&audma0 0x0b>, <&audma1 0x0c>, 1140 <&audma0 0x73>, <&audma1 0x74>; 1141 dma-names = "rx", "tx", "rxu", "txu"; 1142 }; 1143 ssi6: ssi-6 { 1144 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1145 dmas = <&audma0 0x0d>, <&audma1 0x0e>, 1146 <&audma0 0x75>, <&audma1 0x76>; 1147 dma-names = "rx", "tx", "rxu", "txu"; 1148 }; 1149 ssi7: ssi-7 { 1150 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1151 dmas = <&audma0 0x0f>, <&audma1 0x10>, 1152 <&audma0 0x79>, <&audma1 0x7a>; 1153 dma-names = "rx", "tx", "rxu", "txu"; 1154 }; 1155 ssi8: ssi-8 { 1156 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1157 dmas = <&audma0 0x11>, <&audma1 0x12>, 1158 <&audma0 0x7b>, <&audma1 0x7c>; 1159 dma-names = "rx", "tx", "rxu", "txu"; 1160 }; 1161 ssi9: ssi-9 { 1162 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1163 dmas = <&audma0 0x13>, <&audma1 0x14>, 1164 <&audma0 0x7d>, <&audma1 0x7e>; 1165 dma-names = "rx", "tx", "rxu", "txu"; 1166 }; 1167 }; 1168 }; 1169 1170 audma0: dma-controller@ec700000 { 1171 compatible = "renesas,dmac-r8a7793", 1172 "renesas,rcar-dmac"; 1173 reg = <0 0xec700000 0 0x10000>; 1174 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1188 interrupt-names = "error", 1189 "ch0", "ch1", "ch2", "ch3", 1190 "ch4", "ch5", "ch6", "ch7", 1191 "ch8", "ch9", "ch10", "ch11", 1192 "ch12"; 1193 clocks = <&cpg CPG_MOD 502>; 1194 clock-names = "fck"; 1195 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1196 resets = <&cpg 502>; 1197 #dma-cells = <1>; 1198 dma-channels = <13>; 1199 }; 1200 1201 audma1: dma-controller@ec720000 { 1202 compatible = "renesas,dmac-r8a7793", 1203 "renesas,rcar-dmac"; 1204 reg = <0 0xec720000 0 0x10000>; 1205 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1219 interrupt-names = "error", 1220 "ch0", "ch1", "ch2", "ch3", 1221 "ch4", "ch5", "ch6", "ch7", 1222 "ch8", "ch9", "ch10", "ch11", 1223 "ch12"; 1224 clocks = <&cpg CPG_MOD 501>; 1225 clock-names = "fck"; 1226 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1227 resets = <&cpg 501>; 1228 #dma-cells = <1>; 1229 dma-channels = <13>; 1230 }; 1231 1232 sdhi0: mmc@ee100000 { 1233 compatible = "renesas,sdhi-r8a7793", 1234 "renesas,rcar-gen2-sdhi"; 1235 reg = <0 0xee100000 0 0x328>; 1236 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1237 clocks = <&cpg CPG_MOD 314>; 1238 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 1239 <&dmac1 0xcd>, <&dmac1 0xce>; 1240 dma-names = "tx", "rx", "tx", "rx"; 1241 max-frequency = <195000000>; 1242 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1243 resets = <&cpg 314>; 1244 status = "disabled"; 1245 }; 1246 1247 sdhi1: mmc@ee140000 { 1248 compatible = "renesas,sdhi-r8a7793", 1249 "renesas,rcar-gen2-sdhi"; 1250 reg = <0 0xee140000 0 0x100>; 1251 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&cpg CPG_MOD 312>; 1253 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 1254 <&dmac1 0xc1>, <&dmac1 0xc2>; 1255 dma-names = "tx", "rx", "tx", "rx"; 1256 max-frequency = <97500000>; 1257 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1258 resets = <&cpg 312>; 1259 status = "disabled"; 1260 }; 1261 1262 sdhi2: mmc@ee160000 { 1263 compatible = "renesas,sdhi-r8a7793", 1264 "renesas,rcar-gen2-sdhi"; 1265 reg = <0 0xee160000 0 0x100>; 1266 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&cpg CPG_MOD 311>; 1268 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 1269 <&dmac1 0xd3>, <&dmac1 0xd4>; 1270 dma-names = "tx", "rx", "tx", "rx"; 1271 max-frequency = <97500000>; 1272 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1273 resets = <&cpg 311>; 1274 status = "disabled"; 1275 }; 1276 1277 mmcif0: mmc@ee200000 { 1278 compatible = "renesas,mmcif-r8a7793", 1279 "renesas,sh-mmcif"; 1280 reg = <0 0xee200000 0 0x80>; 1281 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&cpg CPG_MOD 315>; 1283 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 1284 <&dmac1 0xd1>, <&dmac1 0xd2>; 1285 dma-names = "tx", "rx", "tx", "rx"; 1286 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1287 resets = <&cpg 315>; 1288 reg-io-width = <4>; 1289 status = "disabled"; 1290 max-frequency = <97500000>; 1291 }; 1292 1293 ether: ethernet@ee700000 { 1294 compatible = "renesas,ether-r8a7793", 1295 "renesas,rcar-gen2-ether"; 1296 reg = <0 0xee700000 0 0x400>; 1297 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1298 clocks = <&cpg CPG_MOD 813>; 1299 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1300 resets = <&cpg 813>; 1301 phy-mode = "rmii"; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 status = "disabled"; 1305 }; 1306 1307 gic: interrupt-controller@f1001000 { 1308 compatible = "arm,gic-400"; 1309 #interrupt-cells = <3>; 1310 #address-cells = <0>; 1311 interrupt-controller; 1312 reg = <0 0xf1001000 0 0x1000>, 1313 <0 0xf1002000 0 0x2000>, 1314 <0 0xf1004000 0 0x2000>, 1315 <0 0xf1006000 0 0x2000>; 1316 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1317 clocks = <&cpg CPG_MOD 408>; 1318 clock-names = "clk"; 1319 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1320 resets = <&cpg 408>; 1321 }; 1322 1323 fdp1@fe940000 { 1324 compatible = "renesas,fdp1"; 1325 reg = <0 0xfe940000 0 0x2400>; 1326 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1327 clocks = <&cpg CPG_MOD 119>; 1328 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1329 resets = <&cpg 119>; 1330 }; 1331 1332 fdp1@fe944000 { 1333 compatible = "renesas,fdp1"; 1334 reg = <0 0xfe944000 0 0x2400>; 1335 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1336 clocks = <&cpg CPG_MOD 118>; 1337 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1338 resets = <&cpg 118>; 1339 }; 1340 1341 du: display@feb00000 { 1342 compatible = "renesas,du-r8a7793"; 1343 reg = <0 0xfeb00000 0 0x40000>; 1344 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1346 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1347 clock-names = "du.0", "du.1"; 1348 resets = <&cpg 724>; 1349 reset-names = "du.0"; 1350 status = "disabled"; 1351 1352 ports { 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 1356 port@0 { 1357 reg = <0>; 1358 du_out_rgb: endpoint { 1359 }; 1360 }; 1361 port@1 { 1362 reg = <1>; 1363 du_out_lvds0: endpoint { 1364 remote-endpoint = <&lvds0_in>; 1365 }; 1366 }; 1367 }; 1368 }; 1369 1370 lvds0: lvds@feb90000 { 1371 compatible = "renesas,r8a7793-lvds"; 1372 reg = <0 0xfeb90000 0 0x1c>; 1373 clocks = <&cpg CPG_MOD 726>; 1374 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1375 resets = <&cpg 726>; 1376 1377 status = "disabled"; 1378 1379 ports { 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 1383 port@0 { 1384 reg = <0>; 1385 lvds0_in: endpoint { 1386 remote-endpoint = <&du_out_lvds0>; 1387 }; 1388 }; 1389 port@1 { 1390 reg = <1>; 1391 lvds0_out: endpoint { 1392 }; 1393 }; 1394 }; 1395 }; 1396 1397 prr: chipid@ff000044 { 1398 compatible = "renesas,prr"; 1399 reg = <0 0xff000044 0 4>; 1400 }; 1401 1402 cmt0: timer@ffca0000 { 1403 compatible = "renesas,r8a7793-cmt0", 1404 "renesas,rcar-gen2-cmt0"; 1405 reg = <0 0xffca0000 0 0x1004>; 1406 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1408 clocks = <&cpg CPG_MOD 124>; 1409 clock-names = "fck"; 1410 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1411 resets = <&cpg 124>; 1412 1413 status = "disabled"; 1414 }; 1415 1416 cmt1: timer@e6130000 { 1417 compatible = "renesas,r8a7793-cmt1", 1418 "renesas,rcar-gen2-cmt1"; 1419 reg = <0 0xe6130000 0 0x1004>; 1420 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1428 clocks = <&cpg CPG_MOD 329>; 1429 clock-names = "fck"; 1430 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1431 resets = <&cpg 329>; 1432 1433 status = "disabled"; 1434 }; 1435 }; 1436 1437 thermal-zones { 1438 cpu_thermal: cpu-thermal { 1439 polling-delay-passive = <0>; 1440 polling-delay = <0>; 1441 1442 thermal-sensors = <&thermal>; 1443 1444 trips { 1445 cpu-crit { 1446 temperature = <95000>; 1447 hysteresis = <0>; 1448 type = "critical"; 1449 }; 1450 }; 1451 cooling-maps { 1452 }; 1453 }; 1454 }; 1455 1456 timer { 1457 compatible = "arm,armv7-timer"; 1458 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1459 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1460 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1461 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1462 }; 1463 1464 /* External USB clock - can be overridden by the board */ 1465 usb_extal_clk: usb_extal { 1466 compatible = "fixed-clock"; 1467 #clock-cells = <0>; 1468 clock-frequency = <48000000>; 1469 }; 1470}; 1471