1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V2H (R8A77920) SoC 4 * 5 * Copyright (C) 2016 Cogent Embedded Inc. 6 */ 7 8#include <dt-bindings/clock/r8a7792-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a7792-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7792"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &iic3; 26 spi0 = &qspi; 27 spi1 = &msiof0; 28 spi2 = &msiof1; 29 vin0 = &vin0; 30 vin1 = &vin1; 31 vin2 = &vin2; 32 vin3 = &vin3; 33 vin4 = &vin4; 34 vin5 = &vin5; 35 }; 36 37 /* External CAN clock */ 38 can_clk: can { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board. */ 42 clock-frequency = <0>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a15"; 52 reg = <0>; 53 clock-frequency = <1000000000>; 54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 55 power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 56 enable-method = "renesas,apmu"; 57 next-level-cache = <&L2_CA15>; 58 }; 59 60 cpu1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a15"; 63 reg = <1>; 64 clock-frequency = <1000000000>; 65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 66 power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 67 enable-method = "renesas,apmu"; 68 next-level-cache = <&L2_CA15>; 69 }; 70 71 L2_CA15: cache-controller-0 { 72 compatible = "cache"; 73 cache-unified; 74 cache-level = <2>; 75 power-domains = <&sysc R8A7792_PD_CA15_SCU>; 76 }; 77 }; 78 79 /* External root clock */ 80 extal_clk: extal { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 /* This value must be overridden by the board. */ 84 clock-frequency = <0>; 85 }; 86 87 lbsc: lbsc { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges = <0 0 0 0x1c000000>; 92 }; 93 94 pmu { 95 compatible = "arm,cortex-a15-pmu"; 96 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 97 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 98 interrupt-affinity = <&cpu0>, <&cpu1>; 99 }; 100 101 /* External SCIF clock */ 102 scif_clk: scif { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 /* This value must be overridden by the board. */ 106 clock-frequency = <0>; 107 }; 108 109 soc { 110 compatible = "simple-bus"; 111 interrupt-parent = <&gic>; 112 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 117 rwdt: watchdog@e6020000 { 118 compatible = "renesas,r8a7792-wdt", 119 "renesas,rcar-gen2-wdt"; 120 reg = <0 0xe6020000 0 0x0c>; 121 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&cpg CPG_MOD 402>; 123 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 124 resets = <&cpg 402>; 125 status = "disabled"; 126 }; 127 128 gpio0: gpio@e6050000 { 129 compatible = "renesas,gpio-r8a7792", 130 "renesas,rcar-gen2-gpio"; 131 reg = <0 0xe6050000 0 0x50>; 132 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 133 #gpio-cells = <2>; 134 gpio-controller; 135 gpio-ranges = <&pfc 0 0 29>; 136 #interrupt-cells = <2>; 137 interrupt-controller; 138 clocks = <&cpg CPG_MOD 912>; 139 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 140 resets = <&cpg 912>; 141 }; 142 143 gpio1: gpio@e6051000 { 144 compatible = "renesas,gpio-r8a7792", 145 "renesas,rcar-gen2-gpio"; 146 reg = <0 0xe6051000 0 0x50>; 147 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 148 #gpio-cells = <2>; 149 gpio-controller; 150 gpio-ranges = <&pfc 0 32 23>; 151 #interrupt-cells = <2>; 152 interrupt-controller; 153 clocks = <&cpg CPG_MOD 911>; 154 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 155 resets = <&cpg 911>; 156 }; 157 158 gpio2: gpio@e6052000 { 159 compatible = "renesas,gpio-r8a7792", 160 "renesas,rcar-gen2-gpio"; 161 reg = <0 0xe6052000 0 0x50>; 162 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 163 #gpio-cells = <2>; 164 gpio-controller; 165 gpio-ranges = <&pfc 0 64 32>; 166 #interrupt-cells = <2>; 167 interrupt-controller; 168 clocks = <&cpg CPG_MOD 910>; 169 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 170 resets = <&cpg 910>; 171 }; 172 173 gpio3: gpio@e6053000 { 174 compatible = "renesas,gpio-r8a7792", 175 "renesas,rcar-gen2-gpio"; 176 reg = <0 0xe6053000 0 0x50>; 177 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 178 #gpio-cells = <2>; 179 gpio-controller; 180 gpio-ranges = <&pfc 0 96 28>; 181 #interrupt-cells = <2>; 182 interrupt-controller; 183 clocks = <&cpg CPG_MOD 909>; 184 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 185 resets = <&cpg 909>; 186 }; 187 188 gpio4: gpio@e6054000 { 189 compatible = "renesas,gpio-r8a7792", 190 "renesas,rcar-gen2-gpio"; 191 reg = <0 0xe6054000 0 0x50>; 192 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 193 #gpio-cells = <2>; 194 gpio-controller; 195 gpio-ranges = <&pfc 0 128 17>; 196 #interrupt-cells = <2>; 197 interrupt-controller; 198 clocks = <&cpg CPG_MOD 908>; 199 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 200 resets = <&cpg 908>; 201 }; 202 203 gpio5: gpio@e6055000 { 204 compatible = "renesas,gpio-r8a7792", 205 "renesas,rcar-gen2-gpio"; 206 reg = <0 0xe6055000 0 0x50>; 207 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 208 #gpio-cells = <2>; 209 gpio-controller; 210 gpio-ranges = <&pfc 0 160 17>; 211 #interrupt-cells = <2>; 212 interrupt-controller; 213 clocks = <&cpg CPG_MOD 907>; 214 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 215 resets = <&cpg 907>; 216 }; 217 218 gpio6: gpio@e6055100 { 219 compatible = "renesas,gpio-r8a7792", 220 "renesas,rcar-gen2-gpio"; 221 reg = <0 0xe6055100 0 0x50>; 222 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 223 #gpio-cells = <2>; 224 gpio-controller; 225 gpio-ranges = <&pfc 0 192 17>; 226 #interrupt-cells = <2>; 227 interrupt-controller; 228 clocks = <&cpg CPG_MOD 905>; 229 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 230 resets = <&cpg 905>; 231 }; 232 233 gpio7: gpio@e6055200 { 234 compatible = "renesas,gpio-r8a7792", 235 "renesas,rcar-gen2-gpio"; 236 reg = <0 0xe6055200 0 0x50>; 237 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 238 #gpio-cells = <2>; 239 gpio-controller; 240 gpio-ranges = <&pfc 0 224 17>; 241 #interrupt-cells = <2>; 242 interrupt-controller; 243 clocks = <&cpg CPG_MOD 904>; 244 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 245 resets = <&cpg 904>; 246 }; 247 248 gpio8: gpio@e6055300 { 249 compatible = "renesas,gpio-r8a7792", 250 "renesas,rcar-gen2-gpio"; 251 reg = <0 0xe6055300 0 0x50>; 252 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 253 #gpio-cells = <2>; 254 gpio-controller; 255 gpio-ranges = <&pfc 0 256 17>; 256 #interrupt-cells = <2>; 257 interrupt-controller; 258 clocks = <&cpg CPG_MOD 921>; 259 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 260 resets = <&cpg 921>; 261 }; 262 263 gpio9: gpio@e6055400 { 264 compatible = "renesas,gpio-r8a7792", 265 "renesas,rcar-gen2-gpio"; 266 reg = <0 0xe6055400 0 0x50>; 267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 268 #gpio-cells = <2>; 269 gpio-controller; 270 gpio-ranges = <&pfc 0 288 17>; 271 #interrupt-cells = <2>; 272 interrupt-controller; 273 clocks = <&cpg CPG_MOD 919>; 274 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 275 resets = <&cpg 919>; 276 }; 277 278 gpio10: gpio@e6055500 { 279 compatible = "renesas,gpio-r8a7792", 280 "renesas,rcar-gen2-gpio"; 281 reg = <0 0xe6055500 0 0x50>; 282 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 283 #gpio-cells = <2>; 284 gpio-controller; 285 gpio-ranges = <&pfc 0 320 32>; 286 #interrupt-cells = <2>; 287 interrupt-controller; 288 clocks = <&cpg CPG_MOD 914>; 289 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 290 resets = <&cpg 914>; 291 }; 292 293 gpio11: gpio@e6055600 { 294 compatible = "renesas,gpio-r8a7792", 295 "renesas,rcar-gen2-gpio"; 296 reg = <0 0xe6055600 0 0x50>; 297 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 298 #gpio-cells = <2>; 299 gpio-controller; 300 gpio-ranges = <&pfc 0 352 30>; 301 #interrupt-cells = <2>; 302 interrupt-controller; 303 clocks = <&cpg CPG_MOD 913>; 304 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 305 resets = <&cpg 913>; 306 }; 307 308 pfc: pinctrl@e6060000 { 309 compatible = "renesas,pfc-r8a7792"; 310 reg = <0 0xe6060000 0 0x144>; 311 }; 312 313 cpg: clock-controller@e6150000 { 314 compatible = "renesas,r8a7792-cpg-mssr"; 315 reg = <0 0xe6150000 0 0x1000>; 316 clocks = <&extal_clk>; 317 clock-names = "extal"; 318 #clock-cells = <2>; 319 #power-domain-cells = <0>; 320 #reset-cells = <1>; 321 }; 322 323 apmu@e6152000 { 324 compatible = "renesas,r8a7792-apmu", "renesas,apmu"; 325 reg = <0 0xe6152000 0 0x188>; 326 cpus = <&cpu0>, <&cpu1>; 327 }; 328 329 rst: reset-controller@e6160000 { 330 compatible = "renesas,r8a7792-rst"; 331 reg = <0 0xe6160000 0 0x0100>; 332 }; 333 334 sysc: system-controller@e6180000 { 335 compatible = "renesas,r8a7792-sysc"; 336 reg = <0 0xe6180000 0 0x0200>; 337 #power-domain-cells = <1>; 338 }; 339 340 irqc: interrupt-controller@e61c0000 { 341 compatible = "renesas,irqc-r8a7792", "renesas,irqc"; 342 #interrupt-cells = <2>; 343 interrupt-controller; 344 reg = <0 0xe61c0000 0 0x200>; 345 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&cpg CPG_MOD 407>; 350 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 351 resets = <&cpg 407>; 352 }; 353 354 icram0: sram@e63a0000 { 355 compatible = "mmio-sram"; 356 reg = <0 0xe63a0000 0 0x12000>; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges = <0 0 0xe63a0000 0x12000>; 360 }; 361 362 icram1: sram@e63c0000 { 363 compatible = "mmio-sram"; 364 reg = <0 0xe63c0000 0 0x1000>; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 ranges = <0 0 0xe63c0000 0x1000>; 368 369 smp-sram@0 { 370 compatible = "renesas,smp-sram"; 371 reg = <0 0x100>; 372 }; 373 }; 374 375 /* I2C doesn't need pinmux */ 376 i2c0: i2c@e6508000 { 377 compatible = "renesas,i2c-r8a7792", 378 "renesas,rcar-gen2-i2c"; 379 reg = <0 0xe6508000 0 0x40>; 380 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&cpg CPG_MOD 931>; 382 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 383 resets = <&cpg 931>; 384 i2c-scl-internal-delay-ns = <6>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 status = "disabled"; 388 }; 389 390 i2c1: i2c@e6518000 { 391 compatible = "renesas,i2c-r8a7792", 392 "renesas,rcar-gen2-i2c"; 393 reg = <0 0xe6518000 0 0x40>; 394 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&cpg CPG_MOD 930>; 396 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 397 resets = <&cpg 930>; 398 i2c-scl-internal-delay-ns = <6>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 status = "disabled"; 402 }; 403 404 i2c2: i2c@e6530000 { 405 compatible = "renesas,i2c-r8a7792", 406 "renesas,rcar-gen2-i2c"; 407 reg = <0 0xe6530000 0 0x40>; 408 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cpg CPG_MOD 929>; 410 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 411 resets = <&cpg 929>; 412 i2c-scl-internal-delay-ns = <6>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 status = "disabled"; 416 }; 417 418 i2c3: i2c@e6540000 { 419 compatible = "renesas,i2c-r8a7792", 420 "renesas,rcar-gen2-i2c"; 421 reg = <0 0xe6540000 0 0x40>; 422 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&cpg CPG_MOD 928>; 424 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 425 resets = <&cpg 928>; 426 i2c-scl-internal-delay-ns = <6>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 432 i2c4: i2c@e6520000 { 433 compatible = "renesas,i2c-r8a7792", 434 "renesas,rcar-gen2-i2c"; 435 reg = <0 0xe6520000 0 0x40>; 436 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cpg CPG_MOD 927>; 438 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 439 resets = <&cpg 927>; 440 i2c-scl-internal-delay-ns = <6>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 status = "disabled"; 444 }; 445 446 i2c5: i2c@e6528000 { 447 compatible = "renesas,i2c-r8a7792", 448 "renesas,rcar-gen2-i2c"; 449 reg = <0 0xe6528000 0 0x40>; 450 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cpg CPG_MOD 925>; 452 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 453 resets = <&cpg 925>; 454 i2c-scl-internal-delay-ns = <110>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 status = "disabled"; 458 }; 459 460 iic3: i2c@e60b0000 { 461 #address-cells = <1>; 462 #size-cells = <0>; 463 compatible = "renesas,iic-r8a7792", 464 "renesas,rcar-gen2-iic", 465 "renesas,rmobile-iic"; 466 reg = <0 0xe60b0000 0 0x425>; 467 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&cpg CPG_MOD 926>; 469 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 470 <&dmac1 0x77>, <&dmac1 0x78>; 471 dma-names = "tx", "rx", "tx", "rx"; 472 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 473 resets = <&cpg 926>; 474 status = "disabled"; 475 }; 476 477 dmac0: dma-controller@e6700000 { 478 compatible = "renesas,dmac-r8a7792", 479 "renesas,rcar-dmac"; 480 reg = <0 0xe6700000 0 0x20000>; 481 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 497 interrupt-names = "error", 498 "ch0", "ch1", "ch2", "ch3", 499 "ch4", "ch5", "ch6", "ch7", 500 "ch8", "ch9", "ch10", "ch11", 501 "ch12", "ch13", "ch14"; 502 clocks = <&cpg CPG_MOD 219>; 503 clock-names = "fck"; 504 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 505 resets = <&cpg 219>; 506 #dma-cells = <1>; 507 dma-channels = <15>; 508 }; 509 510 dmac1: dma-controller@e6720000 { 511 compatible = "renesas,dmac-r8a7792", 512 "renesas,rcar-dmac"; 513 reg = <0 0xe6720000 0 0x20000>; 514 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-names = "error", 531 "ch0", "ch1", "ch2", "ch3", 532 "ch4", "ch5", "ch6", "ch7", 533 "ch8", "ch9", "ch10", "ch11", 534 "ch12", "ch13", "ch14"; 535 clocks = <&cpg CPG_MOD 218>; 536 clock-names = "fck"; 537 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 538 resets = <&cpg 218>; 539 #dma-cells = <1>; 540 dma-channels = <15>; 541 }; 542 543 avb: ethernet@e6800000 { 544 compatible = "renesas,etheravb-r8a7792", 545 "renesas,etheravb-rcar-gen2"; 546 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 547 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cpg CPG_MOD 812>; 549 clock-names = "fck"; 550 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 551 resets = <&cpg 812>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 status = "disabled"; 555 }; 556 557 qspi: spi@e6b10000 { 558 compatible = "renesas,qspi-r8a7792", "renesas,qspi"; 559 reg = <0 0xe6b10000 0 0x2c>; 560 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&cpg CPG_MOD 917>; 562 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 563 <&dmac1 0x17>, <&dmac1 0x18>; 564 dma-names = "tx", "rx", "tx", "rx"; 565 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 566 resets = <&cpg 917>; 567 num-cs = <1>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 scif0: serial@e6e60000 { 574 compatible = "renesas,scif-r8a7792", 575 "renesas,rcar-gen2-scif", "renesas,scif"; 576 reg = <0 0xe6e60000 0 64>; 577 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cpg CPG_MOD 721>, 579 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 580 clock-names = "fck", "brg_int", "scif_clk"; 581 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 582 <&dmac1 0x29>, <&dmac1 0x2a>; 583 dma-names = "tx", "rx", "tx", "rx"; 584 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 585 resets = <&cpg 721>; 586 status = "disabled"; 587 }; 588 589 scif1: serial@e6e68000 { 590 compatible = "renesas,scif-r8a7792", 591 "renesas,rcar-gen2-scif", "renesas,scif"; 592 reg = <0 0xe6e68000 0 64>; 593 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cpg CPG_MOD 720>, 595 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 596 clock-names = "fck", "brg_int", "scif_clk"; 597 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 598 <&dmac1 0x2d>, <&dmac1 0x2e>; 599 dma-names = "tx", "rx", "tx", "rx"; 600 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 601 resets = <&cpg 720>; 602 status = "disabled"; 603 }; 604 605 scif2: serial@e6e58000 { 606 compatible = "renesas,scif-r8a7792", 607 "renesas,rcar-gen2-scif", "renesas,scif"; 608 reg = <0 0xe6e58000 0 64>; 609 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&cpg CPG_MOD 719>, 611 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 612 clock-names = "fck", "brg_int", "scif_clk"; 613 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 614 <&dmac1 0x2b>, <&dmac1 0x2c>; 615 dma-names = "tx", "rx", "tx", "rx"; 616 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 617 resets = <&cpg 719>; 618 status = "disabled"; 619 }; 620 621 scif3: serial@e6ea8000 { 622 compatible = "renesas,scif-r8a7792", 623 "renesas,rcar-gen2-scif", "renesas,scif"; 624 reg = <0 0xe6ea8000 0 64>; 625 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cpg CPG_MOD 718>, 627 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 628 clock-names = "fck", "brg_int", "scif_clk"; 629 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 630 <&dmac1 0x2f>, <&dmac1 0x30>; 631 dma-names = "tx", "rx", "tx", "rx"; 632 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 633 resets = <&cpg 718>; 634 status = "disabled"; 635 }; 636 637 hscif0: serial@e62c0000 { 638 compatible = "renesas,hscif-r8a7792", 639 "renesas,rcar-gen2-hscif", "renesas,hscif"; 640 reg = <0 0xe62c0000 0 96>; 641 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cpg CPG_MOD 717>, 643 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 644 clock-names = "fck", "brg_int", "scif_clk"; 645 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 646 <&dmac1 0x39>, <&dmac1 0x3a>; 647 dma-names = "tx", "rx", "tx", "rx"; 648 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 649 resets = <&cpg 717>; 650 status = "disabled"; 651 }; 652 653 hscif1: serial@e62c8000 { 654 compatible = "renesas,hscif-r8a7792", 655 "renesas,rcar-gen2-hscif", "renesas,hscif"; 656 reg = <0 0xe62c8000 0 96>; 657 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cpg CPG_MOD 716>, 659 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 660 clock-names = "fck", "brg_int", "scif_clk"; 661 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 662 <&dmac1 0x4d>, <&dmac1 0x4e>; 663 dma-names = "tx", "rx", "tx", "rx"; 664 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 665 resets = <&cpg 716>; 666 status = "disabled"; 667 }; 668 669 msiof0: spi@e6e20000 { 670 compatible = "renesas,msiof-r8a7792", 671 "renesas,rcar-gen2-msiof"; 672 reg = <0 0xe6e20000 0 0x0064>; 673 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cpg CPG_MOD 000>; 675 dmas = <&dmac0 0x51>, <&dmac0 0x52>, 676 <&dmac1 0x51>, <&dmac1 0x52>; 677 dma-names = "tx", "rx", "tx", "rx"; 678 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 679 resets = <&cpg 000>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 status = "disabled"; 683 }; 684 685 msiof1: spi@e6e10000 { 686 compatible = "renesas,msiof-r8a7792", 687 "renesas,rcar-gen2-msiof"; 688 reg = <0 0xe6e10000 0 0x0064>; 689 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&cpg CPG_MOD 208>; 691 dmas = <&dmac0 0x55>, <&dmac0 0x56>, 692 <&dmac1 0x55>, <&dmac1 0x56>; 693 dma-names = "tx", "rx", "tx", "rx"; 694 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 695 resets = <&cpg 208>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 status = "disabled"; 699 }; 700 701 can0: can@e6e80000 { 702 compatible = "renesas,can-r8a7792", 703 "renesas,rcar-gen2-can"; 704 reg = <0 0xe6e80000 0 0x1000>; 705 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cpg CPG_MOD 916>, 707 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 708 clock-names = "clkp1", "clkp2", "can_clk"; 709 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 710 resets = <&cpg 916>; 711 status = "disabled"; 712 }; 713 714 can1: can@e6e88000 { 715 compatible = "renesas,can-r8a7792", 716 "renesas,rcar-gen2-can"; 717 reg = <0 0xe6e88000 0 0x1000>; 718 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cpg CPG_MOD 915>, 720 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 721 clock-names = "clkp1", "clkp2", "can_clk"; 722 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 723 resets = <&cpg 915>; 724 status = "disabled"; 725 }; 726 727 vin0: video@e6ef0000 { 728 compatible = "renesas,vin-r8a7792", 729 "renesas,rcar-gen2-vin"; 730 reg = <0 0xe6ef0000 0 0x1000>; 731 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&cpg CPG_MOD 811>; 733 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 734 resets = <&cpg 811>; 735 status = "disabled"; 736 }; 737 738 vin1: video@e6ef1000 { 739 compatible = "renesas,vin-r8a7792", 740 "renesas,rcar-gen2-vin"; 741 reg = <0 0xe6ef1000 0 0x1000>; 742 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&cpg CPG_MOD 810>; 744 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 745 resets = <&cpg 810>; 746 status = "disabled"; 747 }; 748 749 vin2: video@e6ef2000 { 750 compatible = "renesas,vin-r8a7792", 751 "renesas,rcar-gen2-vin"; 752 reg = <0 0xe6ef2000 0 0x1000>; 753 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cpg CPG_MOD 809>; 755 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 756 resets = <&cpg 809>; 757 status = "disabled"; 758 }; 759 760 vin3: video@e6ef3000 { 761 compatible = "renesas,vin-r8a7792", 762 "renesas,rcar-gen2-vin"; 763 reg = <0 0xe6ef3000 0 0x1000>; 764 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&cpg CPG_MOD 808>; 766 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 767 resets = <&cpg 808>; 768 status = "disabled"; 769 }; 770 771 vin4: video@e6ef4000 { 772 compatible = "renesas,vin-r8a7792", 773 "renesas,rcar-gen2-vin"; 774 reg = <0 0xe6ef4000 0 0x1000>; 775 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&cpg CPG_MOD 805>; 777 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 778 resets = <&cpg 805>; 779 status = "disabled"; 780 }; 781 782 vin5: video@e6ef5000 { 783 compatible = "renesas,vin-r8a7792", 784 "renesas,rcar-gen2-vin"; 785 reg = <0 0xe6ef5000 0 0x1000>; 786 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&cpg CPG_MOD 804>; 788 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 789 resets = <&cpg 804>; 790 status = "disabled"; 791 }; 792 793 sdhi0: mmc@ee100000 { 794 compatible = "renesas,sdhi-r8a7792", 795 "renesas,rcar-gen2-sdhi"; 796 reg = <0 0xee100000 0 0x328>; 797 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 798 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 799 <&dmac1 0xcd>, <&dmac1 0xce>; 800 dma-names = "tx", "rx", "tx", "rx"; 801 clocks = <&cpg CPG_MOD 314>; 802 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 803 resets = <&cpg 314>; 804 status = "disabled"; 805 }; 806 807 gic: interrupt-controller@f1001000 { 808 compatible = "arm,gic-400"; 809 #interrupt-cells = <3>; 810 interrupt-controller; 811 reg = <0 0xf1001000 0 0x1000>, 812 <0 0xf1002000 0 0x2000>, 813 <0 0xf1004000 0 0x2000>, 814 <0 0xf1006000 0 0x2000>; 815 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 816 IRQ_TYPE_LEVEL_HIGH)>; 817 clocks = <&cpg CPG_MOD 408>; 818 clock-names = "clk"; 819 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 820 resets = <&cpg 408>; 821 }; 822 823 vsp@fe928000 { 824 compatible = "renesas,vsp1"; 825 reg = <0 0xfe928000 0 0x8000>; 826 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&cpg CPG_MOD 131>; 828 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 829 resets = <&cpg 131>; 830 }; 831 832 vsp@fe930000 { 833 compatible = "renesas,vsp1"; 834 reg = <0 0xfe930000 0 0x8000>; 835 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&cpg CPG_MOD 128>; 837 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 838 resets = <&cpg 128>; 839 }; 840 841 vsp@fe938000 { 842 compatible = "renesas,vsp1"; 843 reg = <0 0xfe938000 0 0x8000>; 844 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&cpg CPG_MOD 127>; 846 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 847 resets = <&cpg 127>; 848 }; 849 850 jpu: jpeg-codec@fe980000 { 851 compatible = "renesas,jpu-r8a7792", 852 "renesas,rcar-gen2-jpu"; 853 reg = <0 0xfe980000 0 0x10300>; 854 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cpg CPG_MOD 106>; 856 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 857 resets = <&cpg 106>; 858 }; 859 860 du: display@feb00000 { 861 compatible = "renesas,du-r8a7792"; 862 reg = <0 0xfeb00000 0 0x40000>; 863 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 866 clock-names = "du.0", "du.1"; 867 resets = <&cpg 724>; 868 reset-names = "du.0"; 869 status = "disabled"; 870 871 ports { 872 #address-cells = <1>; 873 #size-cells = <0>; 874 875 port@0 { 876 reg = <0>; 877 du_out_rgb0: endpoint { 878 }; 879 }; 880 port@1 { 881 reg = <1>; 882 du_out_rgb1: endpoint { 883 }; 884 }; 885 }; 886 }; 887 888 prr: chipid@ff000044 { 889 compatible = "renesas,prr"; 890 reg = <0 0xff000044 0 4>; 891 }; 892 893 cmt0: timer@ffca0000 { 894 compatible = "renesas,r8a7792-cmt0", 895 "renesas,rcar-gen2-cmt0"; 896 reg = <0 0xffca0000 0 0x1004>; 897 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&cpg CPG_MOD 124>; 900 clock-names = "fck"; 901 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 902 resets = <&cpg 124>; 903 904 status = "disabled"; 905 }; 906 907 cmt1: timer@e6130000 { 908 compatible = "renesas,r8a7792-cmt1", 909 "renesas,rcar-gen2-cmt1"; 910 reg = <0 0xe6130000 0 0x1004>; 911 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&cpg CPG_MOD 329>; 920 clock-names = "fck"; 921 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 922 resets = <&cpg 329>; 923 924 status = "disabled"; 925 }; 926 }; 927 928 timer { 929 compatible = "arm,armv7-timer"; 930 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 931 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 932 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 933 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 934 }; 935}; 936