1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a73a4 SoC 4 * 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Magnus Damm 7 */ 8 9#include <dt-bindings/clock/r8a73a4-clock.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12 13/ { 14 compatible = "renesas,r8a73a4"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a15"; 26 reg = <0>; 27 clocks = <&cpg_clocks R8A73A4_CLK_Z>; 28 clock-frequency = <1500000000>; 29 power-domains = <&pd_a2sl>; 30 next-level-cache = <&L2_CA15>; 31 }; 32 33 L2_CA15: cache-controller-0 { 34 compatible = "cache"; 35 clocks = <&cpg_clocks R8A73A4_CLK_Z>; 36 power-domains = <&pd_a3sm>; 37 cache-unified; 38 cache-level = <2>; 39 }; 40 41 L2_CA7: cache-controller-1 { 42 compatible = "cache"; 43 clocks = <&cpg_clocks R8A73A4_CLK_Z2>; 44 power-domains = <&pd_a3km>; 45 cache-unified; 46 cache-level = <2>; 47 }; 48 }; 49 50 ptm { 51 compatible = "arm,coresight-etm3x"; 52 power-domains = <&pd_d4>; 53 }; 54 55 timer { 56 compatible = "arm,armv7-timer"; 57 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 58 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 59 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 60 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 61 }; 62 63 tmu0: timer@e61e0000 { 64 compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; 65 reg = <0 0xe61e0000 0 0x30>; 66 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-names = "tuni0", "tuni1", "tuni2"; 70 clocks = <&mstp1_clks R8A73A4_CLK_TMU0>; 71 clock-names = "fck"; 72 power-domains = <&pd_c5>; 73 status = "disabled"; 74 }; 75 76 tmu3: timer@fff80000 { 77 compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; 78 reg = <0 0xfff80000 0 0x30>; 79 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 82 interrupt-names = "tuni0", "tuni1", "tuni2"; 83 clocks = <&mstp1_clks R8A73A4_CLK_TMU3>; 84 clock-names = "fck"; 85 power-domains = <&pd_a3r>; 86 status = "disabled"; 87 }; 88 89 dbsc1: memory-controller@e6790000 { 90 compatible = "renesas,dbsc-r8a73a4"; 91 reg = <0 0xe6790000 0 0x10000>; 92 power-domains = <&pd_a3bc>; 93 }; 94 95 dbsc2: memory-controller@e67a0000 { 96 compatible = "renesas,dbsc-r8a73a4"; 97 reg = <0 0xe67a0000 0 0x10000>; 98 power-domains = <&pd_a3bc>; 99 }; 100 101 i2c5: i2c@e60b0000 { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 105 reg = <0 0xe60b0000 0 0x428>; 106 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; 108 power-domains = <&pd_a3sp>; 109 110 status = "disabled"; 111 }; 112 113 cmt1: timer@e6130000 { 114 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; 115 reg = <0 0xe6130000 0 0x1004>; 116 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; 125 clock-names = "fck"; 126 power-domains = <&pd_c5>; 127 status = "disabled"; 128 }; 129 130 irqc0: interrupt-controller@e61c0000 { 131 compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 132 #interrupt-cells = <2>; 133 interrupt-controller; 134 reg = <0 0xe61c0000 0 0x200>; 135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 168 power-domains = <&pd_c4>; 169 }; 170 171 irqc1: interrupt-controller@e61c0200 { 172 compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 173 #interrupt-cells = <2>; 174 interrupt-controller; 175 reg = <0 0xe61c0200 0 0x200>; 176 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 203 power-domains = <&pd_c4>; 204 }; 205 206 pfc: pinctrl@e6050000 { 207 compatible = "renesas,pfc-r8a73a4"; 208 reg = <0 0xe6050000 0 0x9000>; 209 gpio-controller; 210 #gpio-cells = <2>; 211 gpio-ranges = 212 <&pfc 0 0 31>, <&pfc 32 32 9>, 213 <&pfc 64 64 22>, <&pfc 96 96 31>, 214 <&pfc 128 128 7>, <&pfc 160 160 19>, 215 <&pfc 192 192 31>, <&pfc 224 224 27>, 216 <&pfc 256 256 28>, <&pfc 288 288 21>, 217 <&pfc 320 320 10>; 218 interrupts-extended = 219 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, 220 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, 221 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, 222 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, 223 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, 224 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, 225 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, 226 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, 227 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, 228 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, 229 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, 230 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, 231 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, 232 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, 233 <&irqc1 24 0>, <&irqc1 25 0>; 234 power-domains = <&pd_c5>; 235 }; 236 237 thermal@e61f0000 { 238 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; 239 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 240 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 241 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; 243 power-domains = <&pd_c5>; 244 }; 245 246 i2c0: i2c@e6500000 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 250 reg = <0 0xe6500000 0 0x428>; 251 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; 253 power-domains = <&pd_a3sp>; 254 status = "disabled"; 255 }; 256 257 i2c1: i2c@e6510000 { 258 #address-cells = <1>; 259 #size-cells = <0>; 260 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 261 reg = <0 0xe6510000 0 0x428>; 262 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; 264 power-domains = <&pd_a3sp>; 265 status = "disabled"; 266 }; 267 268 i2c2: i2c@e6520000 { 269 #address-cells = <1>; 270 #size-cells = <0>; 271 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 272 reg = <0 0xe6520000 0 0x428>; 273 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; 275 power-domains = <&pd_a3sp>; 276 status = "disabled"; 277 }; 278 279 i2c3: i2c@e6530000 { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 283 reg = <0 0xe6530000 0 0x428>; 284 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; 286 power-domains = <&pd_a3sp>; 287 status = "disabled"; 288 }; 289 290 i2c4: i2c@e6540000 { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 294 reg = <0 0xe6540000 0 0x428>; 295 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; 297 power-domains = <&pd_a3sp>; 298 status = "disabled"; 299 }; 300 301 i2c6: i2c@e6550000 { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 305 reg = <0 0xe6550000 0 0x428>; 306 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; 308 power-domains = <&pd_a3sp>; 309 status = "disabled"; 310 }; 311 312 i2c7: i2c@e6560000 { 313 #address-cells = <1>; 314 #size-cells = <0>; 315 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 316 reg = <0 0xe6560000 0 0x428>; 317 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; 319 power-domains = <&pd_a3sp>; 320 status = "disabled"; 321 }; 322 323 i2c8: i2c@e6570000 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 327 reg = <0 0xe6570000 0 0x428>; 328 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; 330 power-domains = <&pd_a3sp>; 331 status = "disabled"; 332 }; 333 334 scifb0: serial@e6c20000 { 335 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 336 reg = <0 0xe6c20000 0 0x100>; 337 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; 339 clock-names = "fck"; 340 power-domains = <&pd_a3sp>; 341 status = "disabled"; 342 }; 343 344 scifb1: serial@e6c30000 { 345 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 346 reg = <0 0xe6c30000 0 0x100>; 347 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; 349 clock-names = "fck"; 350 power-domains = <&pd_a3sp>; 351 status = "disabled"; 352 }; 353 354 scifa0: serial@e6c40000 { 355 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 356 reg = <0 0xe6c40000 0 0x100>; 357 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; 359 clock-names = "fck"; 360 power-domains = <&pd_a3sp>; 361 status = "disabled"; 362 }; 363 364 scifa1: serial@e6c50000 { 365 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 366 reg = <0 0xe6c50000 0 0x100>; 367 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; 369 clock-names = "fck"; 370 power-domains = <&pd_a3sp>; 371 status = "disabled"; 372 }; 373 374 scifb2: serial@e6ce0000 { 375 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 376 reg = <0 0xe6ce0000 0 0x100>; 377 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; 379 clock-names = "fck"; 380 power-domains = <&pd_a3sp>; 381 status = "disabled"; 382 }; 383 384 scifb3: serial@e6cf0000 { 385 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 386 reg = <0 0xe6cf0000 0 0x100>; 387 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; 389 clock-names = "fck"; 390 power-domains = <&pd_c4>; 391 status = "disabled"; 392 }; 393 394 sdhi0: mmc@ee100000 { 395 compatible = "renesas,sdhi-r8a73a4"; 396 reg = <0 0xee100000 0 0x100>; 397 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; 399 power-domains = <&pd_a3sp>; 400 cap-sd-highspeed; 401 status = "disabled"; 402 }; 403 404 sdhi1: mmc@ee120000 { 405 compatible = "renesas,sdhi-r8a73a4"; 406 reg = <0 0xee120000 0 0x100>; 407 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; 409 power-domains = <&pd_a3sp>; 410 cap-sd-highspeed; 411 status = "disabled"; 412 }; 413 414 sdhi2: mmc@ee140000 { 415 compatible = "renesas,sdhi-r8a73a4"; 416 reg = <0 0xee140000 0 0x100>; 417 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; 419 power-domains = <&pd_a3sp>; 420 cap-sd-highspeed; 421 status = "disabled"; 422 }; 423 424 mmcif0: mmc@ee200000 { 425 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 426 reg = <0 0xee200000 0 0x80>; 427 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; 429 power-domains = <&pd_a3sp>; 430 reg-io-width = <4>; 431 status = "disabled"; 432 }; 433 434 mmcif1: mmc@ee220000 { 435 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 436 reg = <0 0xee220000 0 0x80>; 437 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; 439 power-domains = <&pd_a3sp>; 440 reg-io-width = <4>; 441 status = "disabled"; 442 }; 443 444 gic: interrupt-controller@f1001000 { 445 compatible = "arm,gic-400"; 446 #interrupt-cells = <3>; 447 #address-cells = <0>; 448 interrupt-controller; 449 reg = <0 0xf1001000 0 0x1000>, 450 <0 0xf1002000 0 0x2000>, 451 <0 0xf1004000 0 0x2000>, 452 <0 0xf1006000 0 0x2000>; 453 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 454 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; 455 clock-names = "clk"; 456 power-domains = <&pd_c4>; 457 }; 458 459 bsc: bus@fec10000 { 460 compatible = "renesas,bsc-r8a73a4", "renesas,bsc", 461 "simple-pm-bus"; 462 #address-cells = <1>; 463 #size-cells = <1>; 464 ranges = <0 0 0 0x20000000>; 465 reg = <0 0xfec10000 0 0x400>; 466 clocks = <&zb_clk>; 467 power-domains = <&pd_c4>; 468 }; 469 470 clocks { 471 #address-cells = <2>; 472 #size-cells = <2>; 473 ranges; 474 475 /* External root clocks */ 476 extalr_clk: extalr { 477 compatible = "fixed-clock"; 478 #clock-cells = <0>; 479 /* This value must be overridden by the board. */ 480 clock-frequency = <0>; 481 }; 482 extal1_clk: extal1 { 483 compatible = "fixed-clock"; 484 #clock-cells = <0>; 485 /* This value must be overridden by the board. */ 486 clock-frequency = <0>; 487 }; 488 extal2_clk: extal2 { 489 compatible = "fixed-clock"; 490 #clock-cells = <0>; 491 /* This value must be overridden by the board. */ 492 clock-frequency = <0>; 493 }; 494 fsiack_clk: fsiack { 495 compatible = "fixed-clock"; 496 #clock-cells = <0>; 497 /* This value must be overridden by the board. */ 498 clock-frequency = <0>; 499 }; 500 fsibck_clk: fsibck { 501 compatible = "fixed-clock"; 502 #clock-cells = <0>; 503 /* This value must be overridden by the board. */ 504 clock-frequency = <0>; 505 }; 506 507 /* Special CPG clocks */ 508 cpg_clocks: cpg_clocks@e6150000 { 509 compatible = "renesas,r8a73a4-cpg-clocks"; 510 reg = <0 0xe6150000 0 0x10000>; 511 clocks = <&extal1_clk>, <&extal2_clk>; 512 #clock-cells = <1>; 513 clock-output-names = "main", "pll0", "pll1", "pll2", 514 "pll2s", "pll2h", "z", "z2", 515 "i", "m3", "b", "m1", "m2", 516 "zx", "zs", "hp"; 517 }; 518 519 /* Variable factor clocks (DIV6) */ 520 zb_clk: zb_clk@e6150010 { 521 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 522 reg = <0 0xe6150010 0 4>; 523 clocks = <&pll1_div2_clk>, <0>, 524 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 525 #clock-cells = <0>; 526 clock-output-names = "zb"; 527 }; 528 sdhi0_clk: sdhi0ck@e6150074 { 529 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 530 reg = <0 0xe6150074 0 4>; 531 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 532 <0>, <&extal2_clk>; 533 #clock-cells = <0>; 534 }; 535 sdhi1_clk: sdhi1ck@e6150078 { 536 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 537 reg = <0 0xe6150078 0 4>; 538 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 539 <0>, <&extal2_clk>; 540 #clock-cells = <0>; 541 }; 542 sdhi2_clk: sdhi2ck@e615007c { 543 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 544 reg = <0 0xe615007c 0 4>; 545 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 546 <0>, <&extal2_clk>; 547 #clock-cells = <0>; 548 }; 549 mmc0_clk: mmc0@e6150240 { 550 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 551 reg = <0 0xe6150240 0 4>; 552 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 553 <0>, <&extal2_clk>; 554 #clock-cells = <0>; 555 }; 556 mmc1_clk: mmc1@e6150244 { 557 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 558 reg = <0 0xe6150244 0 4>; 559 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 560 <0>, <&extal2_clk>; 561 #clock-cells = <0>; 562 }; 563 vclk1_clk: vclk1@e6150008 { 564 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 565 reg = <0 0xe6150008 0 4>; 566 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 567 <0>, <&extal2_clk>, <&main_div2_clk>, 568 <&extalr_clk>, <0>, <0>; 569 #clock-cells = <0>; 570 }; 571 vclk2_clk: vclk2@e615000c { 572 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 573 reg = <0 0xe615000c 0 4>; 574 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 575 <0>, <&extal2_clk>, <&main_div2_clk>, 576 <&extalr_clk>, <0>, <0>; 577 #clock-cells = <0>; 578 }; 579 vclk3_clk: vclk3@e615001c { 580 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 581 reg = <0 0xe615001c 0 4>; 582 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 583 <0>, <&extal2_clk>, <&main_div2_clk>, 584 <&extalr_clk>, <0>, <0>; 585 #clock-cells = <0>; 586 }; 587 vclk4_clk: vclk4@e6150014 { 588 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 589 reg = <0 0xe6150014 0 4>; 590 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 591 <0>, <&extal2_clk>, <&main_div2_clk>, 592 <&extalr_clk>, <0>, <0>; 593 #clock-cells = <0>; 594 }; 595 vclk5_clk: vclk5@e6150034 { 596 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 597 reg = <0 0xe6150034 0 4>; 598 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 599 <0>, <&extal2_clk>, <&main_div2_clk>, 600 <&extalr_clk>, <0>, <0>; 601 #clock-cells = <0>; 602 }; 603 fsia_clk: fsia@e6150018 { 604 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 605 reg = <0 0xe6150018 0 4>; 606 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 607 <&fsiack_clk>, <0>; 608 #clock-cells = <0>; 609 }; 610 fsib_clk: fsib@e6150090 { 611 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 612 reg = <0 0xe6150090 0 4>; 613 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 614 <&fsibck_clk>, <0>; 615 #clock-cells = <0>; 616 }; 617 mp_clk: mp@e6150080 { 618 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 619 reg = <0 0xe6150080 0 4>; 620 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 621 <&extal2_clk>, <&extal2_clk>; 622 #clock-cells = <0>; 623 }; 624 m4_clk: m4@e6150098 { 625 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 626 reg = <0 0xe6150098 0 4>; 627 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; 628 #clock-cells = <0>; 629 }; 630 hsi_clk: hsi@e615026c { 631 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 632 reg = <0 0xe615026c 0 4>; 633 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, 634 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 635 #clock-cells = <0>; 636 }; 637 spuv_clk: spuv@e6150094 { 638 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 639 reg = <0 0xe6150094 0 4>; 640 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 641 <&extal2_clk>, <&extal2_clk>; 642 #clock-cells = <0>; 643 }; 644 645 /* Fixed factor clocks */ 646 main_div2_clk: main_div2 { 647 compatible = "fixed-factor-clock"; 648 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; 649 #clock-cells = <0>; 650 clock-div = <2>; 651 clock-mult = <1>; 652 }; 653 cp_clk: cp { 654 compatible = "fixed-factor-clock"; 655 clocks = <&main_div2_clk>; 656 #clock-cells = <0>; 657 clock-div = <1>; 658 clock-mult = <1>; 659 }; 660 pll0_div2_clk: pll0_div2 { 661 compatible = "fixed-factor-clock"; 662 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; 663 #clock-cells = <0>; 664 clock-div = <2>; 665 clock-mult = <1>; 666 }; 667 pll1_div2_clk: pll1_div2 { 668 compatible = "fixed-factor-clock"; 669 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; 670 #clock-cells = <0>; 671 clock-div = <2>; 672 clock-mult = <1>; 673 }; 674 extal1_div2_clk: extal1_div2 { 675 compatible = "fixed-factor-clock"; 676 clocks = <&extal1_clk>; 677 #clock-cells = <0>; 678 clock-div = <2>; 679 clock-mult = <1>; 680 }; 681 682 /* Gate clocks */ 683 mstp1_clks: mstp1_clks@e6150134 { 684 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 685 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 686 clocks = <&cp_clk>, <&mp_clk>; 687 #clock-cells = <1>; 688 clock-indices = < 689 R8A73A4_CLK_TMU0 R8A73A4_CLK_TMU3 690 >; 691 clock-output-names = 692 "tmu0", "tmu3"; 693 }; 694 mstp2_clks: mstp2_clks@e6150138 { 695 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 696 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 697 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 698 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 699 #clock-cells = <1>; 700 clock-indices = < 701 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 702 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 703 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 704 R8A73A4_CLK_DMAC 705 >; 706 clock-output-names = 707 "scifa0", "scifa1", "scifb0", "scifb1", 708 "scifb2", "scifb3", "dmac"; 709 }; 710 mstp3_clks: mstp3_clks@e615013c { 711 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 712 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 713 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, 714 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, 715 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 716 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks 717 R8A73A4_CLK_HP>, <&cpg_clocks 718 R8A73A4_CLK_HP>, <&extalr_clk>; 719 #clock-cells = <1>; 720 clock-indices = < 721 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 722 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 723 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 724 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 725 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 726 R8A73A4_CLK_CMT1 727 >; 728 clock-output-names = 729 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", 730 "mmcif0", "iic6", "iic7", "iic0", "iic1", 731 "cmt1"; 732 }; 733 mstp4_clks: mstp4_clks@e6150140 { 734 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 735 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 736 clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, 737 <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 738 <&cpg_clocks R8A73A4_CLK_HP>; 739 #clock-cells = <1>; 740 clock-indices = < 741 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS 742 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 743 R8A73A4_CLK_IIC3 744 >; 745 clock-output-names = 746 "irqc", "intc-sys", "iic5", "iic4", "iic3"; 747 }; 748 mstp5_clks: mstp5_clks@e6150144 { 749 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 750 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 751 clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 752 #clock-cells = <1>; 753 clock-indices = < 754 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 755 >; 756 clock-output-names = 757 "thermal", "iic8"; 758 }; 759 }; 760 761 prr: chipid@ff000044 { 762 compatible = "renesas,prr"; 763 reg = <0 0xff000044 0 4>; 764 }; 765 766 sysc: system-controller@e6180000 { 767 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; 768 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; 769 770 pm-domains { 771 pd_c5: c5 { 772 #address-cells = <1>; 773 #size-cells = <0>; 774 #power-domain-cells = <0>; 775 776 pd_c4: c4@0 { 777 reg = <0>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 #power-domain-cells = <0>; 781 782 pd_a3sg: a3sg@16 { 783 reg = <16>; 784 #power-domain-cells = <0>; 785 }; 786 787 pd_a3ex: a3ex@17 { 788 reg = <17>; 789 #power-domain-cells = <0>; 790 }; 791 792 pd_a3sp: a3sp@18 { 793 reg = <18>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 #power-domain-cells = <0>; 797 798 pd_a2us: a2us@19 { 799 reg = <19>; 800 #power-domain-cells = <0>; 801 }; 802 }; 803 804 pd_a3sm: a3sm@20 { 805 reg = <20>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 #power-domain-cells = <0>; 809 810 pd_a2sl: a2sl@21 { 811 reg = <21>; 812 #power-domain-cells = <0>; 813 }; 814 }; 815 816 pd_a3km: a3km@22 { 817 reg = <22>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 #power-domain-cells = <0>; 821 822 pd_a2kl: a2kl@23 { 823 reg = <23>; 824 #power-domain-cells = <0>; 825 }; 826 }; 827 }; 828 829 pd_c4ma: c4ma@1 { 830 reg = <1>; 831 #power-domain-cells = <0>; 832 }; 833 834 pd_c4cl: c4cl@2 { 835 reg = <2>; 836 #power-domain-cells = <0>; 837 }; 838 839 pd_d4: d4@3 { 840 reg = <3>; 841 #power-domain-cells = <0>; 842 }; 843 844 pd_a4bc: a4bc@4 { 845 reg = <4>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 #power-domain-cells = <0>; 849 850 pd_a3bc: a3bc@5 { 851 reg = <5>; 852 #power-domain-cells = <0>; 853 }; 854 }; 855 856 pd_a4l: a4l@6 { 857 reg = <6>; 858 #power-domain-cells = <0>; 859 }; 860 861 pd_a4lc: a4lc@7 { 862 reg = <7>; 863 #power-domain-cells = <0>; 864 }; 865 866 pd_a4mp: a4mp@8 { 867 reg = <8>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 #power-domain-cells = <0>; 871 872 pd_a3mp: a3mp@9 { 873 reg = <9>; 874 #power-domain-cells = <0>; 875 }; 876 877 pd_a3vc: a3vc@10 { 878 reg = <10>; 879 #power-domain-cells = <0>; 880 }; 881 }; 882 883 pd_a4sf: a4sf@11 { 884 reg = <11>; 885 #power-domain-cells = <0>; 886 }; 887 888 pd_a3r: a3r@12 { 889 reg = <12>; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 #power-domain-cells = <0>; 893 894 pd_a2rv: a2rv@13 { 895 reg = <13>; 896 #power-domain-cells = <0>; 897 }; 898 899 pd_a2is: a2is@14 { 900 reg = <14>; 901 #power-domain-cells = <0>; 902 }; 903 }; 904 }; 905 }; 906 }; 907}; 908