1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r7s72100 SoC 4 * 5 * Copyright (C) 2013-14 Renesas Solutions Corp. 6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 7 */ 8 9#include <dt-bindings/clock/r7s72100-clock.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12 13/ { 14 compatible = "renesas,r7s72100"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 spi0 = &spi0; 24 spi1 = &spi1; 25 spi2 = &spi2; 26 spi3 = &spi3; 27 spi4 = &spi4; 28 }; 29 30 /* Fixed factor clocks */ 31 b_clk: b { 32 #clock-cells = <0>; 33 compatible = "fixed-factor-clock"; 34 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 35 clock-mult = <1>; 36 clock-div = <3>; 37 }; 38 39 bsc: bsc { 40 compatible = "simple-bus"; 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0 0 0x18000000>; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a9"; 53 reg = <0>; 54 clock-frequency = <400000000>; 55 clocks = <&cpg_clocks R7S72100_CLK_I>; 56 next-level-cache = <&L2>; 57 }; 58 }; 59 60 /* External clocks */ 61 extal_clk: extal { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 /* If clk present, value must be set by board */ 65 clock-frequency = <0>; 66 }; 67 68 p0_clk: p0 { 69 #clock-cells = <0>; 70 compatible = "fixed-factor-clock"; 71 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 72 clock-mult = <1>; 73 clock-div = <12>; 74 }; 75 76 p1_clk: p1 { 77 #clock-cells = <0>; 78 compatible = "fixed-factor-clock"; 79 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 80 clock-mult = <1>; 81 clock-div = <6>; 82 }; 83 84 pmu { 85 compatible = "arm,cortex-a9-pmu"; 86 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; 87 }; 88 89 rtc_x1_clk: rtc_x1 { 90 #clock-cells = <0>; 91 compatible = "fixed-clock"; 92 /* If clk present, value must be set by board to 32678 */ 93 clock-frequency = <0>; 94 }; 95 96 rtc_x3_clk: rtc_x3 { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 /* If clk present, value must be set by board to 4000000 */ 100 clock-frequency = <0>; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 interrupt-parent = <&gic>; 106 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 111 L2: cache-controller@3ffff000 { 112 compatible = "arm,pl310-cache"; 113 reg = <0x3ffff000 0x1000>; 114 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 115 arm,early-bresp-disable; 116 arm,full-line-zero-disable; 117 cache-unified; 118 cache-level = <2>; 119 }; 120 121 scif0: serial@e8007000 { 122 compatible = "renesas,scif-r7s72100", "renesas,scif"; 123 reg = <0xe8007000 64>; 124 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 128 interrupt-names = "eri", "rxi", "txi", "bri"; 129 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; 130 clock-names = "fck"; 131 power-domains = <&cpg_clocks>; 132 status = "disabled"; 133 }; 134 135 scif1: serial@e8007800 { 136 compatible = "renesas,scif-r7s72100", "renesas,scif"; 137 reg = <0xe8007800 64>; 138 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 142 interrupt-names = "eri", "rxi", "txi", "bri"; 143 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; 144 clock-names = "fck"; 145 power-domains = <&cpg_clocks>; 146 status = "disabled"; 147 }; 148 149 scif2: serial@e8008000 { 150 compatible = "renesas,scif-r7s72100", "renesas,scif"; 151 reg = <0xe8008000 64>; 152 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 156 interrupt-names = "eri", "rxi", "txi", "bri"; 157 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; 158 clock-names = "fck"; 159 power-domains = <&cpg_clocks>; 160 status = "disabled"; 161 }; 162 163 scif3: serial@e8008800 { 164 compatible = "renesas,scif-r7s72100", "renesas,scif"; 165 reg = <0xe8008800 64>; 166 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 170 interrupt-names = "eri", "rxi", "txi", "bri"; 171 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; 172 clock-names = "fck"; 173 power-domains = <&cpg_clocks>; 174 status = "disabled"; 175 }; 176 177 scif4: serial@e8009000 { 178 compatible = "renesas,scif-r7s72100", "renesas,scif"; 179 reg = <0xe8009000 64>; 180 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "eri", "rxi", "txi", "bri"; 185 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; 186 clock-names = "fck"; 187 power-domains = <&cpg_clocks>; 188 status = "disabled"; 189 }; 190 191 scif5: serial@e8009800 { 192 compatible = "renesas,scif-r7s72100", "renesas,scif"; 193 reg = <0xe8009800 64>; 194 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-names = "eri", "rxi", "txi", "bri"; 199 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; 200 clock-names = "fck"; 201 power-domains = <&cpg_clocks>; 202 status = "disabled"; 203 }; 204 205 scif6: serial@e800a000 { 206 compatible = "renesas,scif-r7s72100", "renesas,scif"; 207 reg = <0xe800a000 64>; 208 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "eri", "rxi", "txi", "bri"; 213 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; 214 clock-names = "fck"; 215 power-domains = <&cpg_clocks>; 216 status = "disabled"; 217 }; 218 219 scif7: serial@e800a800 { 220 compatible = "renesas,scif-r7s72100", "renesas,scif"; 221 reg = <0xe800a800 64>; 222 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "eri", "rxi", "txi", "bri"; 227 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; 228 clock-names = "fck"; 229 power-domains = <&cpg_clocks>; 230 status = "disabled"; 231 }; 232 233 spi0: spi@e800c800 { 234 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 235 reg = <0xe800c800 0x24>; 236 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 239 interrupt-names = "error", "rx", "tx"; 240 clocks = <&mstp10_clks R7S72100_CLK_SPI0>; 241 power-domains = <&cpg_clocks>; 242 num-cs = <1>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 status = "disabled"; 246 }; 247 248 spi1: spi@e800d000 { 249 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 250 reg = <0xe800d000 0x24>; 251 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 254 interrupt-names = "error", "rx", "tx"; 255 clocks = <&mstp10_clks R7S72100_CLK_SPI1>; 256 power-domains = <&cpg_clocks>; 257 num-cs = <1>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 status = "disabled"; 261 }; 262 263 spi2: spi@e800d800 { 264 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 265 reg = <0xe800d800 0x24>; 266 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 269 interrupt-names = "error", "rx", "tx"; 270 clocks = <&mstp10_clks R7S72100_CLK_SPI2>; 271 power-domains = <&cpg_clocks>; 272 num-cs = <1>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 status = "disabled"; 276 }; 277 278 spi3: spi@e800e000 { 279 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 280 reg = <0xe800e000 0x24>; 281 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-names = "error", "rx", "tx"; 285 clocks = <&mstp10_clks R7S72100_CLK_SPI3>; 286 power-domains = <&cpg_clocks>; 287 num-cs = <1>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 status = "disabled"; 291 }; 292 293 spi4: spi@e800e800 { 294 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 295 reg = <0xe800e800 0x24>; 296 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-names = "error", "rx", "tx"; 300 clocks = <&mstp10_clks R7S72100_CLK_SPI4>; 301 power-domains = <&cpg_clocks>; 302 num-cs = <1>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 status = "disabled"; 306 }; 307 308 usbhs0: usb@e8010000 { 309 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; 310 reg = <0xe8010000 0x1a0>; 311 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&mstp7_clks R7S72100_CLK_USB0>; 313 renesas,buswait = <4>; 314 power-domains = <&cpg_clocks>; 315 status = "disabled"; 316 }; 317 318 usbhs1: usb@e8207000 { 319 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; 320 reg = <0xe8207000 0x1a0>; 321 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&mstp7_clks R7S72100_CLK_USB1>; 323 renesas,buswait = <4>; 324 power-domains = <&cpg_clocks>; 325 status = "disabled"; 326 }; 327 328 mmcif: mmc@e804c800 { 329 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; 330 reg = <0xe804c800 0x80>; 331 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; 335 power-domains = <&cpg_clocks>; 336 reg-io-width = <4>; 337 bus-width = <8>; 338 status = "disabled"; 339 }; 340 341 sdhi0: mmc@e804e000 { 342 compatible = "renesas,sdhi-r7s72100"; 343 reg = <0xe804e000 0x100>; 344 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 347 348 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, 349 <&mstp12_clks R7S72100_CLK_SDHI01>; 350 clock-names = "core", "cd"; 351 power-domains = <&cpg_clocks>; 352 cap-sd-highspeed; 353 cap-sdio-irq; 354 status = "disabled"; 355 }; 356 357 sdhi1: mmc@e804e800 { 358 compatible = "renesas,sdhi-r7s72100"; 359 reg = <0xe804e800 0x100>; 360 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 363 364 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, 365 <&mstp12_clks R7S72100_CLK_SDHI11>; 366 clock-names = "core", "cd"; 367 power-domains = <&cpg_clocks>; 368 cap-sd-highspeed; 369 cap-sdio-irq; 370 status = "disabled"; 371 }; 372 373 gic: interrupt-controller@e8201000 { 374 compatible = "arm,pl390"; 375 #interrupt-cells = <3>; 376 #address-cells = <0>; 377 interrupt-controller; 378 reg = <0xe8201000 0x1000>, 379 <0xe8202000 0x1000>; 380 }; 381 382 ether: ethernet@e8203000 { 383 compatible = "renesas,ether-r7s72100"; 384 reg = <0xe8203000 0x800>, 385 <0xe8204800 0x200>; 386 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&mstp7_clks R7S72100_CLK_ETHER>; 388 power-domains = <&cpg_clocks>; 389 phy-mode = "mii"; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 status = "disabled"; 393 }; 394 395 ceu: camera@e8210000 { 396 reg = <0xe8210000 0x3000>; 397 compatible = "renesas,r7s72100-ceu"; 398 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&mstp6_clks R7S72100_CLK_CEU>; 400 power-domains = <&cpg_clocks>; 401 status = "disabled"; 402 }; 403 404 wdt: watchdog@fcfe0000 { 405 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; 406 reg = <0xfcfe0000 0x6>; 407 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&p0_clk>; 409 }; 410 411 /* Special CPG clocks */ 412 cpg_clocks: cpg_clocks@fcfe0000 { 413 #clock-cells = <1>; 414 compatible = "renesas,r7s72100-cpg-clocks", 415 "renesas,rz-cpg-clocks"; 416 reg = <0xfcfe0000 0x18>; 417 clocks = <&extal_clk>, <&usb_x1_clk>; 418 clock-output-names = "pll", "i", "g"; 419 #power-domain-cells = <0>; 420 }; 421 422 /* MSTP clocks */ 423 mstp3_clks: mstp3_clks@fcfe0420 { 424 #clock-cells = <1>; 425 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 426 reg = <0xfcfe0420 4>; 427 clocks = <&p0_clk>; 428 clock-indices = <R7S72100_CLK_MTU2>; 429 clock-output-names = "mtu2"; 430 }; 431 432 mstp4_clks: mstp4_clks@fcfe0424 { 433 #clock-cells = <1>; 434 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 435 reg = <0xfcfe0424 4>; 436 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 437 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; 438 clock-indices = < 439 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 440 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 441 >; 442 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; 443 }; 444 445 mstp5_clks: mstp5_clks@fcfe0428 { 446 #clock-cells = <1>; 447 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 448 reg = <0xfcfe0428 4>; 449 clocks = <&p0_clk>, <&p0_clk>; 450 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>; 451 clock-output-names = "ostm0", "ostm1"; 452 }; 453 454 mstp6_clks: mstp6_clks@fcfe042c { 455 #clock-cells = <1>; 456 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 457 reg = <0xfcfe042c 4>; 458 clocks = <&b_clk>, <&p0_clk>; 459 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>; 460 clock-output-names = "ceu", "rtc"; 461 }; 462 463 mstp7_clks: mstp7_clks@fcfe0430 { 464 #clock-cells = <1>; 465 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 466 reg = <0xfcfe0430 4>; 467 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; 468 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>; 469 clock-output-names = "ether", "usb0", "usb1"; 470 }; 471 472 mstp8_clks: mstp8_clks@fcfe0434 { 473 #clock-cells = <1>; 474 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 475 reg = <0xfcfe0434 4>; 476 clocks = <&p1_clk>; 477 clock-indices = <R7S72100_CLK_MMCIF>; 478 clock-output-names = "mmcif"; 479 }; 480 481 mstp9_clks: mstp9_clks@fcfe0438 { 482 #clock-cells = <1>; 483 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 484 reg = <0xfcfe0438 4>; 485 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>; 486 clock-indices = < 487 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 488 R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1 489 >; 490 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1"; 491 }; 492 493 mstp10_clks: mstp10_clks@fcfe043c { 494 #clock-cells = <1>; 495 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 496 reg = <0xfcfe043c 4>; 497 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 498 <&p1_clk>; 499 clock-indices = < 500 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 501 R7S72100_CLK_SPI4 502 >; 503 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; 504 }; 505 mstp12_clks: mstp12_clks@fcfe0444 { 506 #clock-cells = <1>; 507 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 508 reg = <0xfcfe0444 4>; 509 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; 510 clock-indices = < 511 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 512 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 513 >; 514 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; 515 }; 516 517 pinctrl: pinctrl@fcfe3000 { 518 compatible = "renesas,r7s72100-ports"; 519 520 reg = <0xfcfe3000 0x4230>; 521 522 port0: gpio-0 { 523 gpio-controller; 524 #gpio-cells = <2>; 525 gpio-ranges = <&pinctrl 0 0 6>; 526 }; 527 528 port1: gpio-1 { 529 gpio-controller; 530 #gpio-cells = <2>; 531 gpio-ranges = <&pinctrl 0 16 16>; 532 }; 533 534 port2: gpio-2 { 535 gpio-controller; 536 #gpio-cells = <2>; 537 gpio-ranges = <&pinctrl 0 32 16>; 538 }; 539 540 port3: gpio-3 { 541 gpio-controller; 542 #gpio-cells = <2>; 543 gpio-ranges = <&pinctrl 0 48 16>; 544 }; 545 546 port4: gpio-4 { 547 gpio-controller; 548 #gpio-cells = <2>; 549 gpio-ranges = <&pinctrl 0 64 16>; 550 }; 551 552 port5: gpio-5 { 553 gpio-controller; 554 #gpio-cells = <2>; 555 gpio-ranges = <&pinctrl 0 80 11>; 556 }; 557 558 port6: gpio-6 { 559 gpio-controller; 560 #gpio-cells = <2>; 561 gpio-ranges = <&pinctrl 0 96 16>; 562 }; 563 564 port7: gpio-7 { 565 gpio-controller; 566 #gpio-cells = <2>; 567 gpio-ranges = <&pinctrl 0 112 16>; 568 }; 569 570 port8: gpio-8 { 571 gpio-controller; 572 #gpio-cells = <2>; 573 gpio-ranges = <&pinctrl 0 128 16>; 574 }; 575 576 port9: gpio-9 { 577 gpio-controller; 578 #gpio-cells = <2>; 579 gpio-ranges = <&pinctrl 0 144 8>; 580 }; 581 582 port10: gpio-10 { 583 gpio-controller; 584 #gpio-cells = <2>; 585 gpio-ranges = <&pinctrl 0 160 16>; 586 }; 587 588 port11: gpio-11 { 589 gpio-controller; 590 #gpio-cells = <2>; 591 gpio-ranges = <&pinctrl 0 176 16>; 592 }; 593 }; 594 595 ostm0: timer@fcfec000 { 596 compatible = "renesas,r7s72100-ostm", "renesas,ostm"; 597 reg = <0xfcfec000 0x30>; 598 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; 599 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; 600 power-domains = <&cpg_clocks>; 601 status = "disabled"; 602 }; 603 604 ostm1: timer@fcfec400 { 605 compatible = "renesas,r7s72100-ostm", "renesas,ostm"; 606 reg = <0xfcfec400 0x30>; 607 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>; 608 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; 609 power-domains = <&cpg_clocks>; 610 status = "disabled"; 611 }; 612 613 i2c0: i2c@fcfee000 { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 617 reg = <0xfcfee000 0x44>; 618 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, 620 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, 621 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "tei", "ri", "ti", "spi", "sti", 627 "naki", "ali", "tmoi"; 628 clocks = <&mstp9_clks R7S72100_CLK_I2C0>; 629 clock-frequency = <100000>; 630 power-domains = <&cpg_clocks>; 631 status = "disabled"; 632 }; 633 634 i2c1: i2c@fcfee400 { 635 #address-cells = <1>; 636 #size-cells = <0>; 637 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 638 reg = <0xfcfee400 0x44>; 639 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, 641 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, 642 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "tei", "ri", "ti", "spi", "sti", 648 "naki", "ali", "tmoi"; 649 clocks = <&mstp9_clks R7S72100_CLK_I2C1>; 650 clock-frequency = <100000>; 651 power-domains = <&cpg_clocks>; 652 status = "disabled"; 653 }; 654 655 i2c2: i2c@fcfee800 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 659 reg = <0xfcfee800 0x44>; 660 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, 662 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, 663 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 668 interrupt-names = "tei", "ri", "ti", "spi", "sti", 669 "naki", "ali", "tmoi"; 670 clocks = <&mstp9_clks R7S72100_CLK_I2C2>; 671 clock-frequency = <100000>; 672 power-domains = <&cpg_clocks>; 673 status = "disabled"; 674 }; 675 676 i2c3: i2c@fcfeec00 { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 680 reg = <0xfcfeec00 0x44>; 681 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, 683 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, 684 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 689 interrupt-names = "tei", "ri", "ti", "spi", "sti", 690 "naki", "ali", "tmoi"; 691 clocks = <&mstp9_clks R7S72100_CLK_I2C3>; 692 clock-frequency = <100000>; 693 power-domains = <&cpg_clocks>; 694 status = "disabled"; 695 }; 696 697 irqc: interrupt-controller@fcfef800 { 698 compatible = "renesas,r7s72100-irqc", 699 "renesas,rza1-irqc"; 700 #interrupt-cells = <2>; 701 #address-cells = <0>; 702 interrupt-controller; 703 reg = <0xfcfef800 0x6>; 704 interrupt-map = 705 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 706 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 707 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 708 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 709 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 710 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 711 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 712 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 713 interrupt-map-mask = <7 0>; 714 }; 715 716 mtu2: timer@fcff0000 { 717 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; 718 reg = <0xfcff0000 0x400>; 719 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 720 interrupt-names = "tgi0a"; 721 clocks = <&mstp3_clks R7S72100_CLK_MTU2>; 722 clock-names = "fck"; 723 power-domains = <&cpg_clocks>; 724 status = "disabled"; 725 }; 726 727 rtc: rtc@fcff1000 { 728 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; 729 reg = <0xfcff1000 0x2e>; 730 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 733 interrupt-names = "alarm", "period", "carry"; 734 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, 735 <&rtc_x3_clk>, <&extal_clk>; 736 clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; 737 power-domains = <&cpg_clocks>; 738 status = "disabled"; 739 }; 740 }; 741 742 usb_x1_clk: usb_x1 { 743 #clock-cells = <0>; 744 compatible = "fixed-clock"; 745 /* If clk present, value must be set by board */ 746 clock-frequency = <0>; 747 }; 748}; 749