1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r7s72100 SoC 4 * 5 * Copyright (C) 2013-14 Renesas Solutions Corp. 6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 7 */ 8 9#include <dt-bindings/clock/r7s72100-clock.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12 13/ { 14 compatible = "renesas,r7s72100"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 spi0 = &spi0; 24 spi1 = &spi1; 25 spi2 = &spi2; 26 spi3 = &spi3; 27 spi4 = &spi4; 28 }; 29 30 /* Fixed factor clocks */ 31 b_clk: b { 32 #clock-cells = <0>; 33 compatible = "fixed-factor-clock"; 34 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 35 clock-mult = <1>; 36 clock-div = <3>; 37 }; 38 39 bsc: bus { 40 compatible = "simple-bus"; 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0 0 0x18000000>; 44 bootph-all; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a9"; 54 reg = <0>; 55 clock-frequency = <400000000>; 56 clocks = <&cpg_clocks R7S72100_CLK_I>; 57 next-level-cache = <&L2>; 58 }; 59 }; 60 61 /* External clocks */ 62 extal_clk: extal { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 /* If clk present, value must be set by board */ 66 clock-frequency = <0>; 67 }; 68 69 p0_clk: p0 { 70 #clock-cells = <0>; 71 compatible = "fixed-factor-clock"; 72 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 73 clock-mult = <1>; 74 clock-div = <12>; 75 }; 76 77 p1_clk: p1 { 78 #clock-cells = <0>; 79 compatible = "fixed-factor-clock"; 80 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 81 clock-mult = <1>; 82 clock-div = <6>; 83 }; 84 85 pmu { 86 compatible = "arm,cortex-a9-pmu"; 87 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; 88 }; 89 90 rtc_x1_clk: rtc_x1 { 91 #clock-cells = <0>; 92 compatible = "fixed-clock"; 93 /* If clk present, value must be set by board to 32678 */ 94 clock-frequency = <0>; 95 }; 96 97 rtc_x3_clk: rtc_x3 { 98 #clock-cells = <0>; 99 compatible = "fixed-clock"; 100 /* If clk present, value must be set by board to 4000000 */ 101 clock-frequency = <0>; 102 }; 103 104 soc { 105 compatible = "simple-bus"; 106 interrupt-parent = <&gic>; 107 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 bootph-all; 112 113 L2: cache-controller@3ffff000 { 114 compatible = "arm,pl310-cache"; 115 reg = <0x3ffff000 0x1000>; 116 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 117 arm,early-bresp-disable; 118 arm,full-line-zero-disable; 119 cache-unified; 120 cache-level = <2>; 121 }; 122 123 scif0: serial@e8007000 { 124 compatible = "renesas,scif-r7s72100", "renesas,scif"; 125 reg = <0xe8007000 64>; 126 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 130 interrupt-names = "eri", "rxi", "txi", "bri"; 131 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; 132 clock-names = "fck"; 133 power-domains = <&cpg_clocks>; 134 status = "disabled"; 135 }; 136 137 scif1: serial@e8007800 { 138 compatible = "renesas,scif-r7s72100", "renesas,scif"; 139 reg = <0xe8007800 64>; 140 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 144 interrupt-names = "eri", "rxi", "txi", "bri"; 145 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; 146 clock-names = "fck"; 147 power-domains = <&cpg_clocks>; 148 status = "disabled"; 149 }; 150 151 scif2: serial@e8008000 { 152 compatible = "renesas,scif-r7s72100", "renesas,scif"; 153 reg = <0xe8008000 64>; 154 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "eri", "rxi", "txi", "bri"; 159 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; 160 clock-names = "fck"; 161 power-domains = <&cpg_clocks>; 162 status = "disabled"; 163 }; 164 165 scif3: serial@e8008800 { 166 compatible = "renesas,scif-r7s72100", "renesas,scif"; 167 reg = <0xe8008800 64>; 168 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 172 interrupt-names = "eri", "rxi", "txi", "bri"; 173 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; 174 clock-names = "fck"; 175 power-domains = <&cpg_clocks>; 176 status = "disabled"; 177 }; 178 179 scif4: serial@e8009000 { 180 compatible = "renesas,scif-r7s72100", "renesas,scif"; 181 reg = <0xe8009000 64>; 182 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "eri", "rxi", "txi", "bri"; 187 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; 188 clock-names = "fck"; 189 power-domains = <&cpg_clocks>; 190 status = "disabled"; 191 }; 192 193 scif5: serial@e8009800 { 194 compatible = "renesas,scif-r7s72100", "renesas,scif"; 195 reg = <0xe8009800 64>; 196 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 200 interrupt-names = "eri", "rxi", "txi", "bri"; 201 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; 202 clock-names = "fck"; 203 power-domains = <&cpg_clocks>; 204 status = "disabled"; 205 }; 206 207 scif6: serial@e800a000 { 208 compatible = "renesas,scif-r7s72100", "renesas,scif"; 209 reg = <0xe800a000 64>; 210 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-names = "eri", "rxi", "txi", "bri"; 215 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; 216 clock-names = "fck"; 217 power-domains = <&cpg_clocks>; 218 status = "disabled"; 219 }; 220 221 scif7: serial@e800a800 { 222 compatible = "renesas,scif-r7s72100", "renesas,scif"; 223 reg = <0xe800a800 64>; 224 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 228 interrupt-names = "eri", "rxi", "txi", "bri"; 229 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; 230 clock-names = "fck"; 231 power-domains = <&cpg_clocks>; 232 status = "disabled"; 233 }; 234 235 spi0: spi@e800c800 { 236 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 237 reg = <0xe800c800 0x24>; 238 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 241 interrupt-names = "error", "rx", "tx"; 242 clocks = <&mstp10_clks R7S72100_CLK_SPI0>; 243 dmas = <&dmac 0x2d21>, <&dmac 0x2d22>; 244 dma-names = "tx", "rx"; 245 power-domains = <&cpg_clocks>; 246 num-cs = <1>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 status = "disabled"; 250 }; 251 252 spi1: spi@e800d000 { 253 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 254 reg = <0xe800d000 0x24>; 255 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 258 interrupt-names = "error", "rx", "tx"; 259 clocks = <&mstp10_clks R7S72100_CLK_SPI1>; 260 dmas = <&dmac 0x2d25>, <&dmac 0x2d26>; 261 dma-names = "tx", "rx"; 262 power-domains = <&cpg_clocks>; 263 num-cs = <1>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 status = "disabled"; 267 }; 268 269 spi2: spi@e800d800 { 270 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 271 reg = <0xe800d800 0x24>; 272 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 275 interrupt-names = "error", "rx", "tx"; 276 clocks = <&mstp10_clks R7S72100_CLK_SPI2>; 277 dmas = <&dmac 0x2d29>, <&dmac 0x2d2a>; 278 dma-names = "tx", "rx"; 279 power-domains = <&cpg_clocks>; 280 num-cs = <1>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 status = "disabled"; 284 }; 285 286 spi3: spi@e800e000 { 287 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 288 reg = <0xe800e000 0x24>; 289 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-names = "error", "rx", "tx"; 293 clocks = <&mstp10_clks R7S72100_CLK_SPI3>; 294 dmas = <&dmac 0x2d2d>, <&dmac 0x2d2e>; 295 dma-names = "tx", "rx"; 296 power-domains = <&cpg_clocks>; 297 num-cs = <1>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 303 spi4: spi@e800e800 { 304 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 305 reg = <0xe800e800 0x24>; 306 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 309 interrupt-names = "error", "rx", "tx"; 310 clocks = <&mstp10_clks R7S72100_CLK_SPI4>; 311 dmas = <&dmac 0x2d31>, <&dmac 0x2d32>; 312 dma-names = "tx", "rx"; 313 power-domains = <&cpg_clocks>; 314 num-cs = <1>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 status = "disabled"; 318 }; 319 320 usbhs0: usb@e8010000 { 321 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; 322 reg = <0xe8010000 0x1a0>; 323 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&mstp7_clks R7S72100_CLK_USB0>; 325 renesas,buswait = <4>; 326 power-domains = <&cpg_clocks>; 327 status = "disabled"; 328 }; 329 330 usbhs1: usb@e8207000 { 331 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; 332 reg = <0xe8207000 0x1a0>; 333 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&mstp7_clks R7S72100_CLK_USB1>; 335 renesas,buswait = <4>; 336 power-domains = <&cpg_clocks>; 337 status = "disabled"; 338 }; 339 340 mmcif: mmc@e804c800 { 341 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; 342 reg = <0xe804c800 0x80>; 343 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; 347 dmas = <&dmac 0x2cc9>, <&dmac 0x2cca>; 348 dma-names = "tx", "rx"; 349 power-domains = <&cpg_clocks>; 350 status = "disabled"; 351 }; 352 353 sdhi0: mmc@e804e000 { 354 compatible = "renesas,sdhi-r7s72100"; 355 reg = <0xe804e000 0x100>; 356 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 359 360 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, 361 <&mstp12_clks R7S72100_CLK_SDHI01>; 362 clock-names = "core", "cd"; 363 power-domains = <&cpg_clocks>; 364 cap-sd-highspeed; 365 cap-sdio-irq; 366 status = "disabled"; 367 }; 368 369 sdhi1: mmc@e804e800 { 370 compatible = "renesas,sdhi-r7s72100"; 371 reg = <0xe804e800 0x100>; 372 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 375 376 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, 377 <&mstp12_clks R7S72100_CLK_SDHI11>; 378 clock-names = "core", "cd"; 379 power-domains = <&cpg_clocks>; 380 cap-sd-highspeed; 381 cap-sdio-irq; 382 status = "disabled"; 383 }; 384 385 dmac: dma-controller@e8200000 { 386 compatible = "renesas,r7s72100-dmac", 387 "renesas,rz-dmac"; 388 reg = <0xe8200000 0x1000>, 389 <0xfcfe1000 0x20>; 390 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>, 392 <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>, 393 <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>, 394 <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, 395 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>, 396 <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>, 397 <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>, 398 <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>, 399 <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>, 400 <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>, 401 <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 402 <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, 403 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 404 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, 405 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>, 406 <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 407 interrupt-names = "error", 408 "ch0", "ch1", "ch2", "ch3", 409 "ch4", "ch5", "ch6", "ch7", 410 "ch8", "ch9", "ch10", "ch11", 411 "ch12", "ch13", "ch14", "ch15"; 412 #dma-cells = <1>; 413 dma-channels = <16>; 414 }; 415 416 gic: interrupt-controller@e8201000 { 417 compatible = "arm,pl390"; 418 #interrupt-cells = <3>; 419 #address-cells = <0>; 420 interrupt-controller; 421 reg = <0xe8201000 0x1000>, 422 <0xe8202000 0x1000>; 423 }; 424 425 ether: ethernet@e8203000 { 426 compatible = "renesas,ether-r7s72100"; 427 reg = <0xe8203000 0x800>, 428 <0xe8204800 0x200>; 429 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&mstp7_clks R7S72100_CLK_ETHER>; 431 power-domains = <&cpg_clocks>; 432 phy-mode = "mii"; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 status = "disabled"; 436 }; 437 438 ceu: camera@e8210000 { 439 reg = <0xe8210000 0x3000>; 440 compatible = "renesas,r7s72100-ceu"; 441 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&mstp6_clks R7S72100_CLK_CEU>; 443 power-domains = <&cpg_clocks>; 444 status = "disabled"; 445 }; 446 447 wdt: watchdog@fcfe0000 { 448 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; 449 reg = <0xfcfe0000 0x6>; 450 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&p0_clk>; 452 }; 453 454 /* Special CPG clocks */ 455 cpg_clocks: cpg_clocks@fcfe0000 { 456 #clock-cells = <1>; 457 compatible = "renesas,r7s72100-cpg-clocks", 458 "renesas,rz-cpg-clocks"; 459 reg = <0xfcfe0000 0x18>; 460 clocks = <&extal_clk>, <&usb_x1_clk>; 461 clock-output-names = "pll", "i", "g"; 462 #power-domain-cells = <0>; 463 }; 464 465 /* MSTP clocks */ 466 mstp3_clks: mstp3_clks@fcfe0420 { 467 #clock-cells = <1>; 468 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 469 reg = <0xfcfe0420 4>; 470 clocks = <&p0_clk>; 471 clock-indices = <R7S72100_CLK_MTU2>; 472 clock-output-names = "mtu2"; 473 }; 474 475 mstp4_clks: mstp4_clks@fcfe0424 { 476 #clock-cells = <1>; 477 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 478 reg = <0xfcfe0424 4>; 479 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 480 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; 481 clock-indices = < 482 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 483 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 484 >; 485 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; 486 }; 487 488 mstp5_clks: mstp5_clks@fcfe0428 { 489 #clock-cells = <1>; 490 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 491 reg = <0xfcfe0428 4>; 492 clocks = <&p0_clk>, <&p0_clk>; 493 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>; 494 clock-output-names = "ostm0", "ostm1"; 495 }; 496 497 mstp6_clks: mstp6_clks@fcfe042c { 498 #clock-cells = <1>; 499 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 500 reg = <0xfcfe042c 4>; 501 clocks = <&b_clk>, <&p0_clk>; 502 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>; 503 clock-output-names = "ceu", "rtc"; 504 }; 505 506 mstp7_clks: mstp7_clks@fcfe0430 { 507 #clock-cells = <1>; 508 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 509 reg = <0xfcfe0430 4>; 510 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; 511 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>; 512 clock-output-names = "ether", "usb0", "usb1"; 513 }; 514 515 mstp8_clks: mstp8_clks@fcfe0434 { 516 #clock-cells = <1>; 517 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 518 reg = <0xfcfe0434 4>; 519 clocks = <&p1_clk>; 520 clock-indices = <R7S72100_CLK_MMCIF>; 521 clock-output-names = "mmcif"; 522 }; 523 524 mstp9_clks: mstp9_clks@fcfe0438 { 525 #clock-cells = <1>; 526 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 527 reg = <0xfcfe0438 4>; 528 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>; 529 clock-indices = < 530 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 531 R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1 532 >; 533 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1"; 534 }; 535 536 mstp10_clks: mstp10_clks@fcfe043c { 537 #clock-cells = <1>; 538 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 539 reg = <0xfcfe043c 4>; 540 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 541 <&p1_clk>; 542 clock-indices = < 543 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 544 R7S72100_CLK_SPI4 545 >; 546 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; 547 }; 548 mstp12_clks: mstp12_clks@fcfe0444 { 549 #clock-cells = <1>; 550 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 551 reg = <0xfcfe0444 4>; 552 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; 553 clock-indices = < 554 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 555 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 556 >; 557 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; 558 }; 559 560 pinctrl: pinctrl@fcfe3000 { 561 compatible = "renesas,r7s72100-ports"; 562 bootph-all; 563 564 reg = <0xfcfe3000 0x4230>; 565 566 port0: gpio-0 { 567 gpio-controller; 568 #gpio-cells = <2>; 569 gpio-ranges = <&pinctrl 0 0 6>; 570 }; 571 572 port1: gpio-1 { 573 gpio-controller; 574 #gpio-cells = <2>; 575 gpio-ranges = <&pinctrl 0 16 16>; 576 }; 577 578 port2: gpio-2 { 579 gpio-controller; 580 #gpio-cells = <2>; 581 gpio-ranges = <&pinctrl 0 32 16>; 582 }; 583 584 port3: gpio-3 { 585 gpio-controller; 586 #gpio-cells = <2>; 587 gpio-ranges = <&pinctrl 0 48 16>; 588 }; 589 590 port4: gpio-4 { 591 gpio-controller; 592 #gpio-cells = <2>; 593 gpio-ranges = <&pinctrl 0 64 16>; 594 }; 595 596 port5: gpio-5 { 597 gpio-controller; 598 #gpio-cells = <2>; 599 gpio-ranges = <&pinctrl 0 80 11>; 600 }; 601 602 port6: gpio-6 { 603 gpio-controller; 604 #gpio-cells = <2>; 605 gpio-ranges = <&pinctrl 0 96 16>; 606 }; 607 608 port7: gpio-7 { 609 gpio-controller; 610 #gpio-cells = <2>; 611 gpio-ranges = <&pinctrl 0 112 16>; 612 }; 613 614 port8: gpio-8 { 615 gpio-controller; 616 #gpio-cells = <2>; 617 gpio-ranges = <&pinctrl 0 128 16>; 618 }; 619 620 port9: gpio-9 { 621 gpio-controller; 622 #gpio-cells = <2>; 623 gpio-ranges = <&pinctrl 0 144 8>; 624 }; 625 626 port10: gpio-10 { 627 gpio-controller; 628 #gpio-cells = <2>; 629 gpio-ranges = <&pinctrl 0 160 16>; 630 }; 631 632 port11: gpio-11 { 633 gpio-controller; 634 #gpio-cells = <2>; 635 gpio-ranges = <&pinctrl 0 176 16>; 636 }; 637 }; 638 639 ostm0: timer@fcfec000 { 640 compatible = "renesas,r7s72100-ostm", "renesas,ostm"; 641 reg = <0xfcfec000 0x30>; 642 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; 643 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; 644 power-domains = <&cpg_clocks>; 645 status = "disabled"; 646 }; 647 648 ostm1: timer@fcfec400 { 649 compatible = "renesas,r7s72100-ostm", "renesas,ostm"; 650 reg = <0xfcfec400 0x30>; 651 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>; 652 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; 653 power-domains = <&cpg_clocks>; 654 status = "disabled"; 655 }; 656 657 i2c0: i2c@fcfee000 { 658 #address-cells = <1>; 659 #size-cells = <0>; 660 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 661 reg = <0xfcfee000 0x44>; 662 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, 664 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, 665 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 670 interrupt-names = "tei", "ri", "ti", "spi", "sti", 671 "naki", "ali", "tmoi"; 672 clocks = <&mstp9_clks R7S72100_CLK_I2C0>; 673 clock-frequency = <100000>; 674 power-domains = <&cpg_clocks>; 675 status = "disabled"; 676 }; 677 678 i2c1: i2c@fcfee400 { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 682 reg = <0xfcfee400 0x44>; 683 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, 685 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, 686 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 691 interrupt-names = "tei", "ri", "ti", "spi", "sti", 692 "naki", "ali", "tmoi"; 693 clocks = <&mstp9_clks R7S72100_CLK_I2C1>; 694 clock-frequency = <100000>; 695 power-domains = <&cpg_clocks>; 696 status = "disabled"; 697 }; 698 699 i2c2: i2c@fcfee800 { 700 #address-cells = <1>; 701 #size-cells = <0>; 702 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 703 reg = <0xfcfee800 0x44>; 704 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, 706 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, 707 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 712 interrupt-names = "tei", "ri", "ti", "spi", "sti", 713 "naki", "ali", "tmoi"; 714 clocks = <&mstp9_clks R7S72100_CLK_I2C2>; 715 clock-frequency = <100000>; 716 power-domains = <&cpg_clocks>; 717 status = "disabled"; 718 }; 719 720 i2c3: i2c@fcfeec00 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 724 reg = <0xfcfeec00 0x44>; 725 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, 727 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, 728 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 733 interrupt-names = "tei", "ri", "ti", "spi", "sti", 734 "naki", "ali", "tmoi"; 735 clocks = <&mstp9_clks R7S72100_CLK_I2C3>; 736 clock-frequency = <100000>; 737 power-domains = <&cpg_clocks>; 738 status = "disabled"; 739 }; 740 741 irqc: interrupt-controller@fcfef800 { 742 compatible = "renesas,r7s72100-irqc", 743 "renesas,rza1-irqc"; 744 #interrupt-cells = <2>; 745 #address-cells = <0>; 746 interrupt-controller; 747 reg = <0xfcfef800 0x6>; 748 interrupt-map = 749 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 750 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 751 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 752 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 753 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 754 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 755 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 756 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 757 interrupt-map-mask = <7 0>; 758 }; 759 760 mtu2: timer@fcff0000 { 761 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; 762 reg = <0xfcff0000 0x400>; 763 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 764 interrupt-names = "tgi0a"; 765 clocks = <&mstp3_clks R7S72100_CLK_MTU2>; 766 clock-names = "fck"; 767 power-domains = <&cpg_clocks>; 768 status = "disabled"; 769 }; 770 771 rtc: rtc@fcff1000 { 772 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; 773 reg = <0xfcff1000 0x2e>; 774 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "alarm", "period", "carry"; 778 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, 779 <&rtc_x3_clk>, <&extal_clk>; 780 clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; 781 power-domains = <&cpg_clocks>; 782 status = "disabled"; 783 }; 784 }; 785 786 usb_x1_clk: usb_x1 { 787 #clock-cells = <0>; 788 compatible = "fixed-clock"; 789 /* If clk present, value must be set by board */ 790 clock-frequency = <0>; 791 }; 792}; 793