1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 5#include <dt-bindings/clock/qcom,gcc-msm8974.h> 6#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interconnect/qcom,msm8974.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8974.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 interrupt-parent = <&intc>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo_board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 }; 27 28 sleep_clk: sleep_clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32768>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 39 40 cpu0: cpu@0 { 41 compatible = "qcom,krait"; 42 enable-method = "qcom,kpss-acc-v2"; 43 device_type = "cpu"; 44 reg = <0>; 45 next-level-cache = <&l2>; 46 qcom,acc = <&acc0>; 47 qcom,saw = <&saw0>; 48 cpu-idle-states = <&cpu_spc>; 49 }; 50 51 cpu1: cpu@1 { 52 compatible = "qcom,krait"; 53 enable-method = "qcom,kpss-acc-v2"; 54 device_type = "cpu"; 55 reg = <1>; 56 next-level-cache = <&l2>; 57 qcom,acc = <&acc1>; 58 qcom,saw = <&saw1>; 59 cpu-idle-states = <&cpu_spc>; 60 }; 61 62 cpu2: cpu@2 { 63 compatible = "qcom,krait"; 64 enable-method = "qcom,kpss-acc-v2"; 65 device_type = "cpu"; 66 reg = <2>; 67 next-level-cache = <&l2>; 68 qcom,acc = <&acc2>; 69 qcom,saw = <&saw2>; 70 cpu-idle-states = <&cpu_spc>; 71 }; 72 73 cpu3: cpu@3 { 74 compatible = "qcom,krait"; 75 enable-method = "qcom,kpss-acc-v2"; 76 device_type = "cpu"; 77 reg = <3>; 78 next-level-cache = <&l2>; 79 qcom,acc = <&acc3>; 80 qcom,saw = <&saw3>; 81 cpu-idle-states = <&cpu_spc>; 82 }; 83 84 l2: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 cache-unified; 88 qcom,saw = <&saw_l2>; 89 }; 90 91 idle-states { 92 cpu_spc: cpu-spc { 93 compatible = "qcom,idle-state-spc", 94 "arm,idle-state"; 95 entry-latency-us = <150>; 96 exit-latency-us = <200>; 97 min-residency-us = <2000>; 98 }; 99 }; 100 }; 101 102 firmware { 103 scm { 104 compatible = "qcom,scm-msm8974", "qcom,scm"; 105 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 106 clock-names = "core", "bus", "iface"; 107 }; 108 }; 109 110 memory@0 { 111 device_type = "memory"; 112 reg = <0x0 0x0>; 113 }; 114 115 pmu { 116 compatible = "qcom,krait-pmu"; 117 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 118 }; 119 120 rpm: remoteproc { 121 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; 122 123 master-stats { 124 compatible = "qcom,rpm-master-stats"; 125 qcom,rpm-msg-ram = <&apss_master_stats>, 126 <&mpss_master_stats>, 127 <&lpss_master_stats>, 128 <&pronto_master_stats>; 129 qcom,master-names = "APSS", 130 "MPSS", 131 "LPSS", 132 "PRONTO"; 133 }; 134 135 smd-edge { 136 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 137 mboxes = <&apcs 0>; 138 qcom,smd-edge = <15>; 139 140 rpm_requests: rpm-requests { 141 compatible = "qcom,rpm-msm8974", "qcom,smd-rpm"; 142 qcom,smd-channels = "rpm_requests"; 143 144 rpmcc: clock-controller { 145 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 146 #clock-cells = <1>; 147 clocks = <&xo_board>; 148 clock-names = "xo"; 149 }; 150 151 rpmpd: power-controller { 152 compatible = "qcom,msm8974-rpmpd"; 153 #power-domain-cells = <1>; 154 operating-points-v2 = <&rpmpd_opp_table>; 155 156 rpmpd_opp_table: opp-table { 157 compatible = "operating-points-v2"; 158 159 rpmpd_opp_ret: opp1 { 160 opp-level = <1>; 161 }; 162 163 rpmpd_opp_svs_krait: opp2 { 164 opp-level = <2>; 165 }; 166 167 rpmpd_opp_svs_soc: opp3 { 168 opp-level = <3>; 169 }; 170 171 rpmpd_opp_nom: opp4 { 172 opp-level = <4>; 173 }; 174 175 rpmpd_opp_turbo: opp5 { 176 opp-level = <5>; 177 }; 178 179 rpmpd_opp_super_turbo: opp6 { 180 opp-level = <6>; 181 }; 182 }; 183 }; 184 }; 185 }; 186 }; 187 188 reserved_memory: reserved-memory { 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges; 192 193 mpss_region: mpss@8000000 { 194 reg = <0x08000000 0x5100000>; 195 no-map; 196 }; 197 198 mba_region: mba@d100000 { 199 reg = <0x0d100000 0x100000>; 200 no-map; 201 }; 202 203 wcnss_region: wcnss@d200000 { 204 reg = <0x0d200000 0xa00000>; 205 no-map; 206 }; 207 208 adsp_region: adsp@dc00000 { 209 reg = <0x0dc00000 0x1900000>; 210 no-map; 211 }; 212 213 venus_region: memory@f500000 { 214 reg = <0x0f500000 0x500000>; 215 no-map; 216 }; 217 218 smem_region: smem@fa00000 { 219 reg = <0xfa00000 0x200000>; 220 no-map; 221 }; 222 223 tz_region: memory@fc00000 { 224 reg = <0x0fc00000 0x160000>; 225 no-map; 226 }; 227 228 rfsa_mem: memory@fd60000 { 229 reg = <0x0fd60000 0x20000>; 230 no-map; 231 }; 232 233 rmtfs@fd80000 { 234 compatible = "qcom,rmtfs-mem"; 235 reg = <0x0fd80000 0x180000>; 236 no-map; 237 238 qcom,client-id = <1>; 239 }; 240 }; 241 242 smem { 243 compatible = "qcom,smem"; 244 245 memory-region = <&smem_region>; 246 qcom,rpm-msg-ram = <&rpm_msg_ram>; 247 248 hwlocks = <&tcsr_mutex 3>; 249 }; 250 251 smp2p-adsp { 252 compatible = "qcom,smp2p"; 253 qcom,smem = <443>, <429>; 254 255 interrupt-parent = <&intc>; 256 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 257 258 mboxes = <&apcs 10>; 259 260 qcom,local-pid = <0>; 261 qcom,remote-pid = <2>; 262 263 adsp_smp2p_out: master-kernel { 264 qcom,entry-name = "master-kernel"; 265 #qcom,smem-state-cells = <1>; 266 }; 267 268 adsp_smp2p_in: slave-kernel { 269 qcom,entry-name = "slave-kernel"; 270 271 interrupt-controller; 272 #interrupt-cells = <2>; 273 }; 274 }; 275 276 smp2p-modem { 277 compatible = "qcom,smp2p"; 278 qcom,smem = <435>, <428>; 279 280 interrupt-parent = <&intc>; 281 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 282 283 mboxes = <&apcs 14>; 284 285 qcom,local-pid = <0>; 286 qcom,remote-pid = <1>; 287 288 modem_smp2p_out: master-kernel { 289 qcom,entry-name = "master-kernel"; 290 #qcom,smem-state-cells = <1>; 291 }; 292 293 modem_smp2p_in: slave-kernel { 294 qcom,entry-name = "slave-kernel"; 295 296 interrupt-controller; 297 #interrupt-cells = <2>; 298 }; 299 }; 300 301 smp2p-wcnss { 302 compatible = "qcom,smp2p"; 303 qcom,smem = <451>, <431>; 304 305 interrupt-parent = <&intc>; 306 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 307 308 mboxes = <&apcs 18>; 309 310 qcom,local-pid = <0>; 311 qcom,remote-pid = <4>; 312 313 wcnss_smp2p_out: master-kernel { 314 qcom,entry-name = "master-kernel"; 315 316 #qcom,smem-state-cells = <1>; 317 }; 318 319 wcnss_smp2p_in: slave-kernel { 320 qcom,entry-name = "slave-kernel"; 321 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 }; 325 }; 326 327 smsm { 328 compatible = "qcom,smsm"; 329 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; 334 335 apps_smsm: apps@0 { 336 reg = <0>; 337 338 #qcom,smem-state-cells = <1>; 339 }; 340 341 modem_smsm: modem@1 { 342 reg = <1>; 343 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 344 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 }; 348 349 adsp_smsm: adsp@2 { 350 reg = <2>; 351 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 352 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 }; 356 357 wcnss_smsm: wcnss@7 { 358 reg = <7>; 359 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 360 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 }; 364 }; 365 366 soc: soc { 367 #address-cells = <1>; 368 #size-cells = <1>; 369 ranges; 370 compatible = "simple-bus"; 371 372 intc: interrupt-controller@f9000000 { 373 compatible = "qcom,msm-qgic2"; 374 interrupt-controller; 375 #interrupt-cells = <3>; 376 reg = <0xf9000000 0x1000>, 377 <0xf9002000 0x1000>; 378 }; 379 380 apcs: mailbox@f9011000 { 381 compatible = "qcom,msm8974-apcs-kpss-global", 382 "qcom,msm8994-apcs-kpss-global", "syscon"; 383 reg = <0xf9011000 0x1000>; 384 #mbox-cells = <1>; 385 }; 386 387 saw_l2: power-manager@f9012000 { 388 compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; 389 reg = <0xf9012000 0x1000>; 390 }; 391 392 watchdog@f9017000 { 393 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt"; 394 reg = <0xf9017000 0x1000>; 395 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 396 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 397 clocks = <&sleep_clk>; 398 }; 399 400 timer@f9020000 { 401 #address-cells = <1>; 402 #size-cells = <1>; 403 ranges; 404 compatible = "arm,armv7-timer-mem"; 405 reg = <0xf9020000 0x1000>; 406 clock-frequency = <19200000>; 407 408 frame@f9021000 { 409 frame-number = <0>; 410 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 412 reg = <0xf9021000 0x1000>, 413 <0xf9022000 0x1000>; 414 }; 415 416 frame@f9023000 { 417 frame-number = <1>; 418 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 419 reg = <0xf9023000 0x1000>; 420 status = "disabled"; 421 }; 422 423 frame@f9024000 { 424 frame-number = <2>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 reg = <0xf9024000 0x1000>; 427 status = "disabled"; 428 }; 429 430 frame@f9025000 { 431 frame-number = <3>; 432 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 433 reg = <0xf9025000 0x1000>; 434 status = "disabled"; 435 }; 436 437 frame@f9026000 { 438 frame-number = <4>; 439 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 440 reg = <0xf9026000 0x1000>; 441 status = "disabled"; 442 }; 443 444 frame@f9027000 { 445 frame-number = <5>; 446 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 447 reg = <0xf9027000 0x1000>; 448 status = "disabled"; 449 }; 450 451 frame@f9028000 { 452 frame-number = <6>; 453 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 454 reg = <0xf9028000 0x1000>; 455 status = "disabled"; 456 }; 457 }; 458 459 acc0: power-manager@f9088000 { 460 compatible = "qcom,kpss-acc-v2"; 461 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 462 }; 463 464 saw0: power-manager@f9089000 { 465 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 466 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 467 }; 468 469 acc1: power-manager@f9098000 { 470 compatible = "qcom,kpss-acc-v2"; 471 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 472 }; 473 474 saw1: power-manager@f9099000 { 475 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 476 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 477 }; 478 479 acc2: power-manager@f90a8000 { 480 compatible = "qcom,kpss-acc-v2"; 481 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 482 }; 483 484 saw2: power-manager@f90a9000 { 485 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 486 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 487 }; 488 489 acc3: power-manager@f90b8000 { 490 compatible = "qcom,kpss-acc-v2"; 491 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 492 }; 493 494 saw3: power-manager@f90b9000 { 495 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 496 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 497 }; 498 499 sdhc_1: mmc@f9824900 { 500 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 501 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 502 reg-names = "hc", "core"; 503 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "hc_irq", "pwr_irq"; 506 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 507 <&gcc GCC_SDCC1_APPS_CLK>, 508 <&xo_board>; 509 clock-names = "iface", "core", "xo"; 510 bus-width = <8>; 511 non-removable; 512 513 status = "disabled"; 514 }; 515 516 sdhc_3: mmc@f9864900 { 517 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 518 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 519 reg-names = "hc", "core"; 520 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "hc_irq", "pwr_irq"; 523 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 524 <&gcc GCC_SDCC3_APPS_CLK>, 525 <&xo_board>; 526 clock-names = "iface", "core", "xo"; 527 bus-width = <4>; 528 529 #address-cells = <1>; 530 #size-cells = <0>; 531 532 status = "disabled"; 533 }; 534 535 sdhc_2: mmc@f98a4900 { 536 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 537 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 538 reg-names = "hc", "core"; 539 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 541 interrupt-names = "hc_irq", "pwr_irq"; 542 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 543 <&gcc GCC_SDCC2_APPS_CLK>, 544 <&xo_board>; 545 clock-names = "iface", "core", "xo"; 546 bus-width = <4>; 547 548 #address-cells = <1>; 549 #size-cells = <0>; 550 551 status = "disabled"; 552 }; 553 554 blsp1_uart1: serial@f991d000 { 555 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 556 reg = <0xf991d000 0x1000>; 557 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 559 clock-names = "core", "iface"; 560 status = "disabled"; 561 }; 562 563 blsp1_uart2: serial@f991e000 { 564 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 565 reg = <0xf991e000 0x1000>; 566 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 568 clock-names = "core", "iface"; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&blsp1_uart2_default>; 571 status = "disabled"; 572 }; 573 574 blsp1_i2c1: i2c@f9923000 { 575 status = "disabled"; 576 compatible = "qcom,i2c-qup-v2.1.1"; 577 reg = <0xf9923000 0x1000>; 578 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 580 clock-names = "core", "iface"; 581 pinctrl-names = "default", "sleep"; 582 pinctrl-0 = <&blsp1_i2c1_default>; 583 pinctrl-1 = <&blsp1_i2c1_sleep>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 }; 587 588 blsp1_i2c2: i2c@f9924000 { 589 status = "disabled"; 590 compatible = "qcom,i2c-qup-v2.1.1"; 591 reg = <0xf9924000 0x1000>; 592 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 594 clock-names = "core", "iface"; 595 pinctrl-names = "default", "sleep"; 596 pinctrl-0 = <&blsp1_i2c2_default>; 597 pinctrl-1 = <&blsp1_i2c2_sleep>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 }; 601 602 blsp1_i2c3: i2c@f9925000 { 603 status = "disabled"; 604 compatible = "qcom,i2c-qup-v2.1.1"; 605 reg = <0xf9925000 0x1000>; 606 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 608 clock-names = "core", "iface"; 609 pinctrl-names = "default", "sleep"; 610 pinctrl-0 = <&blsp1_i2c3_default>; 611 pinctrl-1 = <&blsp1_i2c3_sleep>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 }; 615 616 blsp1_i2c6: i2c@f9928000 { 617 status = "disabled"; 618 compatible = "qcom,i2c-qup-v2.1.1"; 619 reg = <0xf9928000 0x1000>; 620 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 622 clock-names = "core", "iface"; 623 pinctrl-names = "default", "sleep"; 624 pinctrl-0 = <&blsp1_i2c6_default>; 625 pinctrl-1 = <&blsp1_i2c6_sleep>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 }; 629 630 blsp2_dma: dma-controller@f9944000 { 631 compatible = "qcom,bam-v1.4.0"; 632 reg = <0xf9944000 0x19000>; 633 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 635 clock-names = "bam_clk"; 636 #dma-cells = <1>; 637 qcom,ee = <0>; 638 }; 639 640 blsp2_uart1: serial@f995d000 { 641 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 642 reg = <0xf995d000 0x1000>; 643 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 645 clock-names = "core", "iface"; 646 pinctrl-names = "default", "sleep"; 647 pinctrl-0 = <&blsp2_uart1_default>; 648 pinctrl-1 = <&blsp2_uart1_sleep>; 649 status = "disabled"; 650 }; 651 652 blsp2_uart2: serial@f995e000 { 653 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 654 reg = <0xf995e000 0x1000>; 655 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 657 clock-names = "core", "iface"; 658 status = "disabled"; 659 }; 660 661 blsp2_uart4: serial@f9960000 { 662 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 663 reg = <0xf9960000 0x1000>; 664 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 666 clock-names = "core", "iface"; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&blsp2_uart4_default>; 669 status = "disabled"; 670 }; 671 672 blsp2_i2c2: i2c@f9964000 { 673 status = "disabled"; 674 compatible = "qcom,i2c-qup-v2.1.1"; 675 reg = <0xf9964000 0x1000>; 676 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 678 clock-names = "core", "iface"; 679 pinctrl-names = "default", "sleep"; 680 pinctrl-0 = <&blsp2_i2c2_default>; 681 pinctrl-1 = <&blsp2_i2c2_sleep>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 }; 685 686 blsp2_i2c5: i2c@f9967000 { 687 status = "disabled"; 688 compatible = "qcom,i2c-qup-v2.1.1"; 689 reg = <0xf9967000 0x1000>; 690 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 692 clock-names = "core", "iface"; 693 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 694 dma-names = "tx", "rx"; 695 pinctrl-names = "default", "sleep"; 696 pinctrl-0 = <&blsp2_i2c5_default>; 697 pinctrl-1 = <&blsp2_i2c5_sleep>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 }; 701 702 blsp2_i2c6: i2c@f9968000 { 703 status = "disabled"; 704 compatible = "qcom,i2c-qup-v2.1.1"; 705 reg = <0xf9968000 0x1000>; 706 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 708 clock-names = "core", "iface"; 709 pinctrl-names = "default", "sleep"; 710 pinctrl-0 = <&blsp2_i2c6_default>; 711 pinctrl-1 = <&blsp2_i2c6_sleep>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 }; 715 716 usb: usb@f9a55000 { 717 compatible = "qcom,ci-hdrc"; 718 reg = <0xf9a55000 0x200>, 719 <0xf9a55200 0x200>; 720 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 722 <&gcc GCC_USB_HS_SYSTEM_CLK>; 723 clock-names = "iface", "core"; 724 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 725 assigned-clock-rates = <75000000>; 726 resets = <&gcc GCC_USB_HS_BCR>; 727 reset-names = "core"; 728 phy_type = "ulpi"; 729 dr_mode = "otg"; 730 ahb-burst-config = <0>; 731 phy-names = "usb-phy"; 732 status = "disabled"; 733 #reset-cells = <1>; 734 735 ulpi { 736 usb_hs1_phy: phy-0 { 737 compatible = "qcom,usb-hs-phy-msm8974", 738 "qcom,usb-hs-phy"; 739 #phy-cells = <0>; 740 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 741 clock-names = "ref", "sleep"; 742 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 743 reset-names = "phy", "por"; 744 status = "disabled"; 745 }; 746 747 usb_hs2_phy: phy-1 { 748 compatible = "qcom,usb-hs-phy-msm8974", 749 "qcom,usb-hs-phy"; 750 #phy-cells = <0>; 751 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 752 clock-names = "ref", "sleep"; 753 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; 754 reset-names = "phy", "por"; 755 status = "disabled"; 756 }; 757 }; 758 }; 759 760 rng@f9bff000 { 761 compatible = "qcom,prng"; 762 reg = <0xf9bff000 0x200>; 763 clocks = <&gcc GCC_PRNG_AHB_CLK>; 764 clock-names = "core"; 765 }; 766 767 pronto: remoteproc@fb204000 { 768 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 769 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 770 reg-names = "ccu", "dxe", "pmu"; 771 772 memory-region = <&wcnss_region>; 773 774 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 775 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 776 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 777 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 778 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 779 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 780 781 power-domains = <&rpmpd MSM8974_VDDCX>; 782 power-domain-names = "cx"; 783 784 qcom,smem-states = <&wcnss_smp2p_out 0>; 785 qcom,smem-state-names = "stop"; 786 787 status = "disabled"; 788 789 iris { 790 compatible = "qcom,wcn3680"; 791 792 clocks = <&rpmcc RPM_SMD_CXO_A2>; 793 clock-names = "xo"; 794 }; 795 796 smd-edge { 797 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 798 799 mboxes = <&apcs 17>; 800 qcom,smd-edge = <6>; 801 802 wcnss { 803 compatible = "qcom,wcnss"; 804 qcom,smd-channels = "WCNSS_CTRL"; 805 status = "disabled"; 806 807 qcom,mmio = <&pronto>; 808 809 bluetooth { 810 compatible = "qcom,wcnss-bt"; 811 }; 812 813 wifi { 814 compatible = "qcom,wcnss-wlan"; 815 816 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 817 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 818 interrupt-names = "tx", "rx"; 819 820 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 821 qcom,smem-state-names = "tx-enable", 822 "tx-rings-empty"; 823 }; 824 }; 825 }; 826 }; 827 828 sram@fc190000 { 829 compatible = "qcom,msm8974-rpm-stats"; 830 reg = <0xfc190000 0x10000>; 831 }; 832 833 etf@fc307000 { 834 compatible = "arm,coresight-tmc", "arm,primecell"; 835 reg = <0xfc307000 0x1000>; 836 837 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 838 clock-names = "apb_pclk", "atclk"; 839 840 out-ports { 841 port { 842 etf_out: endpoint { 843 remote-endpoint = <&replicator_in>; 844 }; 845 }; 846 }; 847 848 in-ports { 849 port { 850 etf_in: endpoint { 851 remote-endpoint = <&merger_out>; 852 }; 853 }; 854 }; 855 }; 856 857 tpiu@fc318000 { 858 compatible = "arm,coresight-tpiu", "arm,primecell"; 859 reg = <0xfc318000 0x1000>; 860 861 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 862 clock-names = "apb_pclk", "atclk"; 863 864 in-ports { 865 port { 866 tpiu_in: endpoint { 867 remote-endpoint = <&replicator_out1>; 868 }; 869 }; 870 }; 871 }; 872 873 funnel@fc31a000 { 874 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 875 reg = <0xfc31a000 0x1000>; 876 877 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 878 clock-names = "apb_pclk", "atclk"; 879 880 in-ports { 881 #address-cells = <1>; 882 #size-cells = <0>; 883 884 /* 885 * Not described input ports: 886 * 0 - not-connected 887 * 1 - connected trought funnel to Multimedia CPU 888 * 2 - connected to Wireless CPU 889 * 3 - not-connected 890 * 4 - not-connected 891 * 6 - not-connected 892 * 7 - connected to STM 893 */ 894 port@5 { 895 reg = <5>; 896 funnel1_in5: endpoint { 897 remote-endpoint = <&kpss_out>; 898 }; 899 }; 900 }; 901 902 out-ports { 903 port { 904 funnel1_out: endpoint { 905 remote-endpoint = <&merger_in1>; 906 }; 907 }; 908 }; 909 }; 910 911 funnel@fc31b000 { 912 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 913 reg = <0xfc31b000 0x1000>; 914 915 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 916 clock-names = "apb_pclk", "atclk"; 917 918 in-ports { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 922 /* 923 * Not described input ports: 924 * 0 - connected trought funnel to Audio, Modem and 925 * Resource and Power Manager CPU's 926 * 2...7 - not-connected 927 */ 928 port@1 { 929 reg = <1>; 930 merger_in1: endpoint { 931 remote-endpoint = <&funnel1_out>; 932 }; 933 }; 934 }; 935 936 out-ports { 937 port { 938 merger_out: endpoint { 939 remote-endpoint = <&etf_in>; 940 }; 941 }; 942 }; 943 }; 944 945 replicator@fc31c000 { 946 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 947 reg = <0xfc31c000 0x1000>; 948 949 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 950 clock-names = "apb_pclk", "atclk"; 951 952 out-ports { 953 #address-cells = <1>; 954 #size-cells = <0>; 955 956 port@0 { 957 reg = <0>; 958 replicator_out0: endpoint { 959 remote-endpoint = <&etr_in>; 960 }; 961 }; 962 port@1 { 963 reg = <1>; 964 replicator_out1: endpoint { 965 remote-endpoint = <&tpiu_in>; 966 }; 967 }; 968 }; 969 970 in-ports { 971 port { 972 replicator_in: endpoint { 973 remote-endpoint = <&etf_out>; 974 }; 975 }; 976 }; 977 }; 978 979 etr@fc322000 { 980 compatible = "arm,coresight-tmc", "arm,primecell"; 981 reg = <0xfc322000 0x1000>; 982 983 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 984 clock-names = "apb_pclk", "atclk"; 985 986 in-ports { 987 port { 988 etr_in: endpoint { 989 remote-endpoint = <&replicator_out0>; 990 }; 991 }; 992 }; 993 }; 994 995 etm@fc33c000 { 996 compatible = "arm,coresight-etm4x", "arm,primecell"; 997 reg = <0xfc33c000 0x1000>; 998 999 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1000 clock-names = "apb_pclk", "atclk"; 1001 1002 cpu = <&cpu0>; 1003 1004 out-ports { 1005 port { 1006 etm0_out: endpoint { 1007 remote-endpoint = <&kpss_in0>; 1008 }; 1009 }; 1010 }; 1011 }; 1012 1013 etm@fc33d000 { 1014 compatible = "arm,coresight-etm4x", "arm,primecell"; 1015 reg = <0xfc33d000 0x1000>; 1016 1017 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1018 clock-names = "apb_pclk", "atclk"; 1019 1020 cpu = <&cpu1>; 1021 1022 out-ports { 1023 port { 1024 etm1_out: endpoint { 1025 remote-endpoint = <&kpss_in1>; 1026 }; 1027 }; 1028 }; 1029 }; 1030 1031 etm@fc33e000 { 1032 compatible = "arm,coresight-etm4x", "arm,primecell"; 1033 reg = <0xfc33e000 0x1000>; 1034 1035 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1036 clock-names = "apb_pclk", "atclk"; 1037 1038 cpu = <&cpu2>; 1039 1040 out-ports { 1041 port { 1042 etm2_out: endpoint { 1043 remote-endpoint = <&kpss_in2>; 1044 }; 1045 }; 1046 }; 1047 }; 1048 1049 etm@fc33f000 { 1050 compatible = "arm,coresight-etm4x", "arm,primecell"; 1051 reg = <0xfc33f000 0x1000>; 1052 1053 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1054 clock-names = "apb_pclk", "atclk"; 1055 1056 cpu = <&cpu3>; 1057 1058 out-ports { 1059 port { 1060 etm3_out: endpoint { 1061 remote-endpoint = <&kpss_in3>; 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 /* KPSS funnel, only 4 inputs are used */ 1068 funnel@fc345000 { 1069 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1070 reg = <0xfc345000 0x1000>; 1071 1072 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1073 clock-names = "apb_pclk", "atclk"; 1074 1075 in-ports { 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 1079 port@0 { 1080 reg = <0>; 1081 kpss_in0: endpoint { 1082 remote-endpoint = <&etm0_out>; 1083 }; 1084 }; 1085 port@1 { 1086 reg = <1>; 1087 kpss_in1: endpoint { 1088 remote-endpoint = <&etm1_out>; 1089 }; 1090 }; 1091 port@2 { 1092 reg = <2>; 1093 kpss_in2: endpoint { 1094 remote-endpoint = <&etm2_out>; 1095 }; 1096 }; 1097 port@3 { 1098 reg = <3>; 1099 kpss_in3: endpoint { 1100 remote-endpoint = <&etm3_out>; 1101 }; 1102 }; 1103 }; 1104 1105 out-ports { 1106 port { 1107 kpss_out: endpoint { 1108 remote-endpoint = <&funnel1_in5>; 1109 }; 1110 }; 1111 }; 1112 }; 1113 1114 bimc: interconnect@fc380000 { 1115 reg = <0xfc380000 0x6a000>; 1116 compatible = "qcom,msm8974-bimc"; 1117 #interconnect-cells = <1>; 1118 }; 1119 1120 gcc: clock-controller@fc400000 { 1121 compatible = "qcom,gcc-msm8974"; 1122 #clock-cells = <1>; 1123 #reset-cells = <1>; 1124 #power-domain-cells = <1>; 1125 reg = <0xfc400000 0x4000>; 1126 1127 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1128 <&sleep_clk>; 1129 clock-names = "xo", 1130 "sleep_clk"; 1131 }; 1132 1133 rpm_msg_ram: sram@fc428000 { 1134 compatible = "qcom,rpm-msg-ram"; 1135 reg = <0xfc428000 0x4000>; 1136 1137 #address-cells = <1>; 1138 #size-cells = <1>; 1139 ranges = <0 0xfc428000 0x4000>; 1140 1141 apss_master_stats: sram@150 { 1142 reg = <0x150 0x14>; 1143 }; 1144 1145 mpss_master_stats: sram@b50 { 1146 reg = <0xb50 0x14>; 1147 }; 1148 1149 lpss_master_stats: sram@1550 { 1150 reg = <0x1550 0x14>; 1151 }; 1152 1153 pronto_master_stats: sram@1f50 { 1154 reg = <0x1f50 0x14>; 1155 }; 1156 }; 1157 1158 snoc: interconnect@fc460000 { 1159 reg = <0xfc460000 0x4000>; 1160 compatible = "qcom,msm8974-snoc"; 1161 #interconnect-cells = <1>; 1162 }; 1163 1164 pnoc: interconnect@fc468000 { 1165 reg = <0xfc468000 0x4000>; 1166 compatible = "qcom,msm8974-pnoc"; 1167 #interconnect-cells = <1>; 1168 }; 1169 1170 ocmemnoc: interconnect@fc470000 { 1171 reg = <0xfc470000 0x4000>; 1172 compatible = "qcom,msm8974-ocmemnoc"; 1173 #interconnect-cells = <1>; 1174 }; 1175 1176 mmssnoc: interconnect@fc478000 { 1177 reg = <0xfc478000 0x4000>; 1178 compatible = "qcom,msm8974-mmssnoc"; 1179 #interconnect-cells = <1>; 1180 clocks = <&mmcc MMSS_S0_AXI_CLK>; 1181 clock-names = "bus"; 1182 }; 1183 1184 cnoc: interconnect@fc480000 { 1185 reg = <0xfc480000 0x4000>; 1186 compatible = "qcom,msm8974-cnoc"; 1187 #interconnect-cells = <1>; 1188 }; 1189 1190 tsens: thermal-sensor@fc4a9000 { 1191 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; 1192 reg = <0xfc4a9000 0x1000>, /* TM */ 1193 <0xfc4a8000 0x1000>; /* SROT */ 1194 nvmem-cells = <&tsens_mode>, 1195 <&tsens_base1>, <&tsens_base2>, 1196 <&tsens_use_backup>, 1197 <&tsens_mode_backup>, 1198 <&tsens_base1_backup>, <&tsens_base2_backup>, 1199 <&tsens_s0_p1>, <&tsens_s0_p2>, 1200 <&tsens_s1_p1>, <&tsens_s1_p2>, 1201 <&tsens_s2_p1>, <&tsens_s2_p2>, 1202 <&tsens_s3_p1>, <&tsens_s3_p2>, 1203 <&tsens_s4_p1>, <&tsens_s4_p2>, 1204 <&tsens_s5_p1>, <&tsens_s5_p2>, 1205 <&tsens_s6_p1>, <&tsens_s6_p2>, 1206 <&tsens_s7_p1>, <&tsens_s7_p2>, 1207 <&tsens_s8_p1>, <&tsens_s8_p2>, 1208 <&tsens_s9_p1>, <&tsens_s9_p2>, 1209 <&tsens_s10_p1>, <&tsens_s10_p2>, 1210 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, 1211 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, 1212 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, 1213 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, 1214 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, 1215 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, 1216 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, 1217 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, 1218 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, 1219 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, 1220 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; 1221 nvmem-cell-names = "mode", 1222 "base1", "base2", 1223 "use_backup", 1224 "mode_backup", 1225 "base1_backup", "base2_backup", 1226 "s0_p1", "s0_p2", 1227 "s1_p1", "s1_p2", 1228 "s2_p1", "s2_p2", 1229 "s3_p1", "s3_p2", 1230 "s4_p1", "s4_p2", 1231 "s5_p1", "s5_p2", 1232 "s6_p1", "s6_p2", 1233 "s7_p1", "s7_p2", 1234 "s8_p1", "s8_p2", 1235 "s9_p1", "s9_p2", 1236 "s10_p1", "s10_p2", 1237 "s0_p1_backup", "s0_p2_backup", 1238 "s1_p1_backup", "s1_p2_backup", 1239 "s2_p1_backup", "s2_p2_backup", 1240 "s3_p1_backup", "s3_p2_backup", 1241 "s4_p1_backup", "s4_p2_backup", 1242 "s5_p1_backup", "s5_p2_backup", 1243 "s6_p1_backup", "s6_p2_backup", 1244 "s7_p1_backup", "s7_p2_backup", 1245 "s8_p1_backup", "s8_p2_backup", 1246 "s9_p1_backup", "s9_p2_backup", 1247 "s10_p1_backup", "s10_p2_backup"; 1248 #qcom,sensors = <11>; 1249 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1250 interrupt-names = "uplow"; 1251 #thermal-sensor-cells = <1>; 1252 }; 1253 1254 restart@fc4ab000 { 1255 compatible = "qcom,pshold"; 1256 reg = <0xfc4ab000 0x4>; 1257 }; 1258 1259 qfprom: efuse@fc4bc000 { 1260 compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 1261 reg = <0xfc4bc000 0x2100>; 1262 #address-cells = <1>; 1263 #size-cells = <1>; 1264 1265 tsens_base1: base1@d0 { 1266 reg = <0xd0 0x1>; 1267 bits = <0 8>; 1268 }; 1269 1270 tsens_s0_p1: s0-p1@d1 { 1271 reg = <0xd1 0x1>; 1272 bits = <0 6>; 1273 }; 1274 1275 tsens_s1_p1: s1-p1@d2 { 1276 reg = <0xd1 0x2>; 1277 bits = <6 6>; 1278 }; 1279 1280 tsens_s2_p1: s2-p1@d2 { 1281 reg = <0xd2 0x2>; 1282 bits = <4 6>; 1283 }; 1284 1285 tsens_s3_p1: s3-p1@d3 { 1286 reg = <0xd3 0x1>; 1287 bits = <2 6>; 1288 }; 1289 1290 tsens_s4_p1: s4-p1@d4 { 1291 reg = <0xd4 0x1>; 1292 bits = <0 6>; 1293 }; 1294 1295 tsens_s5_p1: s5-p1@d4 { 1296 reg = <0xd4 0x2>; 1297 bits = <6 6>; 1298 }; 1299 1300 tsens_s6_p1: s6-p1@d5 { 1301 reg = <0xd5 0x2>; 1302 bits = <4 6>; 1303 }; 1304 1305 tsens_s7_p1: s7-p1@d6 { 1306 reg = <0xd6 0x1>; 1307 bits = <2 6>; 1308 }; 1309 1310 tsens_s8_p1: s8-p1@d7 { 1311 reg = <0xd7 0x1>; 1312 bits = <0 6>; 1313 }; 1314 1315 tsens_mode: mode@d7 { 1316 reg = <0xd7 0x1>; 1317 bits = <6 2>; 1318 }; 1319 1320 tsens_s9_p1: s9-p1@d8 { 1321 reg = <0xd8 0x1>; 1322 bits = <0 6>; 1323 }; 1324 1325 tsens_s10_p1: s10-p1@d8 { 1326 reg = <0xd8 0x2>; 1327 bits = <6 6>; 1328 }; 1329 1330 tsens_base2: base2@d9 { 1331 reg = <0xd9 0x2>; 1332 bits = <4 8>; 1333 }; 1334 1335 tsens_s0_p2: s0-p2@da { 1336 reg = <0xda 0x2>; 1337 bits = <4 6>; 1338 }; 1339 1340 tsens_s1_p2: s1-p2@db { 1341 reg = <0xdb 0x1>; 1342 bits = <2 6>; 1343 }; 1344 1345 tsens_s2_p2: s2-p2@dc { 1346 reg = <0xdc 0x1>; 1347 bits = <0 6>; 1348 }; 1349 1350 tsens_s3_p2: s3-p2@dc { 1351 reg = <0xdc 0x2>; 1352 bits = <6 6>; 1353 }; 1354 1355 tsens_s4_p2: s4-p2@dd { 1356 reg = <0xdd 0x2>; 1357 bits = <4 6>; 1358 }; 1359 1360 tsens_s5_p2: s5-p2@de { 1361 reg = <0xde 0x2>; 1362 bits = <2 6>; 1363 }; 1364 1365 tsens_s6_p2: s6-p2@df { 1366 reg = <0xdf 0x1>; 1367 bits = <0 6>; 1368 }; 1369 1370 tsens_s7_p2: s7-p2@e0 { 1371 reg = <0xe0 0x1>; 1372 bits = <0 6>; 1373 }; 1374 1375 tsens_s8_p2: s8-p2@e0 { 1376 reg = <0xe0 0x2>; 1377 bits = <6 6>; 1378 }; 1379 1380 tsens_s9_p2: s9-p2@e1 { 1381 reg = <0xe1 0x2>; 1382 bits = <4 6>; 1383 }; 1384 1385 tsens_s10_p2: s10-p2@e2 { 1386 reg = <0xe2 0x2>; 1387 bits = <2 6>; 1388 }; 1389 1390 tsens_s5_p2_backup: s5-p2-backup@e3 { 1391 reg = <0xe3 0x2>; 1392 bits = <0 6>; 1393 }; 1394 1395 tsens_mode_backup: mode-backup@e3 { 1396 reg = <0xe3 0x1>; 1397 bits = <6 2>; 1398 }; 1399 1400 tsens_s6_p2_backup: s6-p2-backup@e4 { 1401 reg = <0xe4 0x1>; 1402 bits = <0 6>; 1403 }; 1404 1405 tsens_s7_p2_backup: s7-p2-backup@e4 { 1406 reg = <0xe4 0x2>; 1407 bits = <6 6>; 1408 }; 1409 1410 tsens_s8_p2_backup: s8-p2-backup@e5 { 1411 reg = <0xe5 0x2>; 1412 bits = <4 6>; 1413 }; 1414 1415 tsens_s9_p2_backup: s9-p2-backup@e6 { 1416 reg = <0xe6 0x2>; 1417 bits = <2 6>; 1418 }; 1419 1420 tsens_s10_p2_backup: s10-p2-backup@e7 { 1421 reg = <0xe7 0x1>; 1422 bits = <0 6>; 1423 }; 1424 1425 tsens_base1_backup: base1-backup@440 { 1426 reg = <0x440 0x1>; 1427 bits = <0 8>; 1428 }; 1429 1430 tsens_s0_p1_backup: s0-p1-backup@441 { 1431 reg = <0x441 0x1>; 1432 bits = <0 6>; 1433 }; 1434 1435 tsens_s1_p1_backup: s1-p1-backup@442 { 1436 reg = <0x441 0x2>; 1437 bits = <6 6>; 1438 }; 1439 1440 tsens_s2_p1_backup: s2-p1-backup@442 { 1441 reg = <0x442 0x2>; 1442 bits = <4 6>; 1443 }; 1444 1445 tsens_s3_p1_backup: s3-p1-backup@443 { 1446 reg = <0x443 0x1>; 1447 bits = <2 6>; 1448 }; 1449 1450 tsens_s4_p1_backup: s4-p1-backup@444 { 1451 reg = <0x444 0x1>; 1452 bits = <0 6>; 1453 }; 1454 1455 tsens_s5_p1_backup: s5-p1-backup@444 { 1456 reg = <0x444 0x2>; 1457 bits = <6 6>; 1458 }; 1459 1460 tsens_s6_p1_backup: s6-p1-backup@445 { 1461 reg = <0x445 0x2>; 1462 bits = <4 6>; 1463 }; 1464 1465 tsens_s7_p1_backup: s7-p1-backup@446 { 1466 reg = <0x446 0x1>; 1467 bits = <2 6>; 1468 }; 1469 1470 tsens_use_backup: use-backup@447 { 1471 reg = <0x447 0x1>; 1472 bits = <5 3>; 1473 }; 1474 1475 tsens_s8_p1_backup: s8-p1-backup@448 { 1476 reg = <0x448 0x1>; 1477 bits = <0 6>; 1478 }; 1479 1480 tsens_s9_p1_backup: s9-p1-backup@448 { 1481 reg = <0x448 0x2>; 1482 bits = <6 6>; 1483 }; 1484 1485 tsens_s10_p1_backup: s10-p1-backup@449 { 1486 reg = <0x449 0x2>; 1487 bits = <4 6>; 1488 }; 1489 1490 tsens_base2_backup: base2-backup@44a { 1491 reg = <0x44a 0x2>; 1492 bits = <2 8>; 1493 }; 1494 1495 tsens_s0_p2_backup: s0-p2-backup@44b { 1496 reg = <0x44b 0x3>; 1497 bits = <2 6>; 1498 }; 1499 1500 tsens_s1_p2_backup: s1-p2-backup@44c { 1501 reg = <0x44c 0x1>; 1502 bits = <0 6>; 1503 }; 1504 1505 tsens_s2_p2_backup: s2-p2-backup@44c { 1506 reg = <0x44c 0x2>; 1507 bits = <6 6>; 1508 }; 1509 1510 tsens_s3_p2_backup: s3-p2-backup@44d { 1511 reg = <0x44d 0x2>; 1512 bits = <4 6>; 1513 }; 1514 1515 tsens_s4_p2_backup: s4-p2-backup@44e { 1516 reg = <0x44e 0x1>; 1517 bits = <2 6>; 1518 }; 1519 }; 1520 1521 spmi_bus: spmi@fc4cf000 { 1522 compatible = "qcom,spmi-pmic-arb"; 1523 reg-names = "core", "intr", "cnfg"; 1524 reg = <0xfc4cf000 0x1000>, 1525 <0xfc4cb000 0x1000>, 1526 <0xfc4ca000 0x1000>; 1527 interrupt-names = "periph_irq"; 1528 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1529 qcom,ee = <0>; 1530 qcom,channel = <0>; 1531 #address-cells = <2>; 1532 #size-cells = <0>; 1533 interrupt-controller; 1534 #interrupt-cells = <4>; 1535 }; 1536 1537 bam_dmux_dma: dma-controller@fc834000 { 1538 compatible = "qcom,bam-v1.4.0"; 1539 reg = <0xfc834000 0x7000>; 1540 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1541 #dma-cells = <1>; 1542 qcom,ee = <0>; 1543 1544 num-channels = <6>; 1545 qcom,num-ees = <1>; 1546 qcom,powered-remotely; 1547 }; 1548 1549 remoteproc_mss: remoteproc@fc880000 { 1550 compatible = "qcom,msm8974-mss-pil"; 1551 reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 1552 reg-names = "qdsp6", "rmb"; 1553 1554 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1555 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1556 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1557 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1558 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1559 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1560 1561 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1562 <&gcc GCC_MSS_CFG_AHB_CLK>, 1563 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1564 <&xo_board>; 1565 clock-names = "iface", "bus", "mem", "xo"; 1566 1567 resets = <&gcc GCC_MSS_RESTART>; 1568 reset-names = "mss_restart"; 1569 1570 power-domains = <&rpmpd MSM8974_VDDCX>; 1571 power-domain-names = "cx"; 1572 1573 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; 1574 1575 qcom,smem-states = <&modem_smp2p_out 0>; 1576 qcom,smem-state-names = "stop"; 1577 1578 status = "disabled"; 1579 1580 mba { 1581 memory-region = <&mba_region>; 1582 }; 1583 1584 mpss { 1585 memory-region = <&mpss_region>; 1586 }; 1587 1588 bam_dmux: bam-dmux { 1589 compatible = "qcom,bam-dmux"; 1590 1591 interrupt-parent = <&modem_smsm>; 1592 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1593 interrupt-names = "pc", "pc-ack"; 1594 1595 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1596 qcom,smem-state-names = "pc", "pc-ack"; 1597 1598 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1599 dma-names = "tx", "rx"; 1600 }; 1601 1602 smd-edge { 1603 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1604 1605 mboxes = <&apcs 12>; 1606 qcom,smd-edge = <0>; 1607 1608 label = "modem"; 1609 }; 1610 }; 1611 1612 tcsr_mutex: hwlock@fd484000 { 1613 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; 1614 reg = <0xfd484000 0x2000>; 1615 #hwlock-cells = <1>; 1616 }; 1617 1618 tcsr: syscon@fd4a0000 { 1619 compatible = "qcom,tcsr-msm8974", "syscon"; 1620 reg = <0xfd4a0000 0x10000>; 1621 }; 1622 1623 tlmm: pinctrl@fd510000 { 1624 compatible = "qcom,msm8974-pinctrl"; 1625 reg = <0xfd510000 0x4000>; 1626 gpio-controller; 1627 gpio-ranges = <&tlmm 0 0 146>; 1628 #gpio-cells = <2>; 1629 interrupt-controller; 1630 #interrupt-cells = <2>; 1631 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1632 1633 sdc1_off: sdc1-off-state { 1634 clk-pins { 1635 pins = "sdc1_clk"; 1636 bias-disable; 1637 drive-strength = <2>; 1638 }; 1639 1640 cmd-pins { 1641 pins = "sdc1_cmd"; 1642 bias-pull-up; 1643 drive-strength = <2>; 1644 }; 1645 1646 data-pins { 1647 pins = "sdc1_data"; 1648 bias-pull-up; 1649 drive-strength = <2>; 1650 }; 1651 }; 1652 1653 sdc2_off: sdc2-off-state { 1654 clk-pins { 1655 pins = "sdc2_clk"; 1656 bias-disable; 1657 drive-strength = <2>; 1658 }; 1659 1660 cmd-pins { 1661 pins = "sdc2_cmd"; 1662 bias-pull-up; 1663 drive-strength = <2>; 1664 }; 1665 1666 data-pins { 1667 pins = "sdc2_data"; 1668 bias-pull-up; 1669 drive-strength = <2>; 1670 }; 1671 }; 1672 1673 blsp1_uart2_default: blsp1-uart2-default-state { 1674 rx-pins { 1675 pins = "gpio5"; 1676 function = "blsp_uart2"; 1677 drive-strength = <2>; 1678 bias-pull-up; 1679 }; 1680 1681 tx-pins { 1682 pins = "gpio4"; 1683 function = "blsp_uart2"; 1684 drive-strength = <4>; 1685 bias-disable; 1686 }; 1687 }; 1688 1689 blsp2_uart1_default: blsp2-uart1-default-state { 1690 tx-rts-pins { 1691 pins = "gpio41", "gpio44"; 1692 function = "blsp_uart7"; 1693 drive-strength = <2>; 1694 bias-disable; 1695 }; 1696 1697 rx-cts-pins { 1698 pins = "gpio42", "gpio43"; 1699 function = "blsp_uart7"; 1700 drive-strength = <2>; 1701 bias-pull-up; 1702 }; 1703 }; 1704 1705 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 1706 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1707 function = "gpio"; 1708 drive-strength = <2>; 1709 bias-pull-down; 1710 }; 1711 1712 blsp2_uart4_default: blsp2-uart4-default-state { 1713 tx-rts-pins { 1714 pins = "gpio53", "gpio56"; 1715 function = "blsp_uart10"; 1716 drive-strength = <2>; 1717 bias-disable; 1718 }; 1719 1720 rx-cts-pins { 1721 pins = "gpio54", "gpio55"; 1722 function = "blsp_uart10"; 1723 drive-strength = <2>; 1724 bias-pull-up; 1725 }; 1726 }; 1727 1728 blsp1_i2c1_default: blsp1-i2c1-default-state { 1729 pins = "gpio2", "gpio3"; 1730 function = "blsp_i2c1"; 1731 drive-strength = <2>; 1732 bias-disable; 1733 }; 1734 1735 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { 1736 pins = "gpio2", "gpio3"; 1737 function = "blsp_i2c1"; 1738 drive-strength = <2>; 1739 bias-pull-up; 1740 }; 1741 1742 blsp1_i2c2_default: blsp1-i2c2-default-state { 1743 pins = "gpio6", "gpio7"; 1744 function = "blsp_i2c2"; 1745 drive-strength = <2>; 1746 bias-disable; 1747 }; 1748 1749 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 1750 pins = "gpio6", "gpio7"; 1751 function = "blsp_i2c2"; 1752 drive-strength = <2>; 1753 bias-pull-up; 1754 }; 1755 1756 blsp1_i2c3_default: blsp1-i2c3-default-state { 1757 pins = "gpio10", "gpio11"; 1758 function = "blsp_i2c3"; 1759 drive-strength = <2>; 1760 bias-disable; 1761 }; 1762 1763 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1764 pins = "gpio10", "gpio11"; 1765 function = "blsp_i2c3"; 1766 drive-strength = <2>; 1767 bias-pull-up; 1768 }; 1769 1770 /* BLSP1_I2C4 info is missing */ 1771 1772 /* BLSP1_I2C5 info is missing */ 1773 1774 blsp1_i2c6_default: blsp1-i2c6-default-state { 1775 pins = "gpio29", "gpio30"; 1776 function = "blsp_i2c6"; 1777 drive-strength = <2>; 1778 bias-disable; 1779 }; 1780 1781 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1782 pins = "gpio29", "gpio30"; 1783 function = "blsp_i2c6"; 1784 drive-strength = <2>; 1785 bias-pull-up; 1786 }; 1787 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1788 1789 /* BLSP2_I2C1 info is missing */ 1790 1791 blsp2_i2c2_default: blsp2-i2c2-default-state { 1792 pins = "gpio47", "gpio48"; 1793 function = "blsp_i2c8"; 1794 drive-strength = <2>; 1795 bias-disable; 1796 }; 1797 1798 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1799 pins = "gpio47", "gpio48"; 1800 function = "blsp_i2c8"; 1801 drive-strength = <2>; 1802 bias-pull-up; 1803 }; 1804 1805 /* BLSP2_I2C3 info is missing */ 1806 1807 /* BLSP2_I2C4 info is missing */ 1808 1809 blsp2_i2c5_default: blsp2-i2c5-default-state { 1810 pins = "gpio83", "gpio84"; 1811 function = "blsp_i2c11"; 1812 drive-strength = <2>; 1813 bias-disable; 1814 }; 1815 1816 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1817 pins = "gpio83", "gpio84"; 1818 function = "blsp_i2c11"; 1819 drive-strength = <2>; 1820 bias-pull-up; 1821 }; 1822 1823 blsp2_i2c6_default: blsp2-i2c6-default-state { 1824 pins = "gpio87", "gpio88"; 1825 function = "blsp_i2c12"; 1826 drive-strength = <2>; 1827 bias-disable; 1828 }; 1829 1830 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1831 pins = "gpio87", "gpio88"; 1832 function = "blsp_i2c12"; 1833 drive-strength = <2>; 1834 bias-pull-up; 1835 }; 1836 1837 cci_default: cci-default-state { 1838 cci_i2c0_default: cci-i2c0-default-pins { 1839 pins = "gpio19", "gpio20"; 1840 function = "cci_i2c0"; 1841 drive-strength = <2>; 1842 bias-disable; 1843 }; 1844 1845 cci_i2c1_default: cci-i2c1-default-pins { 1846 pins = "gpio21", "gpio22"; 1847 function = "cci_i2c1"; 1848 drive-strength = <2>; 1849 bias-disable; 1850 }; 1851 }; 1852 1853 cci_sleep: cci-sleep-state { 1854 cci_i2c0_sleep: cci-i2c0-sleep-pins { 1855 pins = "gpio19", "gpio20"; 1856 function = "gpio"; 1857 drive-strength = <2>; 1858 bias-disable; 1859 }; 1860 1861 cci_i2c1_sleep: cci-i2c1-sleep-pins { 1862 pins = "gpio21", "gpio22"; 1863 function = "gpio"; 1864 drive-strength = <2>; 1865 bias-disable; 1866 }; 1867 }; 1868 1869 spi8_default: spi8_default-state { 1870 mosi-pins { 1871 pins = "gpio45"; 1872 function = "blsp_spi8"; 1873 }; 1874 miso-pins { 1875 pins = "gpio46"; 1876 function = "blsp_spi8"; 1877 }; 1878 cs-pins { 1879 pins = "gpio47"; 1880 function = "blsp_spi8"; 1881 }; 1882 clk-pins { 1883 pins = "gpio48"; 1884 function = "blsp_spi8"; 1885 }; 1886 }; 1887 }; 1888 1889 mmcc: clock-controller@fd8c0000 { 1890 compatible = "qcom,mmcc-msm8974"; 1891 #clock-cells = <1>; 1892 #reset-cells = <1>; 1893 #power-domain-cells = <1>; 1894 reg = <0xfd8c0000 0x6000>; 1895 clocks = <&xo_board>, 1896 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 1897 <&gcc GPLL0_VOTE>, 1898 <&gcc GPLL1_VOTE>, 1899 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1900 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1901 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1902 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 1903 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1904 <0>, 1905 <0>, 1906 <0>; 1907 clock-names = "xo", 1908 "mmss_gpll0_vote", 1909 "gpll0_vote", 1910 "gpll1_vote", 1911 "gfx3d_clk_src", 1912 "dsi0pll", 1913 "dsi0pllbyte", 1914 "dsi1pll", 1915 "dsi1pllbyte", 1916 "hdmipll", 1917 "edp_link_clk", 1918 "edp_vco_div"; 1919 }; 1920 1921 mdss: display-subsystem@fd900000 { 1922 compatible = "qcom,mdss"; 1923 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1924 reg-names = "mdss_phys", "vbif_phys"; 1925 1926 power-domains = <&mmcc MDSS_GDSC>; 1927 1928 clocks = <&mmcc MDSS_AHB_CLK>, 1929 <&mmcc MDSS_AXI_CLK>, 1930 <&mmcc MDSS_VSYNC_CLK>; 1931 clock-names = "iface", "bus", "vsync"; 1932 1933 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1934 1935 interrupt-controller; 1936 #interrupt-cells = <1>; 1937 1938 status = "disabled"; 1939 1940 #address-cells = <1>; 1941 #size-cells = <1>; 1942 ranges; 1943 1944 mdp: display-controller@fd900000 { 1945 compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; 1946 reg = <0xfd900100 0x22000>; 1947 reg-names = "mdp_phys"; 1948 1949 interrupt-parent = <&mdss>; 1950 interrupts = <0>; 1951 1952 clocks = <&mmcc MDSS_AHB_CLK>, 1953 <&mmcc MDSS_AXI_CLK>, 1954 <&mmcc MDSS_MDP_CLK>, 1955 <&mmcc MDSS_VSYNC_CLK>; 1956 clock-names = "iface", "bus", "core", "vsync"; 1957 1958 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1959 interconnect-names = "mdp0-mem"; 1960 1961 ports { 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 1965 port@0 { 1966 reg = <0>; 1967 mdp5_intf1_out: endpoint { 1968 remote-endpoint = <&mdss_dsi0_in>; 1969 }; 1970 }; 1971 1972 port@1 { 1973 reg = <1>; 1974 mdp5_intf2_out: endpoint { 1975 remote-endpoint = <&mdss_dsi1_in>; 1976 }; 1977 }; 1978 }; 1979 }; 1980 1981 mdss_dsi0: dsi@fd922800 { 1982 compatible = "qcom,msm8974-dsi-ctrl", 1983 "qcom,mdss-dsi-ctrl"; 1984 reg = <0xfd922800 0x1f8>; 1985 reg-names = "dsi_ctrl"; 1986 1987 interrupt-parent = <&mdss>; 1988 interrupts = <4>; 1989 1990 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1991 <&mmcc PCLK0_CLK_SRC>; 1992 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1993 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1994 1995 clocks = <&mmcc MDSS_MDP_CLK>, 1996 <&mmcc MDSS_AHB_CLK>, 1997 <&mmcc MDSS_AXI_CLK>, 1998 <&mmcc MDSS_BYTE0_CLK>, 1999 <&mmcc MDSS_PCLK0_CLK>, 2000 <&mmcc MDSS_ESC0_CLK>, 2001 <&mmcc MMSS_MISC_AHB_CLK>; 2002 clock-names = "mdp_core", 2003 "iface", 2004 "bus", 2005 "byte", 2006 "pixel", 2007 "core", 2008 "core_mmss"; 2009 2010 phys = <&mdss_dsi0_phy>; 2011 2012 status = "disabled"; 2013 2014 #address-cells = <1>; 2015 #size-cells = <0>; 2016 2017 ports { 2018 #address-cells = <1>; 2019 #size-cells = <0>; 2020 2021 port@0 { 2022 reg = <0>; 2023 mdss_dsi0_in: endpoint { 2024 remote-endpoint = <&mdp5_intf1_out>; 2025 }; 2026 }; 2027 2028 port@1 { 2029 reg = <1>; 2030 mdss_dsi0_out: endpoint { 2031 }; 2032 }; 2033 }; 2034 }; 2035 2036 mdss_dsi0_phy: phy@fd922a00 { 2037 compatible = "qcom,dsi-phy-28nm-hpm"; 2038 reg = <0xfd922a00 0xd4>, 2039 <0xfd922b00 0x280>, 2040 <0xfd922d80 0x30>; 2041 reg-names = "dsi_pll", 2042 "dsi_phy", 2043 "dsi_phy_regulator"; 2044 2045 #clock-cells = <1>; 2046 #phy-cells = <0>; 2047 2048 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2049 clock-names = "iface", "ref"; 2050 2051 status = "disabled"; 2052 }; 2053 2054 mdss_dsi1: dsi@fd922e00 { 2055 compatible = "qcom,msm8974-dsi-ctrl", 2056 "qcom,mdss-dsi-ctrl"; 2057 reg = <0xfd922e00 0x1f8>; 2058 reg-names = "dsi_ctrl"; 2059 2060 interrupt-parent = <&mdss>; 2061 interrupts = <4>; 2062 2063 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 2064 <&mmcc PCLK1_CLK_SRC>; 2065 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2066 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 2067 2068 clocks = <&mmcc MDSS_MDP_CLK>, 2069 <&mmcc MDSS_AHB_CLK>, 2070 <&mmcc MDSS_AXI_CLK>, 2071 <&mmcc MDSS_BYTE1_CLK>, 2072 <&mmcc MDSS_PCLK1_CLK>, 2073 <&mmcc MDSS_ESC1_CLK>, 2074 <&mmcc MMSS_MISC_AHB_CLK>; 2075 clock-names = "mdp_core", 2076 "iface", 2077 "bus", 2078 "byte", 2079 "pixel", 2080 "core", 2081 "core_mmss"; 2082 2083 phys = <&mdss_dsi1_phy>; 2084 2085 status = "disabled"; 2086 2087 #address-cells = <1>; 2088 #size-cells = <0>; 2089 2090 ports { 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 2094 port@0 { 2095 reg = <0>; 2096 mdss_dsi1_in: endpoint { 2097 remote-endpoint = <&mdp5_intf2_out>; 2098 }; 2099 }; 2100 2101 port@1 { 2102 reg = <1>; 2103 mdss_dsi1_out: endpoint { 2104 }; 2105 }; 2106 }; 2107 }; 2108 2109 mdss_dsi1_phy: phy@fd923000 { 2110 compatible = "qcom,dsi-phy-28nm-hpm"; 2111 reg = <0xfd923000 0xd4>, 2112 <0xfd923100 0x280>, 2113 <0xfd923380 0x30>; 2114 reg-names = "dsi_pll", 2115 "dsi_phy", 2116 "dsi_phy_regulator"; 2117 2118 #clock-cells = <1>; 2119 #phy-cells = <0>; 2120 2121 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2122 clock-names = "iface", "ref"; 2123 2124 status = "disabled"; 2125 }; 2126 }; 2127 2128 cci: cci@fda0c000 { 2129 compatible = "qcom,msm8974-cci"; 2130 #address-cells = <1>; 2131 #size-cells = <0>; 2132 reg = <0xfda0c000 0x1000>; 2133 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 2134 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2135 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 2136 <&mmcc CAMSS_CCI_CCI_CLK>; 2137 clock-names = "camss_top_ahb", 2138 "cci_ahb", 2139 "cci"; 2140 2141 pinctrl-names = "default", "sleep"; 2142 pinctrl-0 = <&cci_default>; 2143 pinctrl-1 = <&cci_sleep>; 2144 2145 status = "disabled"; 2146 2147 cci_i2c0: i2c-bus@0 { 2148 reg = <0>; 2149 clock-frequency = <100000>; 2150 #address-cells = <1>; 2151 #size-cells = <0>; 2152 }; 2153 2154 cci_i2c1: i2c-bus@1 { 2155 reg = <1>; 2156 clock-frequency = <100000>; 2157 #address-cells = <1>; 2158 #size-cells = <0>; 2159 }; 2160 }; 2161 2162 gpu: gpu@fdb00000 { 2163 compatible = "qcom,adreno-330.1", "qcom,adreno"; 2164 reg = <0xfdb00000 0x10000>; 2165 reg-names = "kgsl_3d0_reg_memory"; 2166 2167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2168 interrupt-names = "kgsl_3d0_irq"; 2169 2170 clocks = <&mmcc OXILI_GFX3D_CLK>, 2171 <&mmcc OXILICX_AHB_CLK>, 2172 <&mmcc OXILICX_AXI_CLK>; 2173 clock-names = "core", "iface", "mem_iface"; 2174 2175 sram = <&gmu_sram>; 2176 power-domains = <&mmcc OXILICX_GDSC>; 2177 operating-points-v2 = <&gpu_opp_table>; 2178 2179 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 2180 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 2181 interconnect-names = "gfx-mem", "ocmem"; 2182 2183 // iommus = <&gpu_iommu 0>; 2184 2185 status = "disabled"; 2186 2187 gpu_opp_table: opp-table { 2188 compatible = "operating-points-v2"; 2189 2190 opp-320000000 { 2191 opp-hz = /bits/ 64 <320000000>; 2192 }; 2193 2194 opp-200000000 { 2195 opp-hz = /bits/ 64 <200000000>; 2196 }; 2197 2198 opp-27000000 { 2199 opp-hz = /bits/ 64 <27000000>; 2200 }; 2201 }; 2202 }; 2203 2204 sram@fdd00000 { 2205 compatible = "qcom,msm8974-ocmem"; 2206 reg = <0xfdd00000 0x2000>, 2207 <0xfec00000 0x180000>; 2208 reg-names = "ctrl", "mem"; 2209 ranges = <0 0xfec00000 0x180000>; 2210 /* core clock doesn't exist anymore, kept for ABI compliance */ 2211 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 2212 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 2213 clock-names = "core", "iface"; 2214 2215 #address-cells = <1>; 2216 #size-cells = <1>; 2217 2218 gmu_sram: gmu-sram@0 { 2219 reg = <0x0 0x100000>; 2220 }; 2221 }; 2222 2223 remoteproc_adsp: remoteproc@fe200000 { 2224 compatible = "qcom,msm8974-adsp-pil"; 2225 reg = <0xfe200000 0x100>; 2226 2227 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2228 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2229 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2230 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2231 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2232 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2233 2234 clocks = <&xo_board>; 2235 clock-names = "xo"; 2236 2237 power-domains = <&rpmpd MSM8974_VDDCX>; 2238 power-domain-names = "cx"; 2239 2240 memory-region = <&adsp_region>; 2241 2242 qcom,smem-states = <&adsp_smp2p_out 0>; 2243 qcom,smem-state-names = "stop"; 2244 2245 status = "disabled"; 2246 2247 smd-edge { 2248 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2249 2250 mboxes = <&apcs 8>; 2251 qcom,smd-edge = <1>; 2252 label = "lpass"; 2253 }; 2254 }; 2255 2256 imem: sram@fe805000 { 2257 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; 2258 reg = <0xfe805000 0x1000>; 2259 2260 reboot-mode { 2261 compatible = "syscon-reboot-mode"; 2262 offset = <0x65c>; 2263 }; 2264 }; 2265 }; 2266 2267 thermal-zones { 2268 cpu0-thermal { 2269 polling-delay-passive = <250>; 2270 polling-delay = <1000>; 2271 2272 thermal-sensors = <&tsens 5>; 2273 2274 trips { 2275 cpu_alert0: trip0 { 2276 temperature = <75000>; 2277 hysteresis = <2000>; 2278 type = "passive"; 2279 }; 2280 cpu_crit0: trip1 { 2281 temperature = <110000>; 2282 hysteresis = <2000>; 2283 type = "critical"; 2284 }; 2285 }; 2286 }; 2287 2288 cpu1-thermal { 2289 polling-delay-passive = <250>; 2290 polling-delay = <1000>; 2291 2292 thermal-sensors = <&tsens 6>; 2293 2294 trips { 2295 cpu_alert1: trip0 { 2296 temperature = <75000>; 2297 hysteresis = <2000>; 2298 type = "passive"; 2299 }; 2300 cpu_crit1: trip1 { 2301 temperature = <110000>; 2302 hysteresis = <2000>; 2303 type = "critical"; 2304 }; 2305 }; 2306 }; 2307 2308 cpu2-thermal { 2309 polling-delay-passive = <250>; 2310 polling-delay = <1000>; 2311 2312 thermal-sensors = <&tsens 7>; 2313 2314 trips { 2315 cpu_alert2: trip0 { 2316 temperature = <75000>; 2317 hysteresis = <2000>; 2318 type = "passive"; 2319 }; 2320 cpu_crit2: trip1 { 2321 temperature = <110000>; 2322 hysteresis = <2000>; 2323 type = "critical"; 2324 }; 2325 }; 2326 }; 2327 2328 cpu3-thermal { 2329 polling-delay-passive = <250>; 2330 polling-delay = <1000>; 2331 2332 thermal-sensors = <&tsens 8>; 2333 2334 trips { 2335 cpu_alert3: trip0 { 2336 temperature = <75000>; 2337 hysteresis = <2000>; 2338 type = "passive"; 2339 }; 2340 cpu_crit3: trip1 { 2341 temperature = <110000>; 2342 hysteresis = <2000>; 2343 type = "critical"; 2344 }; 2345 }; 2346 }; 2347 2348 q6-dsp-thermal { 2349 polling-delay-passive = <250>; 2350 polling-delay = <1000>; 2351 2352 thermal-sensors = <&tsens 1>; 2353 2354 trips { 2355 q6_dsp_alert0: trip-point0 { 2356 temperature = <90000>; 2357 hysteresis = <2000>; 2358 type = "hot"; 2359 }; 2360 }; 2361 }; 2362 2363 modemtx-thermal { 2364 polling-delay-passive = <250>; 2365 polling-delay = <1000>; 2366 2367 thermal-sensors = <&tsens 2>; 2368 2369 trips { 2370 modemtx_alert0: trip-point0 { 2371 temperature = <90000>; 2372 hysteresis = <2000>; 2373 type = "hot"; 2374 }; 2375 }; 2376 }; 2377 2378 video-thermal { 2379 polling-delay-passive = <250>; 2380 polling-delay = <1000>; 2381 2382 thermal-sensors = <&tsens 3>; 2383 2384 trips { 2385 video_alert0: trip-point0 { 2386 temperature = <95000>; 2387 hysteresis = <2000>; 2388 type = "hot"; 2389 }; 2390 }; 2391 }; 2392 2393 wlan-thermal { 2394 polling-delay-passive = <250>; 2395 polling-delay = <1000>; 2396 2397 thermal-sensors = <&tsens 4>; 2398 2399 trips { 2400 wlan_alert0: trip-point0 { 2401 temperature = <105000>; 2402 hysteresis = <2000>; 2403 type = "hot"; 2404 }; 2405 }; 2406 }; 2407 2408 gpu-top-thermal { 2409 polling-delay-passive = <250>; 2410 polling-delay = <1000>; 2411 2412 thermal-sensors = <&tsens 9>; 2413 2414 trips { 2415 gpu1_alert0: trip-point0 { 2416 temperature = <90000>; 2417 hysteresis = <2000>; 2418 type = "hot"; 2419 }; 2420 }; 2421 }; 2422 2423 gpu-bottom-thermal { 2424 polling-delay-passive = <250>; 2425 polling-delay = <1000>; 2426 2427 thermal-sensors = <&tsens 10>; 2428 2429 trips { 2430 gpu2_alert0: trip-point0 { 2431 temperature = <90000>; 2432 hysteresis = <2000>; 2433 type = "hot"; 2434 }; 2435 }; 2436 }; 2437 }; 2438 2439 timer { 2440 compatible = "arm,armv7-timer"; 2441 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2442 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2443 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2444 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2445 clock-frequency = <19200000>; 2446 }; 2447}; 2448