xref: /linux/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi (revision f6154d8babbb8a98f0d3ea325aafae2e33bfd8be)
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interconnect/qcom,msm8974.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8974.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/reset/qcom,gcc-msm8974.h>
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15	interrupt-parent = <&intc>;
16
17	clocks {
18		xo_board: xo_board {
19			compatible = "fixed-clock";
20			#clock-cells = <0>;
21			clock-frequency = <19200000>;
22		};
23
24		sleep_clk: sleep_clk {
25			compatible = "fixed-clock";
26			#clock-cells = <0>;
27			clock-frequency = <32768>;
28		};
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34		interrupts = <GIC_PPI 9 0xf04>;
35
36		CPU0: cpu@0 {
37			compatible = "qcom,krait";
38			enable-method = "qcom,kpss-acc-v2";
39			device_type = "cpu";
40			reg = <0>;
41			next-level-cache = <&L2>;
42			qcom,acc = <&acc0>;
43			qcom,saw = <&saw0>;
44			cpu-idle-states = <&CPU_SPC>;
45		};
46
47		CPU1: cpu@1 {
48			compatible = "qcom,krait";
49			enable-method = "qcom,kpss-acc-v2";
50			device_type = "cpu";
51			reg = <1>;
52			next-level-cache = <&L2>;
53			qcom,acc = <&acc1>;
54			qcom,saw = <&saw1>;
55			cpu-idle-states = <&CPU_SPC>;
56		};
57
58		CPU2: cpu@2 {
59			compatible = "qcom,krait";
60			enable-method = "qcom,kpss-acc-v2";
61			device_type = "cpu";
62			reg = <2>;
63			next-level-cache = <&L2>;
64			qcom,acc = <&acc2>;
65			qcom,saw = <&saw2>;
66			cpu-idle-states = <&CPU_SPC>;
67		};
68
69		CPU3: cpu@3 {
70			compatible = "qcom,krait";
71			enable-method = "qcom,kpss-acc-v2";
72			device_type = "cpu";
73			reg = <3>;
74			next-level-cache = <&L2>;
75			qcom,acc = <&acc3>;
76			qcom,saw = <&saw3>;
77			cpu-idle-states = <&CPU_SPC>;
78		};
79
80		L2: l2-cache {
81			compatible = "cache";
82			cache-level = <2>;
83			cache-unified;
84			qcom,saw = <&saw_l2>;
85		};
86
87		idle-states {
88			CPU_SPC: spc {
89				compatible = "qcom,idle-state-spc",
90						"arm,idle-state";
91				entry-latency-us = <150>;
92				exit-latency-us = <200>;
93				min-residency-us = <2000>;
94			};
95		};
96	};
97
98	firmware {
99		scm {
100			compatible = "qcom,scm-msm8974", "qcom,scm";
101			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
102			clock-names = "core", "bus", "iface";
103		};
104	};
105
106	memory {
107		device_type = "memory";
108		reg = <0x0 0x0>;
109	};
110
111	pmu {
112		compatible = "qcom,krait-pmu";
113		interrupts = <GIC_PPI 7 0xf04>;
114	};
115
116	rpm: remoteproc {
117		compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc";
118
119		master-stats {
120			compatible = "qcom,rpm-master-stats";
121			qcom,rpm-msg-ram = <&apss_master_stats>,
122					   <&mpss_master_stats>,
123					   <&lpss_master_stats>,
124					   <&pronto_master_stats>;
125			qcom,master-names = "APSS",
126					    "MPSS",
127					    "LPSS",
128					    "PRONTO";
129		};
130
131		smd-edge {
132			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
133			qcom,ipc = <&apcs 8 0>;
134			qcom,smd-edge = <15>;
135
136			rpm_requests: rpm-requests {
137				compatible = "qcom,rpm-msm8974";
138				qcom,smd-channels = "rpm_requests";
139
140				rpmcc: clock-controller {
141					compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
142					#clock-cells = <1>;
143					clocks = <&xo_board>;
144					clock-names = "xo";
145				};
146			};
147		};
148	};
149
150	reserved-memory {
151		#address-cells = <1>;
152		#size-cells = <1>;
153		ranges;
154
155		mpss_region: mpss@8000000 {
156			reg = <0x08000000 0x5100000>;
157			no-map;
158		};
159
160		mba_region: mba@d100000 {
161			reg = <0x0d100000 0x100000>;
162			no-map;
163		};
164
165		wcnss_region: wcnss@d200000 {
166			reg = <0x0d200000 0xa00000>;
167			no-map;
168		};
169
170		adsp_region: adsp@dc00000 {
171			reg = <0x0dc00000 0x1900000>;
172			no-map;
173		};
174
175		venus_region: memory@f500000 {
176			reg = <0x0f500000 0x500000>;
177			no-map;
178		};
179
180		smem_region: smem@fa00000 {
181			reg = <0xfa00000 0x200000>;
182			no-map;
183		};
184
185		tz_region: memory@fc00000 {
186			reg = <0x0fc00000 0x160000>;
187			no-map;
188		};
189
190		rfsa_mem: memory@fd60000 {
191			reg = <0x0fd60000 0x20000>;
192			no-map;
193		};
194
195		rmtfs@fd80000 {
196			compatible = "qcom,rmtfs-mem";
197			reg = <0x0fd80000 0x180000>;
198			no-map;
199
200			qcom,client-id = <1>;
201		};
202	};
203
204	smem {
205		compatible = "qcom,smem";
206
207		memory-region = <&smem_region>;
208		qcom,rpm-msg-ram = <&rpm_msg_ram>;
209
210		hwlocks = <&tcsr_mutex 3>;
211	};
212
213	smp2p-adsp {
214		compatible = "qcom,smp2p";
215		qcom,smem = <443>, <429>;
216
217		interrupt-parent = <&intc>;
218		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
219
220		qcom,ipc = <&apcs 8 10>;
221
222		qcom,local-pid = <0>;
223		qcom,remote-pid = <2>;
224
225		adsp_smp2p_out: master-kernel {
226			qcom,entry-name = "master-kernel";
227			#qcom,smem-state-cells = <1>;
228		};
229
230		adsp_smp2p_in: slave-kernel {
231			qcom,entry-name = "slave-kernel";
232
233			interrupt-controller;
234			#interrupt-cells = <2>;
235		};
236	};
237
238	smp2p-modem {
239		compatible = "qcom,smp2p";
240		qcom,smem = <435>, <428>;
241
242		interrupt-parent = <&intc>;
243		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
244
245		qcom,ipc = <&apcs 8 14>;
246
247		qcom,local-pid = <0>;
248		qcom,remote-pid = <1>;
249
250		modem_smp2p_out: master-kernel {
251			qcom,entry-name = "master-kernel";
252			#qcom,smem-state-cells = <1>;
253		};
254
255		modem_smp2p_in: slave-kernel {
256			qcom,entry-name = "slave-kernel";
257
258			interrupt-controller;
259			#interrupt-cells = <2>;
260		};
261	};
262
263	smp2p-wcnss {
264		compatible = "qcom,smp2p";
265		qcom,smem = <451>, <431>;
266
267		interrupt-parent = <&intc>;
268		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
269
270		qcom,ipc = <&apcs 8 18>;
271
272		qcom,local-pid = <0>;
273		qcom,remote-pid = <4>;
274
275		wcnss_smp2p_out: master-kernel {
276			qcom,entry-name = "master-kernel";
277
278			#qcom,smem-state-cells = <1>;
279		};
280
281		wcnss_smp2p_in: slave-kernel {
282			qcom,entry-name = "slave-kernel";
283
284			interrupt-controller;
285			#interrupt-cells = <2>;
286		};
287	};
288
289	smsm {
290		compatible = "qcom,smsm";
291
292		#address-cells = <1>;
293		#size-cells = <0>;
294
295		qcom,ipc-1 = <&apcs 8 13>;
296		qcom,ipc-2 = <&apcs 8 9>;
297		qcom,ipc-3 = <&apcs 8 19>;
298
299		apps_smsm: apps@0 {
300			reg = <0>;
301
302			#qcom,smem-state-cells = <1>;
303		};
304
305		modem_smsm: modem@1 {
306			reg = <1>;
307			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
308
309			interrupt-controller;
310			#interrupt-cells = <2>;
311		};
312
313		adsp_smsm: adsp@2 {
314			reg = <2>;
315			interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
316
317			interrupt-controller;
318			#interrupt-cells = <2>;
319		};
320
321		wcnss_smsm: wcnss@7 {
322			reg = <7>;
323			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
324
325			interrupt-controller;
326			#interrupt-cells = <2>;
327		};
328	};
329
330	soc: soc {
331		#address-cells = <1>;
332		#size-cells = <1>;
333		ranges;
334		compatible = "simple-bus";
335
336		intc: interrupt-controller@f9000000 {
337			compatible = "qcom,msm-qgic2";
338			interrupt-controller;
339			#interrupt-cells = <3>;
340			reg = <0xf9000000 0x1000>,
341			      <0xf9002000 0x1000>;
342		};
343
344		apcs: syscon@f9011000 {
345			compatible = "syscon";
346			reg = <0xf9011000 0x1000>;
347		};
348
349		timer@f9020000 {
350			#address-cells = <1>;
351			#size-cells = <1>;
352			ranges;
353			compatible = "arm,armv7-timer-mem";
354			reg = <0xf9020000 0x1000>;
355			clock-frequency = <19200000>;
356
357			frame@f9021000 {
358				frame-number = <0>;
359				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
360					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
361				reg = <0xf9021000 0x1000>,
362				      <0xf9022000 0x1000>;
363			};
364
365			frame@f9023000 {
366				frame-number = <1>;
367				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
368				reg = <0xf9023000 0x1000>;
369				status = "disabled";
370			};
371
372			frame@f9024000 {
373				frame-number = <2>;
374				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
375				reg = <0xf9024000 0x1000>;
376				status = "disabled";
377			};
378
379			frame@f9025000 {
380				frame-number = <3>;
381				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
382				reg = <0xf9025000 0x1000>;
383				status = "disabled";
384			};
385
386			frame@f9026000 {
387				frame-number = <4>;
388				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
389				reg = <0xf9026000 0x1000>;
390				status = "disabled";
391			};
392
393			frame@f9027000 {
394				frame-number = <5>;
395				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
396				reg = <0xf9027000 0x1000>;
397				status = "disabled";
398			};
399
400			frame@f9028000 {
401				frame-number = <6>;
402				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
403				reg = <0xf9028000 0x1000>;
404				status = "disabled";
405			};
406		};
407
408		saw0: power-controller@f9089000 {
409			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
410			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
411		};
412
413		saw1: power-controller@f9099000 {
414			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
415			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
416		};
417
418		saw2: power-controller@f90a9000 {
419			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
420			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
421		};
422
423		saw3: power-controller@f90b9000 {
424			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
425			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
426		};
427
428		saw_l2: power-controller@f9012000 {
429			compatible = "qcom,saw2";
430			reg = <0xf9012000 0x1000>;
431			regulator;
432		};
433
434		acc0: power-manager@f9088000 {
435			compatible = "qcom,kpss-acc-v2";
436			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
437		};
438
439		acc1: power-manager@f9098000 {
440			compatible = "qcom,kpss-acc-v2";
441			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
442		};
443
444		acc2: power-manager@f90a8000 {
445			compatible = "qcom,kpss-acc-v2";
446			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
447		};
448
449		acc3: power-manager@f90b8000 {
450			compatible = "qcom,kpss-acc-v2";
451			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
452		};
453
454		sdhc_1: mmc@f9824900 {
455			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
456			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
457			reg-names = "hc", "core";
458			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
459				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
460			interrupt-names = "hc_irq", "pwr_irq";
461			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
462				 <&gcc GCC_SDCC1_APPS_CLK>,
463				 <&xo_board>;
464			clock-names = "iface", "core", "xo";
465			bus-width = <8>;
466			non-removable;
467
468			status = "disabled";
469		};
470
471		sdhc_3: mmc@f9864900 {
472			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
473			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
474			reg-names = "hc", "core";
475			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
476				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
477			interrupt-names = "hc_irq", "pwr_irq";
478			clocks = <&gcc GCC_SDCC3_AHB_CLK>,
479				 <&gcc GCC_SDCC3_APPS_CLK>,
480				 <&xo_board>;
481			clock-names = "iface", "core", "xo";
482			bus-width = <4>;
483
484			#address-cells = <1>;
485			#size-cells = <0>;
486
487			status = "disabled";
488		};
489
490		sdhc_2: mmc@f98a4900 {
491			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
492			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
493			reg-names = "hc", "core";
494			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
495				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
496			interrupt-names = "hc_irq", "pwr_irq";
497			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
498				 <&gcc GCC_SDCC2_APPS_CLK>,
499				 <&xo_board>;
500			clock-names = "iface", "core", "xo";
501			bus-width = <4>;
502
503			#address-cells = <1>;
504			#size-cells = <0>;
505
506			status = "disabled";
507		};
508
509		blsp1_uart1: serial@f991d000 {
510			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
511			reg = <0xf991d000 0x1000>;
512			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
513			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
514			clock-names = "core", "iface";
515			status = "disabled";
516		};
517
518		blsp1_uart2: serial@f991e000 {
519			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
520			reg = <0xf991e000 0x1000>;
521			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
522			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
523			clock-names = "core", "iface";
524			pinctrl-names = "default";
525			pinctrl-0 = <&blsp1_uart2_default>;
526			status = "disabled";
527		};
528
529		blsp1_i2c1: i2c@f9923000 {
530			status = "disabled";
531			compatible = "qcom,i2c-qup-v2.1.1";
532			reg = <0xf9923000 0x1000>;
533			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
534			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
535			clock-names = "core", "iface";
536			pinctrl-names = "default", "sleep";
537			pinctrl-0 = <&blsp1_i2c1_default>;
538			pinctrl-1 = <&blsp1_i2c1_sleep>;
539			#address-cells = <1>;
540			#size-cells = <0>;
541		};
542
543		blsp1_i2c2: i2c@f9924000 {
544			status = "disabled";
545			compatible = "qcom,i2c-qup-v2.1.1";
546			reg = <0xf9924000 0x1000>;
547			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
548			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
549			clock-names = "core", "iface";
550			pinctrl-names = "default", "sleep";
551			pinctrl-0 = <&blsp1_i2c2_default>;
552			pinctrl-1 = <&blsp1_i2c2_sleep>;
553			#address-cells = <1>;
554			#size-cells = <0>;
555		};
556
557		blsp1_i2c3: i2c@f9925000 {
558			status = "disabled";
559			compatible = "qcom,i2c-qup-v2.1.1";
560			reg = <0xf9925000 0x1000>;
561			interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
562			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
563			clock-names = "core", "iface";
564			pinctrl-names = "default", "sleep";
565			pinctrl-0 = <&blsp1_i2c3_default>;
566			pinctrl-1 = <&blsp1_i2c3_sleep>;
567			#address-cells = <1>;
568			#size-cells = <0>;
569		};
570
571		blsp1_i2c6: i2c@f9928000 {
572			status = "disabled";
573			compatible = "qcom,i2c-qup-v2.1.1";
574			reg = <0xf9928000 0x1000>;
575			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
576			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
577			clock-names = "core", "iface";
578			pinctrl-names = "default", "sleep";
579			pinctrl-0 = <&blsp1_i2c6_default>;
580			pinctrl-1 = <&blsp1_i2c6_sleep>;
581			#address-cells = <1>;
582			#size-cells = <0>;
583		};
584
585		blsp2_dma: dma-controller@f9944000 {
586			compatible = "qcom,bam-v1.4.0";
587			reg = <0xf9944000 0x19000>;
588			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
589			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
590			clock-names = "bam_clk";
591			#dma-cells = <1>;
592			qcom,ee = <0>;
593		};
594
595		blsp2_uart1: serial@f995d000 {
596			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
597			reg = <0xf995d000 0x1000>;
598			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
599			clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
600			clock-names = "core", "iface";
601			pinctrl-names = "default", "sleep";
602			pinctrl-0 = <&blsp2_uart1_default>;
603			pinctrl-1 = <&blsp2_uart1_sleep>;
604			status = "disabled";
605		};
606
607		blsp2_uart2: serial@f995e000 {
608			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
609			reg = <0xf995e000 0x1000>;
610			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
611			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
612			clock-names = "core", "iface";
613			status = "disabled";
614		};
615
616		blsp2_uart4: serial@f9960000 {
617			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
618			reg = <0xf9960000 0x1000>;
619			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
620			clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
621			clock-names = "core", "iface";
622			pinctrl-names = "default";
623			pinctrl-0 = <&blsp2_uart4_default>;
624			status = "disabled";
625		};
626
627		blsp2_i2c2: i2c@f9964000 {
628			status = "disabled";
629			compatible = "qcom,i2c-qup-v2.1.1";
630			reg = <0xf9964000 0x1000>;
631			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
632			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
633			clock-names = "core", "iface";
634			pinctrl-names = "default", "sleep";
635			pinctrl-0 = <&blsp2_i2c2_default>;
636			pinctrl-1 = <&blsp2_i2c2_sleep>;
637			#address-cells = <1>;
638			#size-cells = <0>;
639		};
640
641		blsp2_i2c5: i2c@f9967000 {
642			status = "disabled";
643			compatible = "qcom,i2c-qup-v2.1.1";
644			reg = <0xf9967000 0x1000>;
645			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
646			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
647			clock-names = "core", "iface";
648			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
649			dma-names = "tx", "rx";
650			pinctrl-names = "default", "sleep";
651			pinctrl-0 = <&blsp2_i2c5_default>;
652			pinctrl-1 = <&blsp2_i2c5_sleep>;
653			#address-cells = <1>;
654			#size-cells = <0>;
655		};
656
657		blsp2_i2c6: i2c@f9968000 {
658			status = "disabled";
659			compatible = "qcom,i2c-qup-v2.1.1";
660			reg = <0xf9968000 0x1000>;
661			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
662			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
663			clock-names = "core", "iface";
664			pinctrl-names = "default", "sleep";
665			pinctrl-0 = <&blsp2_i2c6_default>;
666			pinctrl-1 = <&blsp2_i2c6_sleep>;
667			#address-cells = <1>;
668			#size-cells = <0>;
669		};
670
671		usb: usb@f9a55000 {
672			compatible = "qcom,ci-hdrc";
673			reg = <0xf9a55000 0x200>,
674			      <0xf9a55200 0x200>;
675			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
676			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
677				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
678			clock-names = "iface", "core";
679			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
680			assigned-clock-rates = <75000000>;
681			resets = <&gcc GCC_USB_HS_BCR>;
682			reset-names = "core";
683			phy_type = "ulpi";
684			dr_mode = "otg";
685			ahb-burst-config = <0>;
686			phy-names = "usb-phy";
687			status = "disabled";
688			#reset-cells = <1>;
689
690			ulpi {
691				usb_hs1_phy: phy-0 {
692					compatible = "qcom,usb-hs-phy-msm8974",
693						     "qcom,usb-hs-phy";
694					#phy-cells = <0>;
695					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
696					clock-names = "ref", "sleep";
697					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
698					reset-names = "phy", "por";
699					status = "disabled";
700				};
701
702				usb_hs2_phy: phy-1 {
703					compatible = "qcom,usb-hs-phy-msm8974",
704						     "qcom,usb-hs-phy";
705					#phy-cells = <0>;
706					clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
707					clock-names = "ref", "sleep";
708					resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>;
709					reset-names = "phy", "por";
710					status = "disabled";
711				};
712			};
713		};
714
715		rng@f9bff000 {
716			compatible = "qcom,prng";
717			reg = <0xf9bff000 0x200>;
718			clocks = <&gcc GCC_PRNG_AHB_CLK>;
719			clock-names = "core";
720		};
721
722		pronto: remoteproc@fb204000 {
723			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
724			reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
725			reg-names = "ccu", "dxe", "pmu";
726
727			memory-region = <&wcnss_region>;
728
729			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
730					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
731					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
732					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
733					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
734			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
735
736			qcom,smem-states = <&wcnss_smp2p_out 0>;
737			qcom,smem-state-names = "stop";
738
739			status = "disabled";
740
741			iris {
742				compatible = "qcom,wcn3680";
743
744				clocks = <&rpmcc RPM_SMD_CXO_A2>;
745				clock-names = "xo";
746			};
747
748			smd-edge {
749				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
750
751				qcom,ipc = <&apcs 8 17>;
752				qcom,smd-edge = <6>;
753
754				wcnss {
755					compatible = "qcom,wcnss";
756					qcom,smd-channels = "WCNSS_CTRL";
757					status = "disabled";
758
759					qcom,mmio = <&pronto>;
760
761					bluetooth {
762						compatible = "qcom,wcnss-bt";
763					};
764
765					wifi {
766						compatible = "qcom,wcnss-wlan";
767
768						interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
769							     <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
770						interrupt-names = "tx", "rx";
771
772						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
773						qcom,smem-state-names = "tx-enable",
774									"tx-rings-empty";
775					};
776				};
777			};
778		};
779
780		sram@fc190000 {
781			compatible = "qcom,msm8974-rpm-stats";
782			reg = <0xfc190000 0x10000>;
783		};
784
785		etf@fc307000 {
786			compatible = "arm,coresight-tmc", "arm,primecell";
787			reg = <0xfc307000 0x1000>;
788
789			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
790			clock-names = "apb_pclk", "atclk";
791
792			out-ports {
793				port {
794					etf_out: endpoint {
795						remote-endpoint = <&replicator_in>;
796					};
797				};
798			};
799
800			in-ports {
801				port {
802					etf_in: endpoint {
803						remote-endpoint = <&merger_out>;
804					};
805				};
806			};
807		};
808
809		tpiu@fc318000 {
810			compatible = "arm,coresight-tpiu", "arm,primecell";
811			reg = <0xfc318000 0x1000>;
812
813			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
814			clock-names = "apb_pclk", "atclk";
815
816			in-ports {
817				port {
818					tpiu_in: endpoint {
819						remote-endpoint = <&replicator_out1>;
820					};
821				 };
822			};
823		};
824
825		funnel@fc31a000 {
826			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
827			reg = <0xfc31a000 0x1000>;
828
829			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
830			clock-names = "apb_pclk", "atclk";
831
832			in-ports {
833				#address-cells = <1>;
834				#size-cells = <0>;
835
836				/*
837				 * Not described input ports:
838				 * 0 - not-connected
839				 * 1 - connected trought funnel to Multimedia CPU
840				 * 2 - connected to Wireless CPU
841				 * 3 - not-connected
842				 * 4 - not-connected
843				 * 6 - not-connected
844				 * 7 - connected to STM
845				 */
846				port@5 {
847					reg = <5>;
848					funnel1_in5: endpoint {
849						remote-endpoint = <&kpss_out>;
850					};
851				};
852			};
853
854			out-ports {
855				port {
856					funnel1_out: endpoint {
857						remote-endpoint = <&merger_in1>;
858					};
859				};
860			};
861		};
862
863		funnel@fc31b000 {
864			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
865			reg = <0xfc31b000 0x1000>;
866
867			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
868			clock-names = "apb_pclk", "atclk";
869
870			in-ports {
871				#address-cells = <1>;
872				#size-cells = <0>;
873
874				/*
875				 * Not described input ports:
876				 * 0 - connected trought funnel to Audio, Modem and
877				 *     Resource and Power Manager CPU's
878				 * 2...7 - not-connected
879				 */
880				port@1 {
881					reg = <1>;
882					merger_in1: endpoint {
883						remote-endpoint = <&funnel1_out>;
884					};
885				};
886			};
887
888			out-ports {
889				port {
890					merger_out: endpoint {
891						remote-endpoint = <&etf_in>;
892					};
893				};
894			};
895		};
896
897		replicator@fc31c000 {
898			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
899			reg = <0xfc31c000 0x1000>;
900
901			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
902			clock-names = "apb_pclk", "atclk";
903
904			out-ports {
905				#address-cells = <1>;
906				#size-cells = <0>;
907
908				port@0 {
909					reg = <0>;
910					replicator_out0: endpoint {
911						remote-endpoint = <&etr_in>;
912					};
913				};
914				port@1 {
915					reg = <1>;
916					replicator_out1: endpoint {
917						remote-endpoint = <&tpiu_in>;
918					};
919				};
920			};
921
922			in-ports {
923				port {
924					replicator_in: endpoint {
925						remote-endpoint = <&etf_out>;
926					};
927				};
928			};
929		};
930
931		etr@fc322000 {
932			compatible = "arm,coresight-tmc", "arm,primecell";
933			reg = <0xfc322000 0x1000>;
934
935			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
936			clock-names = "apb_pclk", "atclk";
937
938			in-ports {
939				port {
940					etr_in: endpoint {
941						remote-endpoint = <&replicator_out0>;
942					};
943				};
944			};
945		};
946
947		etm@fc33c000 {
948			compatible = "arm,coresight-etm4x", "arm,primecell";
949			reg = <0xfc33c000 0x1000>;
950
951			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
952			clock-names = "apb_pclk", "atclk";
953
954			cpu = <&CPU0>;
955
956			out-ports {
957				port {
958					etm0_out: endpoint {
959						remote-endpoint = <&kpss_in0>;
960					};
961				};
962			};
963		};
964
965		etm@fc33d000 {
966			compatible = "arm,coresight-etm4x", "arm,primecell";
967			reg = <0xfc33d000 0x1000>;
968
969			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
970			clock-names = "apb_pclk", "atclk";
971
972			cpu = <&CPU1>;
973
974			out-ports {
975				port {
976					etm1_out: endpoint {
977						remote-endpoint = <&kpss_in1>;
978					};
979				};
980			};
981		};
982
983		etm@fc33e000 {
984			compatible = "arm,coresight-etm4x", "arm,primecell";
985			reg = <0xfc33e000 0x1000>;
986
987			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
988			clock-names = "apb_pclk", "atclk";
989
990			cpu = <&CPU2>;
991
992			out-ports {
993				port {
994					etm2_out: endpoint {
995						remote-endpoint = <&kpss_in2>;
996					};
997				};
998			};
999		};
1000
1001		etm@fc33f000 {
1002			compatible = "arm,coresight-etm4x", "arm,primecell";
1003			reg = <0xfc33f000 0x1000>;
1004
1005			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1006			clock-names = "apb_pclk", "atclk";
1007
1008			cpu = <&CPU3>;
1009
1010			out-ports {
1011				port {
1012					etm3_out: endpoint {
1013						remote-endpoint = <&kpss_in3>;
1014					};
1015				};
1016			};
1017		};
1018
1019		/* KPSS funnel, only 4 inputs are used */
1020		funnel@fc345000 {
1021			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1022			reg = <0xfc345000 0x1000>;
1023
1024			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1025			clock-names = "apb_pclk", "atclk";
1026
1027			in-ports {
1028				#address-cells = <1>;
1029				#size-cells = <0>;
1030
1031				port@0 {
1032					reg = <0>;
1033					kpss_in0: endpoint {
1034						remote-endpoint = <&etm0_out>;
1035					};
1036				};
1037				port@1 {
1038					reg = <1>;
1039					kpss_in1: endpoint {
1040						remote-endpoint = <&etm1_out>;
1041					};
1042				};
1043				port@2 {
1044					reg = <2>;
1045					kpss_in2: endpoint {
1046						remote-endpoint = <&etm2_out>;
1047					};
1048				};
1049				port@3 {
1050					reg = <3>;
1051					kpss_in3: endpoint {
1052						remote-endpoint = <&etm3_out>;
1053					};
1054				};
1055			};
1056
1057			out-ports {
1058				port {
1059					kpss_out: endpoint {
1060						remote-endpoint = <&funnel1_in5>;
1061					};
1062				};
1063			};
1064		};
1065
1066		gcc: clock-controller@fc400000 {
1067			compatible = "qcom,gcc-msm8974";
1068			#clock-cells = <1>;
1069			#reset-cells = <1>;
1070			#power-domain-cells = <1>;
1071			reg = <0xfc400000 0x4000>;
1072
1073			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1074				 <&sleep_clk>;
1075			clock-names = "xo",
1076				      "sleep_clk";
1077		};
1078
1079		rpm_msg_ram: sram@fc428000 {
1080			compatible = "qcom,rpm-msg-ram";
1081			reg = <0xfc428000 0x4000>;
1082
1083			#address-cells = <1>;
1084			#size-cells = <1>;
1085			ranges = <0 0xfc428000 0x4000>;
1086
1087			apss_master_stats: sram@150 {
1088				reg = <0x150 0x14>;
1089			};
1090
1091			mpss_master_stats: sram@b50 {
1092				reg = <0xb50 0x14>;
1093			};
1094
1095			lpss_master_stats: sram@1550 {
1096				reg = <0x1550 0x14>;
1097			};
1098
1099			pronto_master_stats: sram@1f50 {
1100				reg = <0x1f50 0x14>;
1101			};
1102		};
1103
1104		bimc: interconnect@fc380000 {
1105			reg = <0xfc380000 0x6a000>;
1106			compatible = "qcom,msm8974-bimc";
1107			#interconnect-cells = <1>;
1108			clock-names = "bus", "bus_a";
1109			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1110			         <&rpmcc RPM_SMD_BIMC_A_CLK>;
1111		};
1112
1113		snoc: interconnect@fc460000 {
1114			reg = <0xfc460000 0x4000>;
1115			compatible = "qcom,msm8974-snoc";
1116			#interconnect-cells = <1>;
1117			clock-names = "bus", "bus_a";
1118			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1119			         <&rpmcc RPM_SMD_SNOC_A_CLK>;
1120		};
1121
1122		pnoc: interconnect@fc468000 {
1123			reg = <0xfc468000 0x4000>;
1124			compatible = "qcom,msm8974-pnoc";
1125			#interconnect-cells = <1>;
1126			clock-names = "bus", "bus_a";
1127			clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1128			         <&rpmcc RPM_SMD_PNOC_A_CLK>;
1129		};
1130
1131		ocmemnoc: interconnect@fc470000 {
1132			reg = <0xfc470000 0x4000>;
1133			compatible = "qcom,msm8974-ocmemnoc";
1134			#interconnect-cells = <1>;
1135			clock-names = "bus", "bus_a";
1136			clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1137			         <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1138		};
1139
1140		mmssnoc: interconnect@fc478000 {
1141			reg = <0xfc478000 0x4000>;
1142			compatible = "qcom,msm8974-mmssnoc";
1143			#interconnect-cells = <1>;
1144			clock-names = "bus", "bus_a";
1145			clocks = <&mmcc MMSS_S0_AXI_CLK>,
1146			         <&mmcc MMSS_S0_AXI_CLK>;
1147		};
1148
1149		cnoc: interconnect@fc480000 {
1150			reg = <0xfc480000 0x4000>;
1151			compatible = "qcom,msm8974-cnoc";
1152			#interconnect-cells = <1>;
1153			clock-names = "bus", "bus_a";
1154			clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1155			         <&rpmcc RPM_SMD_CNOC_A_CLK>;
1156		};
1157
1158		tsens: thermal-sensor@fc4a9000 {
1159			compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
1160			reg = <0xfc4a9000 0x1000>, /* TM */
1161			      <0xfc4a8000 0x1000>; /* SROT */
1162			nvmem-cells = <&tsens_mode>,
1163				      <&tsens_base1>, <&tsens_base2>,
1164				      <&tsens_use_backup>,
1165				      <&tsens_mode_backup>,
1166				      <&tsens_base1_backup>, <&tsens_base2_backup>,
1167				      <&tsens_s0_p1>, <&tsens_s0_p2>,
1168				      <&tsens_s1_p1>, <&tsens_s1_p2>,
1169				      <&tsens_s2_p1>, <&tsens_s2_p2>,
1170				      <&tsens_s3_p1>, <&tsens_s3_p2>,
1171				      <&tsens_s4_p1>, <&tsens_s4_p2>,
1172				      <&tsens_s5_p1>, <&tsens_s5_p2>,
1173				      <&tsens_s6_p1>, <&tsens_s6_p2>,
1174				      <&tsens_s7_p1>, <&tsens_s7_p2>,
1175				      <&tsens_s8_p1>, <&tsens_s8_p2>,
1176				      <&tsens_s9_p1>, <&tsens_s9_p2>,
1177				      <&tsens_s10_p1>, <&tsens_s10_p2>,
1178				      <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
1179				      <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
1180				      <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
1181				      <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
1182				      <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
1183				      <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
1184				      <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
1185				      <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
1186				      <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
1187				      <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
1188				      <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
1189			nvmem-cell-names = "mode",
1190					   "base1", "base2",
1191					   "use_backup",
1192					   "mode_backup",
1193					   "base1_backup", "base2_backup",
1194					   "s0_p1", "s0_p2",
1195					   "s1_p1", "s1_p2",
1196					   "s2_p1", "s2_p2",
1197					   "s3_p1", "s3_p2",
1198					   "s4_p1", "s4_p2",
1199					   "s5_p1", "s5_p2",
1200					   "s6_p1", "s6_p2",
1201					   "s7_p1", "s7_p2",
1202					   "s8_p1", "s8_p2",
1203					   "s9_p1", "s9_p2",
1204					   "s10_p1", "s10_p2",
1205					   "s0_p1_backup", "s0_p2_backup",
1206					   "s1_p1_backup", "s1_p2_backup",
1207					   "s2_p1_backup", "s2_p2_backup",
1208					   "s3_p1_backup", "s3_p2_backup",
1209					   "s4_p1_backup", "s4_p2_backup",
1210					   "s5_p1_backup", "s5_p2_backup",
1211					   "s6_p1_backup", "s6_p2_backup",
1212					   "s7_p1_backup", "s7_p2_backup",
1213					   "s8_p1_backup", "s8_p2_backup",
1214					   "s9_p1_backup", "s9_p2_backup",
1215					   "s10_p1_backup", "s10_p2_backup";
1216			#qcom,sensors = <11>;
1217			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1218			interrupt-names = "uplow";
1219			#thermal-sensor-cells = <1>;
1220		};
1221
1222		restart@fc4ab000 {
1223			compatible = "qcom,pshold";
1224			reg = <0xfc4ab000 0x4>;
1225		};
1226
1227		qfprom: qfprom@fc4bc000 {
1228			compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1229			reg = <0xfc4bc000 0x1000>;
1230			#address-cells = <1>;
1231			#size-cells = <1>;
1232
1233			tsens_base1: base1@d0 {
1234				reg = <0xd0 0x1>;
1235				bits = <0 8>;
1236			};
1237
1238			tsens_s0_p1: s0-p1@d1 {
1239				reg = <0xd1 0x1>;
1240				bits = <0 6>;
1241			};
1242
1243			tsens_s1_p1: s1-p1@d2 {
1244				reg = <0xd1 0x2>;
1245				bits = <6 6>;
1246			};
1247
1248			tsens_s2_p1: s2-p1@d2 {
1249				reg = <0xd2 0x2>;
1250				bits = <4 6>;
1251			};
1252
1253			tsens_s3_p1: s3-p1@d3 {
1254				reg = <0xd3 0x1>;
1255				bits = <2 6>;
1256			};
1257
1258			tsens_s4_p1: s4-p1@d4 {
1259				reg = <0xd4 0x1>;
1260				bits = <0 6>;
1261			};
1262
1263			tsens_s5_p1: s5-p1@d4 {
1264				reg = <0xd4 0x2>;
1265				bits = <6 6>;
1266			};
1267
1268			tsens_s6_p1: s6-p1@d5 {
1269				reg = <0xd5 0x2>;
1270				bits = <4 6>;
1271			};
1272
1273			tsens_s7_p1: s7-p1@d6 {
1274				reg = <0xd6 0x1>;
1275				bits = <2 6>;
1276			};
1277
1278			tsens_s8_p1: s8-p1@d7 {
1279				reg = <0xd7 0x1>;
1280				bits = <0 6>;
1281			};
1282
1283			tsens_mode: mode@d7 {
1284				reg = <0xd7 0x1>;
1285				bits = <6 2>;
1286			};
1287
1288			tsens_s9_p1: s9-p1@d8 {
1289				reg = <0xd8 0x1>;
1290				bits = <0 6>;
1291			};
1292
1293			tsens_s10_p1: s10_p1@d8 {
1294				reg = <0xd8 0x2>;
1295				bits = <6 6>;
1296			};
1297
1298			tsens_base2: base2@d9 {
1299				reg = <0xd9 0x2>;
1300				bits = <4 8>;
1301			};
1302
1303			tsens_s0_p2: s0-p2@da {
1304				reg = <0xda 0x2>;
1305				bits = <4 6>;
1306			};
1307
1308			tsens_s1_p2: s1-p2@db {
1309				reg = <0xdb 0x1>;
1310				bits = <2 6>;
1311			};
1312
1313			tsens_s2_p2: s2-p2@dc {
1314				reg = <0xdc 0x1>;
1315				bits = <0 6>;
1316			};
1317
1318			tsens_s3_p2: s3-p2@dc {
1319				reg = <0xdc 0x2>;
1320				bits = <6 6>;
1321			};
1322
1323			tsens_s4_p2: s4-p2@dd {
1324				reg = <0xdd 0x2>;
1325				bits = <4 6>;
1326			};
1327
1328			tsens_s5_p2: s5-p2@de {
1329				reg = <0xde 0x2>;
1330				bits = <2 6>;
1331			};
1332
1333			tsens_s6_p2: s6-p2@df {
1334				reg = <0xdf 0x1>;
1335				bits = <0 6>;
1336			};
1337
1338			tsens_s7_p2: s7-p2@e0 {
1339				reg = <0xe0 0x1>;
1340				bits = <0 6>;
1341			};
1342
1343			tsens_s8_p2: s8-p2@e0 {
1344				reg = <0xe0 0x2>;
1345				bits = <6 6>;
1346			};
1347
1348			tsens_s9_p2: s9-p2@e1 {
1349				reg = <0xe1 0x2>;
1350				bits = <4 6>;
1351			};
1352
1353			tsens_s10_p2: s10_p2@e2 {
1354				reg = <0xe2 0x2>;
1355				bits = <2 6>;
1356			};
1357
1358			tsens_s5_p2_backup: s5-p2_backup@e3 {
1359				reg = <0xe3 0x2>;
1360				bits = <0 6>;
1361			};
1362
1363			tsens_mode_backup: mode_backup@e3 {
1364				reg = <0xe3 0x1>;
1365				bits = <6 2>;
1366			};
1367
1368			tsens_s6_p2_backup: s6-p2_backup@e4 {
1369				reg = <0xe4 0x1>;
1370				bits = <0 6>;
1371			};
1372
1373			tsens_s7_p2_backup: s7-p2_backup@e4 {
1374				reg = <0xe4 0x2>;
1375				bits = <6 6>;
1376			};
1377
1378			tsens_s8_p2_backup: s8-p2_backup@e5 {
1379				reg = <0xe5 0x2>;
1380				bits = <4 6>;
1381			};
1382
1383			tsens_s9_p2_backup: s9-p2_backup@e6 {
1384				reg = <0xe6 0x2>;
1385				bits = <2 6>;
1386			};
1387
1388			tsens_s10_p2_backup: s10_p2_backup@e7 {
1389				reg = <0xe7 0x1>;
1390				bits = <0 6>;
1391			};
1392
1393			tsens_base1_backup: base1_backup@440 {
1394				reg = <0x440 0x1>;
1395				bits = <0 8>;
1396			};
1397
1398			tsens_s0_p1_backup: s0-p1_backup@441 {
1399				reg = <0x441 0x1>;
1400				bits = <0 6>;
1401			};
1402
1403			tsens_s1_p1_backup: s1-p1_backup@442 {
1404				reg = <0x441 0x2>;
1405				bits = <6 6>;
1406			};
1407
1408			tsens_s2_p1_backup: s2-p1_backup@442 {
1409				reg = <0x442 0x2>;
1410				bits = <4 6>;
1411			};
1412
1413			tsens_s3_p1_backup: s3-p1_backup@443 {
1414				reg = <0x443 0x1>;
1415				bits = <2 6>;
1416			};
1417
1418			tsens_s4_p1_backup: s4-p1_backup@444 {
1419				reg = <0x444 0x1>;
1420				bits = <0 6>;
1421			};
1422
1423			tsens_s5_p1_backup: s5-p1_backup@444 {
1424				reg = <0x444 0x2>;
1425				bits = <6 6>;
1426			};
1427
1428			tsens_s6_p1_backup: s6-p1_backup@445 {
1429				reg = <0x445 0x2>;
1430				bits = <4 6>;
1431			};
1432
1433			tsens_s7_p1_backup: s7-p1_backup@446 {
1434				reg = <0x446 0x1>;
1435				bits = <2 6>;
1436			};
1437
1438			tsens_use_backup: use_backup@447 {
1439				reg = <0x447 0x1>;
1440				bits = <5 3>;
1441			};
1442
1443			tsens_s8_p1_backup: s8-p1_backup@448 {
1444				reg = <0x448 0x1>;
1445				bits = <0 6>;
1446			};
1447
1448			tsens_s9_p1_backup: s9-p1_backup@448 {
1449				reg = <0x448 0x2>;
1450				bits = <6 6>;
1451			};
1452
1453			tsens_s10_p1_backup: s10_p1_backup@449 {
1454				reg = <0x449 0x2>;
1455				bits = <4 6>;
1456			};
1457
1458			tsens_base2_backup: base2_backup@44a {
1459				reg = <0x44a 0x2>;
1460				bits = <2 8>;
1461			};
1462
1463			tsens_s0_p2_backup: s0-p2_backup@44b {
1464				reg = <0x44b 0x3>;
1465				bits = <2 6>;
1466			};
1467
1468			tsens_s1_p2_backup: s1-p2_backup@44c {
1469				reg = <0x44c 0x1>;
1470				bits = <0 6>;
1471			};
1472
1473			tsens_s2_p2_backup: s2-p2_backup@44c {
1474				reg = <0x44c 0x2>;
1475				bits = <6 6>;
1476			};
1477
1478			tsens_s3_p2_backup: s3-p2_backup@44d {
1479				reg = <0x44d 0x2>;
1480				bits = <4 6>;
1481			};
1482
1483			tsens_s4_p2_backup: s4-p2_backup@44e {
1484				reg = <0x44e 0x1>;
1485				bits = <2 6>;
1486			};
1487		};
1488
1489		spmi_bus: spmi@fc4cf000 {
1490			compatible = "qcom,spmi-pmic-arb";
1491			reg-names = "core", "intr", "cnfg";
1492			reg = <0xfc4cf000 0x1000>,
1493			      <0xfc4cb000 0x1000>,
1494			      <0xfc4ca000 0x1000>;
1495			interrupt-names = "periph_irq";
1496			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1497			qcom,ee = <0>;
1498			qcom,channel = <0>;
1499			#address-cells = <2>;
1500			#size-cells = <0>;
1501			interrupt-controller;
1502			#interrupt-cells = <4>;
1503		};
1504
1505		bam_dmux_dma: dma-controller@fc834000 {
1506			compatible = "qcom,bam-v1.4.0";
1507			reg = <0xfc834000 0x7000>;
1508			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1509			#dma-cells = <1>;
1510			qcom,ee = <0>;
1511
1512			num-channels = <6>;
1513			qcom,num-ees = <1>;
1514			qcom,powered-remotely;
1515		};
1516
1517		remoteproc_mss: remoteproc@fc880000 {
1518			compatible = "qcom,msm8974-mss-pil";
1519			reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1520			reg-names = "qdsp6", "rmb";
1521
1522			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1523					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1524					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1525					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1526					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1527			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1528
1529			clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1530				 <&gcc GCC_MSS_CFG_AHB_CLK>,
1531				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1532				 <&xo_board>;
1533			clock-names = "iface", "bus", "mem", "xo";
1534
1535			resets = <&gcc GCC_MSS_RESTART>;
1536			reset-names = "mss_restart";
1537
1538			qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1539
1540			qcom,smem-states = <&modem_smp2p_out 0>;
1541			qcom,smem-state-names = "stop";
1542
1543			status = "disabled";
1544
1545			mba {
1546				memory-region = <&mba_region>;
1547			};
1548
1549			mpss {
1550				memory-region = <&mpss_region>;
1551			};
1552
1553			bam_dmux: bam-dmux {
1554				compatible = "qcom,bam-dmux";
1555
1556				interrupt-parent = <&modem_smsm>;
1557				interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1558				interrupt-names = "pc", "pc-ack";
1559
1560				qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1561				qcom,smem-state-names = "pc", "pc-ack";
1562
1563				dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1564				dma-names = "tx", "rx";
1565			};
1566
1567			smd-edge {
1568				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1569
1570				qcom,ipc = <&apcs 8 12>;
1571				qcom,smd-edge = <0>;
1572
1573				label = "modem";
1574			};
1575		};
1576
1577		tcsr_mutex: hwlock@fd484000 {
1578			compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
1579			reg = <0xfd484000 0x2000>;
1580			#hwlock-cells = <1>;
1581		};
1582
1583		tcsr: syscon@fd4a0000 {
1584			compatible = "qcom,tcsr-msm8974", "syscon";
1585			reg = <0xfd4a0000 0x10000>;
1586		};
1587
1588		tlmm: pinctrl@fd510000 {
1589			compatible = "qcom,msm8974-pinctrl";
1590			reg = <0xfd510000 0x4000>;
1591			gpio-controller;
1592			gpio-ranges = <&tlmm 0 0 146>;
1593			#gpio-cells = <2>;
1594			interrupt-controller;
1595			#interrupt-cells = <2>;
1596			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1597
1598			sdc1_off: sdc1-off-state {
1599				clk-pins {
1600					pins = "sdc1_clk";
1601					bias-disable;
1602					drive-strength = <2>;
1603				};
1604
1605				cmd-pins {
1606					pins = "sdc1_cmd";
1607					bias-pull-up;
1608					drive-strength = <2>;
1609				};
1610
1611				data-pins {
1612					pins = "sdc1_data";
1613					bias-pull-up;
1614					drive-strength = <2>;
1615				};
1616			};
1617
1618			sdc2_off: sdc2-off-state {
1619				clk-pins {
1620					pins = "sdc2_clk";
1621					bias-disable;
1622					drive-strength = <2>;
1623				};
1624
1625				cmd-pins {
1626					pins = "sdc2_cmd";
1627					bias-pull-up;
1628					drive-strength = <2>;
1629				};
1630
1631				data-pins {
1632					pins = "sdc2_data";
1633					bias-pull-up;
1634					drive-strength = <2>;
1635				};
1636
1637				cd-pins {
1638					pins = "gpio54";
1639					function = "gpio";
1640					bias-disable;
1641					drive-strength = <2>;
1642				};
1643			};
1644
1645			blsp1_uart2_default: blsp1-uart2-default-state {
1646				rx-pins {
1647					pins = "gpio5";
1648					function = "blsp_uart2";
1649					drive-strength = <2>;
1650					bias-pull-up;
1651				};
1652
1653				tx-pins {
1654					pins = "gpio4";
1655					function = "blsp_uart2";
1656					drive-strength = <4>;
1657					bias-disable;
1658				};
1659			};
1660
1661			blsp2_uart1_default: blsp2-uart1-default-state {
1662				tx-rts-pins {
1663					pins = "gpio41", "gpio44";
1664					function = "blsp_uart7";
1665					drive-strength = <2>;
1666					bias-disable;
1667				};
1668
1669				rx-cts-pins {
1670					pins = "gpio42", "gpio43";
1671					function = "blsp_uart7";
1672					drive-strength = <2>;
1673					bias-pull-up;
1674				};
1675			};
1676
1677			blsp2_uart1_sleep: blsp2-uart1-sleep-state {
1678				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1679				function = "gpio";
1680				drive-strength = <2>;
1681				bias-pull-down;
1682			};
1683
1684			blsp2_uart4_default: blsp2-uart4-default-state {
1685				tx-rts-pins {
1686					pins = "gpio53", "gpio56";
1687					function = "blsp_uart10";
1688					drive-strength = <2>;
1689					bias-disable;
1690				};
1691
1692				rx-cts-pins {
1693					pins = "gpio54", "gpio55";
1694					function = "blsp_uart10";
1695					drive-strength = <2>;
1696					bias-pull-up;
1697				};
1698			};
1699
1700			blsp1_i2c1_default: blsp1-i2c1-default-state {
1701				pins = "gpio2", "gpio3";
1702				function = "blsp_i2c1";
1703				drive-strength = <2>;
1704				bias-disable;
1705			};
1706
1707			blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
1708				pins = "gpio2", "gpio3";
1709				function = "blsp_i2c1";
1710				drive-strength = <2>;
1711				bias-pull-up;
1712			};
1713
1714			blsp1_i2c2_default: blsp1-i2c2-default-state {
1715				pins = "gpio6", "gpio7";
1716				function = "blsp_i2c2";
1717				drive-strength = <2>;
1718				bias-disable;
1719			};
1720
1721			blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
1722				pins = "gpio6", "gpio7";
1723				function = "blsp_i2c2";
1724				drive-strength = <2>;
1725				bias-pull-up;
1726			};
1727
1728			blsp1_i2c3_default: blsp1-i2c3-default-state {
1729				pins = "gpio10", "gpio11";
1730				function = "blsp_i2c3";
1731				drive-strength = <2>;
1732				bias-disable;
1733			};
1734
1735			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1736				pins = "gpio10", "gpio11";
1737				function = "blsp_i2c3";
1738				drive-strength = <2>;
1739				bias-pull-up;
1740			};
1741
1742			/* BLSP1_I2C4 info is missing */
1743
1744			/* BLSP1_I2C5 info is missing */
1745
1746			blsp1_i2c6_default: blsp1-i2c6-default-state {
1747				pins = "gpio29", "gpio30";
1748				function = "blsp_i2c6";
1749				drive-strength = <2>;
1750				bias-disable;
1751			};
1752
1753			blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1754				pins = "gpio29", "gpio30";
1755				function = "blsp_i2c6";
1756				drive-strength = <2>;
1757				bias-pull-up;
1758			};
1759			/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1760
1761			/* BLSP2_I2C1 info is missing */
1762
1763			blsp2_i2c2_default: blsp2-i2c2-default-state {
1764				pins = "gpio47", "gpio48";
1765				function = "blsp_i2c8";
1766				drive-strength = <2>;
1767				bias-disable;
1768			};
1769
1770			blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1771				pins = "gpio47", "gpio48";
1772				function = "blsp_i2c8";
1773				drive-strength = <2>;
1774				bias-pull-up;
1775			};
1776
1777			/* BLSP2_I2C3 info is missing */
1778
1779			/* BLSP2_I2C4 info is missing */
1780
1781			blsp2_i2c5_default: blsp2-i2c5-default-state {
1782				pins = "gpio83", "gpio84";
1783				function = "blsp_i2c11";
1784				drive-strength = <2>;
1785				bias-disable;
1786			};
1787
1788			blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1789				pins = "gpio83", "gpio84";
1790				function = "blsp_i2c11";
1791				drive-strength = <2>;
1792				bias-pull-up;
1793			};
1794
1795			blsp2_i2c6_default: blsp2-i2c6-default-state {
1796				pins = "gpio87", "gpio88";
1797				function = "blsp_i2c12";
1798				drive-strength = <2>;
1799				bias-disable;
1800			};
1801
1802			blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1803				pins = "gpio87", "gpio88";
1804				function = "blsp_i2c12";
1805				drive-strength = <2>;
1806				bias-pull-up;
1807			};
1808
1809			cci_default: cci-default-state {
1810				cci_i2c0_default: cci-i2c0-default-pins {
1811					pins = "gpio19", "gpio20";
1812					function = "cci_i2c0";
1813					drive-strength = <2>;
1814					bias-disable;
1815				};
1816
1817				cci_i2c1_default: cci-i2c1-default-pins {
1818					pins = "gpio21", "gpio22";
1819					function = "cci_i2c1";
1820					drive-strength = <2>;
1821					bias-disable;
1822				};
1823			};
1824
1825			cci_sleep: cci-sleep-state {
1826				cci_i2c0_sleep: cci-i2c0-sleep-pins {
1827					pins = "gpio19", "gpio20";
1828					function = "gpio";
1829					drive-strength = <2>;
1830					bias-disable;
1831				};
1832
1833				cci_i2c1_sleep: cci-i2c1-sleep-pins {
1834					pins = "gpio21", "gpio22";
1835					function = "gpio";
1836					drive-strength = <2>;
1837					bias-disable;
1838				};
1839			};
1840
1841			spi8_default: spi8_default-state {
1842				mosi-pins {
1843					pins = "gpio45";
1844					function = "blsp_spi8";
1845				};
1846				miso-pins {
1847					pins = "gpio46";
1848					function = "blsp_spi8";
1849				};
1850				cs-pins {
1851					pins = "gpio47";
1852					function = "blsp_spi8";
1853				};
1854				clk-pins {
1855					pins = "gpio48";
1856					function = "blsp_spi8";
1857				};
1858			};
1859		};
1860
1861		mmcc: clock-controller@fd8c0000 {
1862			compatible = "qcom,mmcc-msm8974";
1863			#clock-cells = <1>;
1864			#reset-cells = <1>;
1865			#power-domain-cells = <1>;
1866			reg = <0xfd8c0000 0x6000>;
1867			clocks = <&xo_board>,
1868				 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
1869				 <&gcc GPLL0_VOTE>,
1870				 <&gcc GPLL1_VOTE>,
1871				 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1872				 <&mdss_dsi0_phy 1>,
1873				 <&mdss_dsi0_phy 0>,
1874				 <&mdss_dsi1_phy 1>,
1875				 <&mdss_dsi1_phy 0>,
1876				 <0>,
1877				 <0>,
1878				 <0>;
1879			clock-names = "xo",
1880				      "mmss_gpll0_vote",
1881				      "gpll0_vote",
1882				      "gpll1_vote",
1883				      "gfx3d_clk_src",
1884				      "dsi0pll",
1885				      "dsi0pllbyte",
1886				      "dsi1pll",
1887				      "dsi1pllbyte",
1888				      "hdmipll",
1889				      "edp_link_clk",
1890				      "edp_vco_div";
1891		};
1892
1893		mdss: display-subsystem@fd900000 {
1894			compatible = "qcom,mdss";
1895			reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1896			reg-names = "mdss_phys", "vbif_phys";
1897
1898			power-domains = <&mmcc MDSS_GDSC>;
1899
1900			clocks = <&mmcc MDSS_AHB_CLK>,
1901				 <&mmcc MDSS_AXI_CLK>,
1902				 <&mmcc MDSS_VSYNC_CLK>;
1903			clock-names = "iface", "bus", "vsync";
1904
1905			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1906
1907			interrupt-controller;
1908			#interrupt-cells = <1>;
1909
1910			status = "disabled";
1911
1912			#address-cells = <1>;
1913			#size-cells = <1>;
1914			ranges;
1915
1916			mdp: display-controller@fd900000 {
1917				compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
1918				reg = <0xfd900100 0x22000>;
1919				reg-names = "mdp_phys";
1920
1921				interrupt-parent = <&mdss>;
1922				interrupts = <0>;
1923
1924				clocks = <&mmcc MDSS_AHB_CLK>,
1925					 <&mmcc MDSS_AXI_CLK>,
1926					 <&mmcc MDSS_MDP_CLK>,
1927					 <&mmcc MDSS_VSYNC_CLK>;
1928				clock-names = "iface", "bus", "core", "vsync";
1929
1930				interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1931				interconnect-names = "mdp0-mem";
1932
1933				ports {
1934					#address-cells = <1>;
1935					#size-cells = <0>;
1936
1937					port@0 {
1938						reg = <0>;
1939						mdp5_intf1_out: endpoint {
1940							remote-endpoint = <&mdss_dsi0_in>;
1941						};
1942					};
1943
1944					port@1 {
1945						reg = <1>;
1946						mdp5_intf2_out: endpoint {
1947							remote-endpoint = <&mdss_dsi1_in>;
1948						};
1949					};
1950				};
1951			};
1952
1953			mdss_dsi0: dsi@fd922800 {
1954				compatible = "qcom,msm8974-dsi-ctrl",
1955					     "qcom,mdss-dsi-ctrl";
1956				reg = <0xfd922800 0x1f8>;
1957				reg-names = "dsi_ctrl";
1958
1959				interrupt-parent = <&mdss>;
1960				interrupts = <4>;
1961
1962				assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1963				assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1964
1965				clocks = <&mmcc MDSS_MDP_CLK>,
1966					 <&mmcc MDSS_AHB_CLK>,
1967					 <&mmcc MDSS_AXI_CLK>,
1968					 <&mmcc MDSS_BYTE0_CLK>,
1969					 <&mmcc MDSS_PCLK0_CLK>,
1970					 <&mmcc MDSS_ESC0_CLK>,
1971					 <&mmcc MMSS_MISC_AHB_CLK>;
1972				clock-names = "mdp_core",
1973					      "iface",
1974					      "bus",
1975					      "byte",
1976					      "pixel",
1977					      "core",
1978					      "core_mmss";
1979
1980				phys = <&mdss_dsi0_phy>;
1981
1982				status = "disabled";
1983
1984				#address-cells = <1>;
1985				#size-cells = <0>;
1986
1987				ports {
1988					#address-cells = <1>;
1989					#size-cells = <0>;
1990
1991					port@0 {
1992						reg = <0>;
1993						mdss_dsi0_in: endpoint {
1994							remote-endpoint = <&mdp5_intf1_out>;
1995						};
1996					};
1997
1998					port@1 {
1999						reg = <1>;
2000						mdss_dsi0_out: endpoint {
2001						};
2002					};
2003				};
2004			};
2005
2006			mdss_dsi0_phy: phy@fd922a00 {
2007				compatible = "qcom,dsi-phy-28nm-hpm";
2008				reg = <0xfd922a00 0xd4>,
2009				      <0xfd922b00 0x280>,
2010				      <0xfd922d80 0x30>;
2011				reg-names = "dsi_pll",
2012					    "dsi_phy",
2013					    "dsi_phy_regulator";
2014
2015				#clock-cells = <1>;
2016				#phy-cells = <0>;
2017
2018				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2019				clock-names = "iface", "ref";
2020
2021				status = "disabled";
2022			};
2023
2024			mdss_dsi1: dsi@fd922e00 {
2025				compatible = "qcom,msm8974-dsi-ctrl",
2026					     "qcom,mdss-dsi-ctrl";
2027				reg = <0xfd922e00 0x1f8>;
2028				reg-names = "dsi_ctrl";
2029
2030				interrupt-parent = <&mdss>;
2031				interrupts = <4>;
2032
2033				assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2034				assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2035
2036				clocks = <&mmcc MDSS_MDP_CLK>,
2037					 <&mmcc MDSS_AHB_CLK>,
2038					 <&mmcc MDSS_AXI_CLK>,
2039					 <&mmcc MDSS_BYTE1_CLK>,
2040					 <&mmcc MDSS_PCLK1_CLK>,
2041					 <&mmcc MDSS_ESC1_CLK>,
2042					 <&mmcc MMSS_MISC_AHB_CLK>;
2043				clock-names = "mdp_core",
2044					      "iface",
2045					      "bus",
2046					      "byte",
2047					      "pixel",
2048					      "core",
2049					      "core_mmss";
2050
2051				phys = <&mdss_dsi1_phy>;
2052
2053				status = "disabled";
2054
2055				#address-cells = <1>;
2056				#size-cells = <0>;
2057
2058				ports {
2059					#address-cells = <1>;
2060					#size-cells = <0>;
2061
2062					port@0 {
2063						reg = <0>;
2064						mdss_dsi1_in: endpoint {
2065							remote-endpoint = <&mdp5_intf2_out>;
2066						};
2067					};
2068
2069					port@1 {
2070						reg = <1>;
2071						mdss_dsi1_out: endpoint {
2072						};
2073					};
2074				};
2075			};
2076
2077			mdss_dsi1_phy: phy@fd923000 {
2078				compatible = "qcom,dsi-phy-28nm-hpm";
2079				reg = <0xfd923000 0xd4>,
2080				      <0xfd923100 0x280>,
2081				      <0xfd923380 0x30>;
2082				reg-names = "dsi_pll",
2083					    "dsi_phy",
2084					    "dsi_phy_regulator";
2085
2086				#clock-cells = <1>;
2087				#phy-cells = <0>;
2088
2089				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2090				clock-names = "iface", "ref";
2091
2092				status = "disabled";
2093			};
2094		};
2095
2096		cci: cci@fda0c000 {
2097			compatible = "qcom,msm8974-cci";
2098			#address-cells = <1>;
2099			#size-cells = <0>;
2100			reg = <0xfda0c000 0x1000>;
2101			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
2102			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2103				 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
2104				 <&mmcc CAMSS_CCI_CCI_CLK>;
2105			clock-names = "camss_top_ahb",
2106				      "cci_ahb",
2107				      "cci";
2108
2109			pinctrl-names = "default", "sleep";
2110			pinctrl-0 = <&cci_default>;
2111			pinctrl-1 = <&cci_sleep>;
2112
2113			status = "disabled";
2114
2115			cci_i2c0: i2c-bus@0 {
2116				reg = <0>;
2117				clock-frequency = <100000>;
2118				#address-cells = <1>;
2119				#size-cells = <0>;
2120			};
2121
2122			cci_i2c1: i2c-bus@1 {
2123				reg = <1>;
2124				clock-frequency = <100000>;
2125				#address-cells = <1>;
2126				#size-cells = <0>;
2127			};
2128		};
2129
2130		gpu: adreno@fdb00000 {
2131			compatible = "qcom,adreno-330.1", "qcom,adreno";
2132			reg = <0xfdb00000 0x10000>;
2133			reg-names = "kgsl_3d0_reg_memory";
2134
2135			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2136			interrupt-names = "kgsl_3d0_irq";
2137
2138			clocks = <&mmcc OXILI_GFX3D_CLK>,
2139				 <&mmcc OXILICX_AHB_CLK>,
2140				 <&mmcc OXILICX_AXI_CLK>;
2141			clock-names = "core", "iface", "mem_iface";
2142
2143			sram = <&gmu_sram>;
2144			power-domains = <&mmcc OXILICX_GDSC>;
2145			operating-points-v2 = <&gpu_opp_table>;
2146
2147			interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
2148					<&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
2149			interconnect-names = "gfx-mem", "ocmem";
2150
2151			// iommus = <&gpu_iommu 0>;
2152
2153			status = "disabled";
2154
2155			gpu_opp_table: opp-table {
2156				compatible = "operating-points-v2";
2157
2158				opp-320000000 {
2159					opp-hz = /bits/ 64 <320000000>;
2160				};
2161
2162				opp-200000000 {
2163					opp-hz = /bits/ 64 <200000000>;
2164				};
2165
2166				opp-27000000 {
2167					opp-hz = /bits/ 64 <27000000>;
2168				};
2169			};
2170		};
2171
2172		sram@fdd00000 {
2173			compatible = "qcom,msm8974-ocmem";
2174			reg = <0xfdd00000 0x2000>,
2175			      <0xfec00000 0x180000>;
2176			reg-names = "ctrl", "mem";
2177			ranges = <0 0xfec00000 0x180000>;
2178			clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
2179				 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
2180			clock-names = "core", "iface";
2181
2182			#address-cells = <1>;
2183			#size-cells = <1>;
2184
2185			gmu_sram: gmu-sram@0 {
2186				reg = <0x0 0x100000>;
2187			};
2188		};
2189
2190		remoteproc_adsp: remoteproc@fe200000 {
2191			compatible = "qcom,msm8974-adsp-pil";
2192			reg = <0xfe200000 0x100>;
2193
2194			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2195					       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2196					       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2197					       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2198					       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2199			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2200
2201			clocks = <&xo_board>;
2202			clock-names = "xo";
2203
2204			memory-region = <&adsp_region>;
2205
2206			qcom,smem-states = <&adsp_smp2p_out 0>;
2207			qcom,smem-state-names = "stop";
2208
2209			status = "disabled";
2210
2211			smd-edge {
2212				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2213
2214				qcom,ipc = <&apcs 8 8>;
2215				qcom,smd-edge = <1>;
2216				label = "lpass";
2217			};
2218		};
2219
2220		imem: sram@fe805000 {
2221			compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
2222			reg = <0xfe805000 0x1000>;
2223
2224			reboot-mode {
2225				compatible = "syscon-reboot-mode";
2226				offset = <0x65c>;
2227			};
2228		};
2229	};
2230
2231	thermal-zones {
2232		cpu0-thermal {
2233			polling-delay-passive = <250>;
2234			polling-delay = <1000>;
2235
2236			thermal-sensors = <&tsens 5>;
2237
2238			trips {
2239				cpu_alert0: trip0 {
2240					temperature = <75000>;
2241					hysteresis = <2000>;
2242					type = "passive";
2243				};
2244				cpu_crit0: trip1 {
2245					temperature = <110000>;
2246					hysteresis = <2000>;
2247					type = "critical";
2248				};
2249			};
2250		};
2251
2252		cpu1-thermal {
2253			polling-delay-passive = <250>;
2254			polling-delay = <1000>;
2255
2256			thermal-sensors = <&tsens 6>;
2257
2258			trips {
2259				cpu_alert1: trip0 {
2260					temperature = <75000>;
2261					hysteresis = <2000>;
2262					type = "passive";
2263				};
2264				cpu_crit1: trip1 {
2265					temperature = <110000>;
2266					hysteresis = <2000>;
2267					type = "critical";
2268				};
2269			};
2270		};
2271
2272		cpu2-thermal {
2273			polling-delay-passive = <250>;
2274			polling-delay = <1000>;
2275
2276			thermal-sensors = <&tsens 7>;
2277
2278			trips {
2279				cpu_alert2: trip0 {
2280					temperature = <75000>;
2281					hysteresis = <2000>;
2282					type = "passive";
2283				};
2284				cpu_crit2: trip1 {
2285					temperature = <110000>;
2286					hysteresis = <2000>;
2287					type = "critical";
2288				};
2289			};
2290		};
2291
2292		cpu3-thermal {
2293			polling-delay-passive = <250>;
2294			polling-delay = <1000>;
2295
2296			thermal-sensors = <&tsens 8>;
2297
2298			trips {
2299				cpu_alert3: trip0 {
2300					temperature = <75000>;
2301					hysteresis = <2000>;
2302					type = "passive";
2303				};
2304				cpu_crit3: trip1 {
2305					temperature = <110000>;
2306					hysteresis = <2000>;
2307					type = "critical";
2308				};
2309			};
2310		};
2311
2312		q6-dsp-thermal {
2313			polling-delay-passive = <250>;
2314			polling-delay = <1000>;
2315
2316			thermal-sensors = <&tsens 1>;
2317
2318			trips {
2319				q6_dsp_alert0: trip-point0 {
2320					temperature = <90000>;
2321					hysteresis = <2000>;
2322					type = "hot";
2323				};
2324			};
2325		};
2326
2327		modemtx-thermal {
2328			polling-delay-passive = <250>;
2329			polling-delay = <1000>;
2330
2331			thermal-sensors = <&tsens 2>;
2332
2333			trips {
2334				modemtx_alert0: trip-point0 {
2335					temperature = <90000>;
2336					hysteresis = <2000>;
2337					type = "hot";
2338				};
2339			};
2340		};
2341
2342		video-thermal {
2343			polling-delay-passive = <250>;
2344			polling-delay = <1000>;
2345
2346			thermal-sensors = <&tsens 3>;
2347
2348			trips {
2349				video_alert0: trip-point0 {
2350					temperature = <95000>;
2351					hysteresis = <2000>;
2352					type = "hot";
2353				};
2354			};
2355		};
2356
2357		wlan-thermal {
2358			polling-delay-passive = <250>;
2359			polling-delay = <1000>;
2360
2361			thermal-sensors = <&tsens 4>;
2362
2363			trips {
2364				wlan_alert0: trip-point0 {
2365					temperature = <105000>;
2366					hysteresis = <2000>;
2367					type = "hot";
2368				};
2369			};
2370		};
2371
2372		gpu-top-thermal {
2373			polling-delay-passive = <250>;
2374			polling-delay = <1000>;
2375
2376			thermal-sensors = <&tsens 9>;
2377
2378			trips {
2379				gpu1_alert0: trip-point0 {
2380					temperature = <90000>;
2381					hysteresis = <2000>;
2382					type = "hot";
2383				};
2384			};
2385		};
2386
2387		gpu-bottom-thermal {
2388			polling-delay-passive = <250>;
2389			polling-delay = <1000>;
2390
2391			thermal-sensors = <&tsens 10>;
2392
2393			trips {
2394				gpu2_alert0: trip-point0 {
2395					temperature = <90000>;
2396					hysteresis = <2000>;
2397					type = "hot";
2398				};
2399			};
2400		};
2401	};
2402
2403	timer {
2404		compatible = "arm,armv7-timer";
2405		interrupts = <GIC_PPI 2 0xf08>,
2406			     <GIC_PPI 3 0xf08>,
2407			     <GIC_PPI 4 0xf08>,
2408			     <GIC_PPI 1 0xf08>;
2409		clock-frequency = <19200000>;
2410	};
2411
2412	vreg_boost: vreg-boost {
2413		compatible = "regulator-fixed";
2414
2415		regulator-name = "vreg-boost";
2416		regulator-min-microvolt = <3150000>;
2417		regulator-max-microvolt = <3150000>;
2418
2419		regulator-always-on;
2420		regulator-boot-on;
2421
2422		gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
2423		enable-active-high;
2424
2425		pinctrl-names = "default";
2426		pinctrl-0 = <&boost_bypass_n_pin>;
2427	};
2428
2429	vreg_vph_pwr: vreg-vph-pwr {
2430		compatible = "regulator-fixed";
2431		regulator-name = "vph-pwr";
2432
2433		regulator-min-microvolt = <3600000>;
2434		regulator-max-microvolt = <3600000>;
2435
2436		regulator-always-on;
2437	};
2438};
2439