1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,lcc-msm8960.h> 8#include <dt-bindings/mfd/qcom-rpm.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 model = "Qualcomm MSM8960"; 15 compatible = "qcom,msm8960"; 16 interrupt-parent = <&intc>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 interrupts = <GIC_PPI 14 0x304>; 22 23 cpu@0 { 24 compatible = "qcom,krait"; 25 enable-method = "qcom,kpss-acc-v1"; 26 device_type = "cpu"; 27 reg = <0>; 28 next-level-cache = <&L2>; 29 qcom,acc = <&acc0>; 30 qcom,saw = <&saw0>; 31 }; 32 33 cpu@1 { 34 compatible = "qcom,krait"; 35 enable-method = "qcom,kpss-acc-v1"; 36 device_type = "cpu"; 37 reg = <1>; 38 next-level-cache = <&L2>; 39 qcom,acc = <&acc1>; 40 qcom,saw = <&saw1>; 41 }; 42 43 L2: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 }; 48 }; 49 50 memory { 51 device_type = "memory"; 52 reg = <0x0 0x0>; 53 }; 54 55 cpu-pmu { 56 compatible = "qcom,krait-pmu"; 57 interrupts = <GIC_PPI 10 0x304>; 58 qcom,no-pc-write; 59 }; 60 61 clocks { 62 cxo_board: cxo_board { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <19200000>; 66 clock-output-names = "cxo_board"; 67 }; 68 69 pxo_board: pxo_board { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <27000000>; 73 clock-output-names = "pxo_board"; 74 }; 75 76 sleep_clk: sleep_clk { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <32768>; 80 clock-output-names = "sleep_clk"; 81 }; 82 }; 83 84 /* Temporary fixed regulator */ 85 vsdcc_fixed: vsdcc-regulator { 86 compatible = "regulator-fixed"; 87 regulator-name = "SDCC Power"; 88 regulator-min-microvolt = <2700000>; 89 regulator-max-microvolt = <2700000>; 90 regulator-always-on; 91 }; 92 93 soc: soc { 94 #address-cells = <1>; 95 #size-cells = <1>; 96 ranges; 97 compatible = "simple-bus"; 98 99 intc: interrupt-controller@2000000 { 100 compatible = "qcom,msm-qgic2"; 101 interrupt-controller; 102 #interrupt-cells = <3>; 103 reg = <0x02000000 0x1000>, 104 <0x02002000 0x1000>; 105 }; 106 107 timer@200a000 { 108 compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", 109 "qcom,msm-timer"; 110 interrupts = <GIC_PPI 1 0x301>, 111 <GIC_PPI 2 0x301>, 112 <GIC_PPI 3 0x301>; 113 reg = <0x0200a000 0x100>; 114 clock-frequency = <27000000>; 115 cpu-offset = <0x80000>; 116 }; 117 118 msmgpio: pinctrl@800000 { 119 compatible = "qcom,msm8960-pinctrl"; 120 gpio-controller; 121 gpio-ranges = <&msmgpio 0 0 152>; 122 #gpio-cells = <2>; 123 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 124 interrupt-controller; 125 #interrupt-cells = <2>; 126 reg = <0x800000 0x4000>; 127 }; 128 129 gcc: clock-controller@900000 { 130 compatible = "qcom,gcc-msm8960"; 131 #clock-cells = <1>; 132 #power-domain-cells = <1>; 133 #reset-cells = <1>; 134 reg = <0x900000 0x4000>; 135 clocks = <&cxo_board>, 136 <&pxo_board>, 137 <&lcc PLL4>; 138 clock-names = "cxo", "pxo", "pll4"; 139 }; 140 141 lcc: clock-controller@28000000 { 142 compatible = "qcom,lcc-msm8960"; 143 reg = <0x28000000 0x1000>; 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 clocks = <&pxo_board>, 147 <&gcc PLL4_VOTE>, 148 <0>, 149 <0>, <0>, 150 <0>, <0>, 151 <0>; 152 clock-names = "pxo", 153 "pll4_vote", 154 "mi2s_codec_clk", 155 "codec_i2s_mic_codec_clk", 156 "spare_i2s_mic_codec_clk", 157 "codec_i2s_spkr_codec_clk", 158 "spare_i2s_spkr_codec_clk", 159 "pcm_codec_clk"; 160 }; 161 162 clock-controller@4000000 { 163 compatible = "qcom,mmcc-msm8960"; 164 reg = <0x4000000 0x1000>; 165 #clock-cells = <1>; 166 #power-domain-cells = <1>; 167 #reset-cells = <1>; 168 clocks = <&pxo_board>, 169 <&gcc PLL3>, 170 <&gcc PLL8_VOTE>, 171 <0>, 172 <0>, 173 <0>, 174 <0>, 175 <0>; 176 clock-names = "pxo", 177 "pll3", 178 "pll8_vote", 179 "dsi1pll", 180 "dsi1pllbyte", 181 "dsi2pll", 182 "dsi2pllbyte", 183 "hdmipll"; 184 }; 185 186 l2cc: clock-controller@2011000 { 187 compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; 188 reg = <0x2011000 0x1000>; 189 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 190 clock-names = "pll8_vote", "pxo"; 191 #clock-cells = <0>; 192 }; 193 194 rpm: rpm@108000 { 195 compatible = "qcom,rpm-msm8960"; 196 reg = <0x108000 0x1000>; 197 qcom,ipc = <&l2cc 0x8 2>; 198 199 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 200 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 201 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 202 interrupt-names = "ack", "err", "wakeup"; 203 }; 204 205 acc0: clock-controller@2088000 { 206 compatible = "qcom,kpss-acc-v1"; 207 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 208 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 209 clock-names = "pll8_vote", "pxo"; 210 clock-output-names = "acpu0_aux"; 211 #clock-cells = <0>; 212 }; 213 214 acc1: clock-controller@2098000 { 215 compatible = "qcom,kpss-acc-v1"; 216 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 217 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 218 clock-names = "pll8_vote", "pxo"; 219 clock-output-names = "acpu1_aux"; 220 #clock-cells = <0>; 221 }; 222 223 saw0: regulator@2089000 { 224 compatible = "qcom,saw2"; 225 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 226 regulator; 227 }; 228 229 saw1: regulator@2099000 { 230 compatible = "qcom,saw2"; 231 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 232 regulator; 233 }; 234 235 gsbi5: gsbi@16400000 { 236 compatible = "qcom,gsbi-v1.0.0"; 237 cell-index = <5>; 238 reg = <0x16400000 0x100>; 239 clocks = <&gcc GSBI5_H_CLK>; 240 clock-names = "iface"; 241 #address-cells = <1>; 242 #size-cells = <1>; 243 ranges; 244 245 syscon-tcsr = <&tcsr>; 246 247 gsbi5_serial: serial@16440000 { 248 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 249 reg = <0x16440000 0x1000>, 250 <0x16400000 0x1000>; 251 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 253 clock-names = "core", "iface"; 254 status = "disabled"; 255 }; 256 }; 257 258 ssbi: ssbi@500000 { 259 compatible = "qcom,ssbi"; 260 reg = <0x500000 0x1000>; 261 qcom,controller-type = "pmic-arbiter"; 262 }; 263 264 rng@1a500000 { 265 compatible = "qcom,prng"; 266 reg = <0x1a500000 0x200>; 267 clocks = <&gcc PRNG_CLK>; 268 clock-names = "core"; 269 }; 270 271 sdcc3: mmc@12180000 { 272 compatible = "arm,pl18x", "arm,primecell"; 273 arm,primecell-periphid = <0x00051180>; 274 status = "disabled"; 275 reg = <0x12180000 0x8000>; 276 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 278 clock-names = "mclk", "apb_pclk"; 279 bus-width = <4>; 280 cap-sd-highspeed; 281 cap-mmc-highspeed; 282 max-frequency = <192000000>; 283 no-1-8-v; 284 vmmc-supply = <&vsdcc_fixed>; 285 }; 286 287 sdcc1: mmc@12400000 { 288 status = "disabled"; 289 compatible = "arm,pl18x", "arm,primecell"; 290 arm,primecell-periphid = <0x00051180>; 291 reg = <0x12400000 0x8000>; 292 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 294 clock-names = "mclk", "apb_pclk"; 295 bus-width = <8>; 296 max-frequency = <96000000>; 297 non-removable; 298 cap-sd-highspeed; 299 cap-mmc-highspeed; 300 vmmc-supply = <&vsdcc_fixed>; 301 }; 302 303 tcsr: syscon@1a400000 { 304 compatible = "qcom,tcsr-msm8960", "syscon"; 305 reg = <0x1a400000 0x100>; 306 }; 307 308 gsbi1: gsbi@16000000 { 309 compatible = "qcom,gsbi-v1.0.0"; 310 cell-index = <1>; 311 reg = <0x16000000 0x100>; 312 clocks = <&gcc GSBI1_H_CLK>; 313 clock-names = "iface"; 314 #address-cells = <1>; 315 #size-cells = <1>; 316 ranges; 317 318 gsbi1_spi: spi@16080000 { 319 compatible = "qcom,spi-qup-v1.1.1"; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 reg = <0x16080000 0x1000>; 323 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 324 cs-gpios = <&msmgpio 8 0>; 325 326 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 327 clock-names = "core", "iface"; 328 status = "disabled"; 329 }; 330 }; 331 332 usb1: usb@12500000 { 333 compatible = "qcom,ci-hdrc"; 334 reg = <0x12500000 0x200>, 335 <0x12500200 0x200>; 336 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 338 clock-names = "core", "iface"; 339 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 340 assigned-clock-rates = <60000000>; 341 resets = <&gcc USB_HS1_RESET>; 342 reset-names = "core"; 343 phy_type = "ulpi"; 344 ahb-burst-config = <0>; 345 phys = <&usb_hs1_phy>; 346 phy-names = "usb-phy"; 347 #reset-cells = <1>; 348 status = "disabled"; 349 350 ulpi { 351 usb_hs1_phy: phy { 352 compatible = "qcom,usb-hs-phy-msm8960", 353 "qcom,usb-hs-phy"; 354 clocks = <&sleep_clk>, <&cxo_board>; 355 clock-names = "sleep", "ref"; 356 resets = <&usb1 0>; 357 reset-names = "por"; 358 #phy-cells = <0>; 359 }; 360 }; 361 }; 362 }; 363}; 364