1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,lcc-msm8960.h> 8#include <dt-bindings/mfd/qcom-rpm.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 model = "Qualcomm MSM8960"; 15 compatible = "qcom,msm8960"; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 cxo_board: cxo_board { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <19200000>; 23 clock-output-names = "cxo_board"; 24 }; 25 26 pxo_board: pxo_board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <27000000>; 30 clock-output-names = "pxo_board"; 31 }; 32 33 sleep_clk: sleep_clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32768>; 37 clock-output-names = "sleep_clk"; 38 }; 39 }; 40 41 cpu-pmu { 42 compatible = "qcom,krait-pmu"; 43 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 44 qcom,no-pc-write; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 51 52 cpu@0 { 53 compatible = "qcom,krait"; 54 reg = <0>; 55 enable-method = "qcom,kpss-acc-v1"; 56 device_type = "cpu"; 57 next-level-cache = <&l2>; 58 qcom,acc = <&acc0>; 59 qcom,saw = <&saw0>; 60 }; 61 62 cpu@1 { 63 compatible = "qcom,krait"; 64 reg = <1>; 65 enable-method = "qcom,kpss-acc-v1"; 66 device_type = "cpu"; 67 next-level-cache = <&l2>; 68 qcom,acc = <&acc1>; 69 qcom,saw = <&saw1>; 70 }; 71 72 l2: l2-cache { 73 compatible = "cache"; 74 cache-level = <2>; 75 cache-unified; 76 }; 77 }; 78 79 memory@80000000 { 80 device_type = "memory"; 81 reg = <0x80000000 0>; 82 }; 83 84 soc: soc { 85 compatible = "simple-bus"; 86 ranges; 87 #address-cells = <1>; 88 #size-cells = <1>; 89 90 rpm: rpm@108000 { 91 compatible = "qcom,rpm-msm8960"; 92 reg = <0x108000 0x1000>; 93 qcom,ipc = <&l2cc 0x8 2>; 94 95 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 96 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 97 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 98 interrupt-names = "ack", 99 "err", 100 "wakeup"; 101 }; 102 103 ssbi: ssbi@500000 { 104 compatible = "qcom,ssbi"; 105 reg = <0x500000 0x1000>; 106 qcom,controller-type = "pmic-arbiter"; 107 }; 108 109 qfprom: efuse@700000 { 110 compatible = "qcom,msm8960-qfprom", "qcom,qfprom"; 111 reg = <0x00700000 0x1000>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 115 tsens_calib: calib@404 { 116 reg = <0x404 0x10>; 117 }; 118 119 tsens_backup: backup-calib@414 { 120 reg = <0x414 0x10>; 121 }; 122 }; 123 124 tlmm: pinctrl@800000 { 125 compatible = "qcom,msm8960-pinctrl"; 126 reg = <0x800000 0x4000>; 127 gpio-controller; 128 gpio-ranges = <&tlmm 0 0 152>; 129 #gpio-cells = <2>; 130 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-controller; 132 #interrupt-cells = <2>; 133 134 i2c1_default_state: i2c1-default-state { 135 i2c1-pins { 136 pins = "gpio8", "gpio9"; 137 function = "gsbi1"; 138 drive-strength = <8>; 139 bias-disable; 140 }; 141 }; 142 143 i2c1_sleep_state: i2c1-sleep-state { 144 i2c1-pins { 145 pins = "gpio8", "gpio9"; 146 function = "gpio"; 147 drive-strength = <2>; 148 bias-bus-hold; 149 }; 150 }; 151 152 i2c2_default_state: i2c2-default-state { 153 i2c2-pins { 154 pins = "gpio12", "gpio13"; 155 function = "gsbi2"; 156 drive-strength = <8>; 157 bias-disable; 158 }; 159 }; 160 161 i2c2_sleep_state: i2c2-sleep-state { 162 i2c2-pins { 163 pins = "gpio12", "gpio13"; 164 function = "gpio"; 165 drive-strength = <2>; 166 bias-bus-hold; 167 }; 168 }; 169 170 i2c3_default_state: i2c3-default-state { 171 i2c3-pins { 172 pins = "gpio16", "gpio17"; 173 function = "gsbi3"; 174 drive-strength = <8>; 175 bias-disable; 176 }; 177 }; 178 179 i2c3_sleep_state: i2c3-sleep-state { 180 i2c3-pins { 181 pins = "gpio16", "gpio17"; 182 function = "gpio"; 183 drive-strength = <2>; 184 bias-bus-hold; 185 }; 186 }; 187 188 i2c7_default_state: i2c7-default-state { 189 i2c7-pins { 190 pins = "gpio32", "gpio33"; 191 function = "gsbi7"; 192 drive-strength = <8>; 193 bias-disable; 194 }; 195 }; 196 197 i2c7_sleep_state: i2c7-sleep-state { 198 i2c7-pins { 199 pins = "gpio32", "gpio33"; 200 function = "gpio"; 201 drive-strength = <2>; 202 bias-bus-hold; 203 }; 204 }; 205 206 i2c8_default_state: i2c8-default-state { 207 i2c8-pins { 208 pins = "gpio36", "gpio37"; 209 function = "gsbi8"; 210 drive-strength = <8>; 211 bias-disable; 212 }; 213 }; 214 215 i2c8_sleep_state: i2c8-sleep-state { 216 i2c8-pins { 217 pins = "gpio36", "gpio37"; 218 function = "gpio"; 219 drive-strength = <2>; 220 bias-bus-hold; 221 }; 222 }; 223 224 i2c10_default_state: i2c10-default-state { 225 i2c10-pins { 226 pins = "gpio73", "gpio74"; 227 function = "gsbi10"; 228 drive-strength = <8>; 229 bias-disable; 230 }; 231 }; 232 233 i2c10_sleep_state: i2c10-sleep-state { 234 i2c10-pins { 235 pins = "gpio73", "gpio74"; 236 function = "gpio"; 237 drive-strength = <2>; 238 bias-bus-hold; 239 }; 240 }; 241 242 i2c12_default_state: i2c12-default-state { 243 i2c12-pins { 244 pins = "gpio44", "gpio45"; 245 function = "gsbi12"; 246 drive-strength = <8>; 247 bias-disable; 248 }; 249 }; 250 251 i2c12_sleep_state: i2c12-sleep-state { 252 i2c12-pins { 253 pins = "gpio44", "gpio45"; 254 function = "gpio"; 255 drive-strength = <2>; 256 bias-bus-hold; 257 }; 258 }; 259 260 sdcc3_default_state: sdcc3-default-state { 261 clk-pins { 262 pins = "sdc3_clk"; 263 drive-strength = <8>; 264 bias-disable; 265 }; 266 267 cmd-pins { 268 pins = "sdc3_cmd"; 269 drive-strength = <8>; 270 bias-pull-up; 271 }; 272 273 data-pins { 274 pins = "sdc3_data"; 275 drive-strength = <8>; 276 bias-pull-up; 277 }; 278 }; 279 280 sdcc3_sleep_state: sdcc3-sleep-state { 281 clk-pins { 282 pins = "sdc3_clk"; 283 drive-strength = <2>; 284 bias-disable; 285 }; 286 287 cmd-pins { 288 pins = "sdc3_cmd"; 289 drive-strength = <2>; 290 bias-pull-up; 291 }; 292 293 data-pins { 294 pins = "sdc3_data"; 295 drive-strength = <2>; 296 bias-pull-up; 297 }; 298 }; 299 }; 300 301 gcc: clock-controller@900000 { 302 compatible = "qcom,gcc-msm8960", "syscon"; 303 reg = <0x900000 0x4000>; 304 #clock-cells = <1>; 305 #reset-cells = <1>; 306 clocks = <&cxo_board>, 307 <&pxo_board>, 308 <&lcc PLL4>; 309 clock-names = "cxo", 310 "pxo", 311 "pll4"; 312 313 tsens: thermal-sensor { 314 compatible = "qcom,msm8960-tsens"; 315 316 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 317 nvmem-cell-names = "calib", "calib_backup"; 318 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 319 interrupt-names = "uplow"; 320 321 #qcom,sensors = <5>; 322 #thermal-sensor-cells = <1>; 323 }; 324 }; 325 326 intc: interrupt-controller@2000000 { 327 compatible = "qcom,msm-qgic2"; 328 reg = <0x02000000 0x1000>, 329 <0x02002000 0x1000>; 330 interrupt-controller; 331 #interrupt-cells = <3>; 332 }; 333 334 timer@200a000 { 335 compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", 336 "qcom,msm-timer"; 337 reg = <0x0200a000 0x100>; 338 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 339 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 340 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 341 clock-frequency = <27000000>; 342 clocks = <&sleep_clk>; 343 clock-names = "sleep"; 344 cpu-offset = <0x80000>; 345 }; 346 347 l2cc: clock-controller@2011000 { 348 compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; 349 reg = <0x2011000 0x1000>; 350 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 351 clock-names = "pll8_vote", "pxo"; 352 #clock-cells = <0>; 353 }; 354 355 acc0: clock-controller@2088000 { 356 compatible = "qcom,kpss-acc-v1"; 357 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 358 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 359 clock-names = "pll8_vote", "pxo"; 360 clock-output-names = "acpu0_aux"; 361 #clock-cells = <0>; 362 }; 363 364 saw0: power-manager@2089000 { 365 compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; 366 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 367 368 saw0_vreg: regulator { 369 regulator-min-microvolt = <850000>; 370 regulator-max-microvolt = <1300000>; 371 }; 372 }; 373 374 acc1: clock-controller@2098000 { 375 compatible = "qcom,kpss-acc-v1"; 376 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 377 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 378 clock-names = "pll8_vote", "pxo"; 379 clock-output-names = "acpu1_aux"; 380 #clock-cells = <0>; 381 }; 382 383 saw1: power-manager@2099000 { 384 compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; 385 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 386 387 saw1_vreg: regulator { 388 regulator-min-microvolt = <850000>; 389 regulator-max-microvolt = <1300000>; 390 }; 391 }; 392 393 clock-controller@4000000 { 394 compatible = "qcom,mmcc-msm8960"; 395 reg = <0x4000000 0x1000>; 396 #clock-cells = <1>; 397 #power-domain-cells = <1>; 398 #reset-cells = <1>; 399 clocks = <&pxo_board>, 400 <&gcc PLL3>, 401 <&gcc PLL8_VOTE>, 402 <0>, 403 <0>, 404 <0>, 405 <0>, 406 <0>; 407 clock-names = "pxo", 408 "pll3", 409 "pll8_vote", 410 "dsi1pll", 411 "dsi1pllbyte", 412 "dsi2pll", 413 "dsi2pllbyte", 414 "hdmipll"; 415 }; 416 417 sdcc3: mmc@12180000 { 418 compatible = "arm,pl18x", "arm,primecell"; 419 reg = <0x12180000 0x2000>; 420 arm,primecell-periphid = <0x00051180>; 421 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 423 clock-names = "mclk", "apb_pclk"; 424 bus-width = <4>; 425 cap-sd-highspeed; 426 cap-mmc-highspeed; 427 max-frequency = <192000000>; 428 no-1-8-v; 429 vmmc-supply = <&vsdcc_fixed>; 430 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 431 dma-names = "tx", "rx"; 432 433 status = "disabled"; 434 }; 435 436 sdcc3bam: dma-controller@12182000 { 437 compatible = "qcom,bam-v1.3.0"; 438 reg = <0x12182000 0x4000>; 439 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&gcc SDC3_H_CLK>; 441 clock-names = "bam_clk"; 442 #dma-cells = <1>; 443 qcom,ee = <0>; 444 }; 445 446 sdcc1: mmc@12400000 { 447 compatible = "arm,pl18x", "arm,primecell"; 448 reg = <0x12400000 0x2000>; 449 arm,primecell-periphid = <0x00051180>; 450 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 452 clock-names = "mclk", "apb_pclk"; 453 bus-width = <8>; 454 max-frequency = <96000000>; 455 non-removable; 456 cap-sd-highspeed; 457 cap-mmc-highspeed; 458 vmmc-supply = <&vsdcc_fixed>; 459 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 460 dma-names = "tx", "rx"; 461 462 status = "disabled"; 463 }; 464 465 sdcc1bam: dma-controller@12402000 { 466 compatible = "qcom,bam-v1.3.0"; 467 reg = <0x12402000 0x4000>; 468 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&gcc SDC1_H_CLK>; 470 clock-names = "bam_clk"; 471 #dma-cells = <1>; 472 qcom,ee = <0>; 473 }; 474 475 gsbi12: gsbi@12480000 { 476 compatible = "qcom,gsbi-v1.0.0"; 477 reg = <0x12480000 0x100>; 478 ranges; 479 cell-index = <12>; 480 clocks = <&gcc GSBI12_H_CLK>; 481 clock-names = "iface"; 482 #address-cells = <1>; 483 #size-cells = <1>; 484 485 status = "disabled"; 486 487 gsbi12_i2c: i2c@124a0000 { 488 compatible = "qcom,i2c-qup-v1.1.1"; 489 reg = <0x124a0000 0x1000>; 490 pinctrl-0 = <&i2c12_default_state>; 491 pinctrl-1 = <&i2c12_sleep_state>; 492 pinctrl-names = "default", "sleep"; 493 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&gcc GSBI12_QUP_CLK>, 495 <&gcc GSBI12_H_CLK>; 496 clock-names = "core", 497 "iface"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 501 status = "disabled"; 502 }; 503 }; 504 505 usb1: usb@12500000 { 506 compatible = "qcom,ci-hdrc"; 507 reg = <0x12500000 0x200>, 508 <0x12500200 0x200>; 509 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 511 clock-names = "core", "iface"; 512 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 513 assigned-clock-rates = <60000000>; 514 resets = <&gcc USB_HS1_RESET>; 515 reset-names = "core"; 516 phy_type = "ulpi"; 517 ahb-burst-config = <0>; 518 phys = <&usb_hs1_phy>; 519 phy-names = "usb-phy"; 520 #reset-cells = <1>; 521 522 status = "disabled"; 523 524 ulpi { 525 usb_hs1_phy: phy { 526 compatible = "qcom,usb-hs-phy-msm8960", 527 "qcom,usb-hs-phy"; 528 clocks = <&sleep_clk>, <&cxo_board>; 529 clock-names = "sleep", "ref"; 530 resets = <&usb1 0>; 531 reset-names = "por"; 532 #phy-cells = <0>; 533 }; 534 }; 535 }; 536 537 gsbi1: gsbi@16000000 { 538 compatible = "qcom,gsbi-v1.0.0"; 539 reg = <0x16000000 0x100>; 540 ranges; 541 cell-index = <1>; 542 clocks = <&gcc GSBI1_H_CLK>; 543 clock-names = "iface"; 544 #address-cells = <1>; 545 #size-cells = <1>; 546 547 status = "disabled"; 548 549 gsbi1_i2c: i2c@16080000 { 550 compatible = "qcom,i2c-qup-v1.1.1"; 551 reg = <0x16080000 0x1000>; 552 pinctrl-0 = <&i2c1_default_state>; 553 pinctrl-1 = <&i2c1_sleep_state>; 554 pinctrl-names = "default", "sleep"; 555 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&gcc GSBI1_QUP_CLK>, 557 <&gcc GSBI1_H_CLK>; 558 clock-names = "core", 559 "iface"; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 563 status = "disabled"; 564 }; 565 566 gsbi1_spi: spi@16080000 { 567 compatible = "qcom,spi-qup-v1.1.1"; 568 reg = <0x16080000 0x1000>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 572 cs-gpios = <&tlmm 8 0>; 573 clocks = <&gcc GSBI1_QUP_CLK>, 574 <&gcc GSBI1_H_CLK>; 575 clock-names = "core", 576 "iface"; 577 578 status = "disabled"; 579 }; 580 }; 581 582 gsbi2: gsbi@16100000 { 583 compatible = "qcom,gsbi-v1.0.0"; 584 reg = <0x16100000 0x100>; 585 ranges; 586 cell-index = <2>; 587 clocks = <&gcc GSBI2_H_CLK>; 588 clock-names = "iface"; 589 #address-cells = <1>; 590 #size-cells = <1>; 591 592 status = "disabled"; 593 594 gsbi2_i2c: i2c@16180000 { 595 compatible = "qcom,i2c-qup-v1.1.1"; 596 reg = <0x16180000 0x1000>; 597 pinctrl-0 = <&i2c2_default_state>; 598 pinctrl-1 = <&i2c2_sleep_state>; 599 pinctrl-names = "default", "sleep"; 600 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&gcc GSBI2_QUP_CLK>, 602 <&gcc GSBI2_H_CLK>; 603 clock-names = "core", 604 "iface"; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 608 status = "disabled"; 609 }; 610 }; 611 612 gsbi3: gsbi@16200000 { 613 compatible = "qcom,gsbi-v1.0.0"; 614 reg = <0x16200000 0x100>; 615 ranges; 616 cell-index = <3>; 617 clocks = <&gcc GSBI3_H_CLK>; 618 clock-names = "iface"; 619 #address-cells = <1>; 620 #size-cells = <1>; 621 622 status = "disabled"; 623 624 gsbi3_i2c: i2c@16280000 { 625 compatible = "qcom,i2c-qup-v1.1.1"; 626 reg = <0x16280000 0x1000>; 627 pinctrl-0 = <&i2c3_default_state>; 628 pinctrl-1 = <&i2c3_sleep_state>; 629 pinctrl-names = "default", "sleep"; 630 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&gcc GSBI3_QUP_CLK>, 632 <&gcc GSBI3_H_CLK>; 633 clock-names = "core", 634 "iface"; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 638 status = "disabled"; 639 }; 640 }; 641 642 gsbi5: gsbi@16400000 { 643 compatible = "qcom,gsbi-v1.0.0"; 644 reg = <0x16400000 0x100>; 645 ranges; 646 cell-index = <5>; 647 clocks = <&gcc GSBI5_H_CLK>; 648 clock-names = "iface"; 649 #address-cells = <1>; 650 #size-cells = <1>; 651 syscon-tcsr = <&tcsr>; 652 653 status = "disabled"; 654 655 gsbi5_serial: serial@16440000 { 656 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 657 reg = <0x16440000 0x1000>, 658 <0x16400000 0x1000>; 659 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&gcc GSBI5_UART_CLK>, 661 <&gcc GSBI5_H_CLK>; 662 clock-names = "core", 663 "iface"; 664 665 status = "disabled"; 666 }; 667 }; 668 669 gsbi7: gsbi@16600000 { 670 compatible = "qcom,gsbi-v1.0.0"; 671 reg = <0x16600000 0x100>; 672 ranges; 673 cell-index = <7>; 674 clocks = <&gcc GSBI7_H_CLK>; 675 clock-names = "iface"; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 679 status = "disabled"; 680 681 gsbi7_i2c: i2c@16680000 { 682 compatible = "qcom,i2c-qup-v1.1.1"; 683 reg = <0x16680000 0x1000>; 684 pinctrl-0 = <&i2c7_default_state>; 685 pinctrl-1 = <&i2c7_sleep_state>; 686 pinctrl-names = "default", "sleep"; 687 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&gcc GSBI7_QUP_CLK>, 689 <&gcc GSBI7_H_CLK>; 690 clock-names = "core", 691 "iface"; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 695 status = "disabled"; 696 }; 697 }; 698 699 gsbi8: gsbi@1a000000 { 700 compatible = "qcom,gsbi-v1.0.0"; 701 reg = <0x1a000000 0x100>; 702 ranges; 703 cell-index = <8>; 704 clocks = <&gcc GSBI8_H_CLK>; 705 clock-names = "iface"; 706 #address-cells = <1>; 707 #size-cells = <1>; 708 syscon-tcsr = <&tcsr>; 709 710 status = "disabled"; 711 712 gsbi8_serial: serial@1a040000 { 713 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 714 reg = <0x1a040000 0x1000>, 715 <0x1a000000 0x1000>; 716 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&gcc GSBI8_UART_CLK>, 718 <&gcc GSBI8_H_CLK>; 719 clock-names = "core", 720 "iface"; 721 722 status = "disabled"; 723 }; 724 725 gsbi8_i2c: i2c@1a080000 { 726 compatible = "qcom,i2c-qup-v1.1.1"; 727 reg = <0x1a080000 0x1000>; 728 pinctrl-0 = <&i2c8_default_state>; 729 pinctrl-1 = <&i2c8_sleep_state>; 730 pinctrl-names = "default", "sleep"; 731 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&gcc GSBI8_QUP_CLK>, 733 <&gcc GSBI8_H_CLK>; 734 clock-names = "core", 735 "iface"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 739 status = "disabled"; 740 }; 741 }; 742 743 gsbi10: gsbi@1a200000 { 744 compatible = "qcom,gsbi-v1.0.0"; 745 reg = <0x1a200000 0x100>; 746 ranges; 747 cell-index = <10>; 748 clocks = <&gcc GSBI10_H_CLK>; 749 clock-names = "iface"; 750 #address-cells = <1>; 751 #size-cells = <1>; 752 753 status = "disabled"; 754 755 gsbi10_i2c: i2c@1a280000 { 756 compatible = "qcom,i2c-qup-v1.1.1"; 757 reg = <0x1a280000 0x1000>; 758 pinctrl-0 = <&i2c10_default_state>; 759 pinctrl-1 = <&i2c10_sleep_state>; 760 pinctrl-names = "default", "sleep"; 761 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&gcc GSBI10_QUP_CLK>, 763 <&gcc GSBI10_H_CLK>; 764 clock-names = "core", 765 "iface"; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 769 status = "disabled"; 770 }; 771 }; 772 773 tcsr: syscon@1a400000 { 774 compatible = "qcom,tcsr-msm8960", "syscon"; 775 reg = <0x1a400000 0x100>; 776 }; 777 778 rng@1a500000 { 779 compatible = "qcom,prng"; 780 reg = <0x1a500000 0x200>; 781 clocks = <&gcc PRNG_CLK>; 782 clock-names = "core"; 783 }; 784 785 lcc: clock-controller@28000000 { 786 compatible = "qcom,lcc-msm8960"; 787 reg = <0x28000000 0x1000>; 788 #clock-cells = <1>; 789 #reset-cells = <1>; 790 clocks = <&pxo_board>, 791 <&gcc PLL4_VOTE>, 792 <0>, 793 <0>, 794 <0>, 795 <0>, 796 <0>, 797 <0>; 798 clock-names = "pxo", 799 "pll4_vote", 800 "mi2s_codec_clk", 801 "codec_i2s_mic_codec_clk", 802 "spare_i2s_mic_codec_clk", 803 "codec_i2s_spkr_codec_clk", 804 "spare_i2s_spkr_codec_clk", 805 "pcm_codec_clk"; 806 }; 807 }; 808 809 thermal-zones { 810 cpu0-thermal { 811 polling-delay-passive = <250>; 812 polling-delay = <1000>; 813 thermal-sensors = <&tsens 0>; 814 815 trips { 816 cpu_alert0: trip0 { 817 temperature = <60000>; 818 hysteresis = <10000>; 819 type = "passive"; 820 }; 821 822 cpu_crit0: trip1 { 823 temperature = <95000>; 824 hysteresis = <10000>; 825 type = "critical"; 826 }; 827 }; 828 }; 829 830 cpu1-thermal { 831 polling-delay-passive = <250>; 832 polling-delay = <1000>; 833 thermal-sensors = <&tsens 1>; 834 835 trips { 836 cpu_alert1: trip0 { 837 temperature = <60000>; 838 hysteresis = <10000>; 839 type = "passive"; 840 }; 841 842 cpu_crit1: trip1 { 843 temperature = <95000>; 844 hysteresis = <10000>; 845 type = "critical"; 846 }; 847 }; 848 }; 849 }; 850 851 /* Temporary fixed regulator */ 852 vsdcc_fixed: vsdcc-regulator { 853 compatible = "regulator-fixed"; 854 regulator-name = "SDCC Power"; 855 regulator-min-microvolt = <2700000>; 856 regulator-max-microvolt = <2700000>; 857 regulator-always-on; 858 }; 859}; 860