1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,lcc-msm8960.h> 8#include <dt-bindings/mfd/qcom-rpm.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 model = "Qualcomm MSM8960"; 15 compatible = "qcom,msm8960"; 16 interrupt-parent = <&intc>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 22 23 cpu@0 { 24 compatible = "qcom,krait"; 25 enable-method = "qcom,kpss-acc-v1"; 26 device_type = "cpu"; 27 reg = <0>; 28 next-level-cache = <&l2>; 29 qcom,acc = <&acc0>; 30 qcom,saw = <&saw0>; 31 }; 32 33 cpu@1 { 34 compatible = "qcom,krait"; 35 enable-method = "qcom,kpss-acc-v1"; 36 device_type = "cpu"; 37 reg = <1>; 38 next-level-cache = <&l2>; 39 qcom,acc = <&acc1>; 40 qcom,saw = <&saw1>; 41 }; 42 43 l2: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 }; 48 }; 49 50 memory@80000000 { 51 device_type = "memory"; 52 reg = <0x80000000 0>; 53 }; 54 55 thermal-zones { 56 cpu0-thermal { 57 polling-delay-passive = <250>; 58 polling-delay = <1000>; 59 thermal-sensors = <&tsens 0>; 60 61 trips { 62 cpu_alert0: trip0 { 63 temperature = <60000>; 64 hysteresis = <10000>; 65 type = "passive"; 66 }; 67 68 cpu_crit0: trip1 { 69 temperature = <95000>; 70 hysteresis = <10000>; 71 type = "critical"; 72 }; 73 }; 74 }; 75 76 cpu1-thermal { 77 polling-delay-passive = <250>; 78 polling-delay = <1000>; 79 thermal-sensors = <&tsens 1>; 80 81 trips { 82 cpu_alert1: trip0 { 83 temperature = <60000>; 84 hysteresis = <10000>; 85 type = "passive"; 86 }; 87 88 cpu_crit1: trip1 { 89 temperature = <95000>; 90 hysteresis = <10000>; 91 type = "critical"; 92 }; 93 }; 94 }; 95 }; 96 97 cpu-pmu { 98 compatible = "qcom,krait-pmu"; 99 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 100 qcom,no-pc-write; 101 }; 102 103 clocks { 104 cxo_board: cxo_board { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <19200000>; 108 clock-output-names = "cxo_board"; 109 }; 110 111 pxo_board: pxo_board { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <27000000>; 115 clock-output-names = "pxo_board"; 116 }; 117 118 sleep_clk: sleep_clk { 119 compatible = "fixed-clock"; 120 #clock-cells = <0>; 121 clock-frequency = <32768>; 122 clock-output-names = "sleep_clk"; 123 }; 124 }; 125 126 /* Temporary fixed regulator */ 127 vsdcc_fixed: vsdcc-regulator { 128 compatible = "regulator-fixed"; 129 regulator-name = "SDCC Power"; 130 regulator-min-microvolt = <2700000>; 131 regulator-max-microvolt = <2700000>; 132 regulator-always-on; 133 }; 134 135 soc: soc { 136 #address-cells = <1>; 137 #size-cells = <1>; 138 ranges; 139 compatible = "simple-bus"; 140 141 intc: interrupt-controller@2000000 { 142 compatible = "qcom,msm-qgic2"; 143 interrupt-controller; 144 #interrupt-cells = <3>; 145 reg = <0x02000000 0x1000>, 146 <0x02002000 0x1000>; 147 }; 148 149 timer@200a000 { 150 compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", 151 "qcom,msm-timer"; 152 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 153 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 154 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 155 reg = <0x0200a000 0x100>; 156 clock-frequency = <27000000>; 157 clocks = <&sleep_clk>; 158 clock-names = "sleep"; 159 cpu-offset = <0x80000>; 160 }; 161 162 qfprom: efuse@700000 { 163 compatible = "qcom,msm8960-qfprom", "qcom,qfprom"; 164 reg = <0x00700000 0x1000>; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 168 tsens_calib: calib@404 { 169 reg = <0x404 0x10>; 170 }; 171 172 tsens_backup: backup-calib@414 { 173 reg = <0x414 0x10>; 174 }; 175 }; 176 177 msmgpio: pinctrl@800000 { 178 compatible = "qcom,msm8960-pinctrl"; 179 gpio-controller; 180 gpio-ranges = <&msmgpio 0 0 152>; 181 #gpio-cells = <2>; 182 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 183 interrupt-controller; 184 #interrupt-cells = <2>; 185 reg = <0x800000 0x4000>; 186 }; 187 188 gcc: clock-controller@900000 { 189 compatible = "qcom,gcc-msm8960", "syscon"; 190 #clock-cells = <1>; 191 #reset-cells = <1>; 192 reg = <0x900000 0x4000>; 193 clocks = <&cxo_board>, 194 <&pxo_board>, 195 <&lcc PLL4>; 196 clock-names = "cxo", "pxo", "pll4"; 197 198 tsens: thermal-sensor { 199 compatible = "qcom,msm8960-tsens"; 200 201 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 202 nvmem-cell-names = "calib", "calib_backup"; 203 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 204 interrupt-names = "uplow"; 205 206 #qcom,sensors = <5>; 207 #thermal-sensor-cells = <1>; 208 }; 209 }; 210 211 lcc: clock-controller@28000000 { 212 compatible = "qcom,lcc-msm8960"; 213 reg = <0x28000000 0x1000>; 214 #clock-cells = <1>; 215 #reset-cells = <1>; 216 clocks = <&pxo_board>, 217 <&gcc PLL4_VOTE>, 218 <0>, 219 <0>, <0>, 220 <0>, <0>, 221 <0>; 222 clock-names = "pxo", 223 "pll4_vote", 224 "mi2s_codec_clk", 225 "codec_i2s_mic_codec_clk", 226 "spare_i2s_mic_codec_clk", 227 "codec_i2s_spkr_codec_clk", 228 "spare_i2s_spkr_codec_clk", 229 "pcm_codec_clk"; 230 }; 231 232 clock-controller@4000000 { 233 compatible = "qcom,mmcc-msm8960"; 234 reg = <0x4000000 0x1000>; 235 #clock-cells = <1>; 236 #power-domain-cells = <1>; 237 #reset-cells = <1>; 238 clocks = <&pxo_board>, 239 <&gcc PLL3>, 240 <&gcc PLL8_VOTE>, 241 <0>, 242 <0>, 243 <0>, 244 <0>, 245 <0>; 246 clock-names = "pxo", 247 "pll3", 248 "pll8_vote", 249 "dsi1pll", 250 "dsi1pllbyte", 251 "dsi2pll", 252 "dsi2pllbyte", 253 "hdmipll"; 254 }; 255 256 l2cc: clock-controller@2011000 { 257 compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; 258 reg = <0x2011000 0x1000>; 259 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 260 clock-names = "pll8_vote", "pxo"; 261 #clock-cells = <0>; 262 }; 263 264 rpm: rpm@108000 { 265 compatible = "qcom,rpm-msm8960"; 266 reg = <0x108000 0x1000>; 267 qcom,ipc = <&l2cc 0x8 2>; 268 269 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 270 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 271 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 272 interrupt-names = "ack", "err", "wakeup"; 273 }; 274 275 acc0: clock-controller@2088000 { 276 compatible = "qcom,kpss-acc-v1"; 277 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 278 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 279 clock-names = "pll8_vote", "pxo"; 280 clock-output-names = "acpu0_aux"; 281 #clock-cells = <0>; 282 }; 283 284 acc1: clock-controller@2098000 { 285 compatible = "qcom,kpss-acc-v1"; 286 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 287 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 288 clock-names = "pll8_vote", "pxo"; 289 clock-output-names = "acpu1_aux"; 290 #clock-cells = <0>; 291 }; 292 293 saw0: power-manager@2089000 { 294 compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; 295 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 296 297 saw0_vreg: regulator { 298 regulator-min-microvolt = <850000>; 299 regulator-max-microvolt = <1300000>; 300 }; 301 }; 302 303 saw1: power-manager@2099000 { 304 compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; 305 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 306 307 saw1_vreg: regulator { 308 regulator-min-microvolt = <850000>; 309 regulator-max-microvolt = <1300000>; 310 }; 311 }; 312 313 gsbi5: gsbi@16400000 { 314 compatible = "qcom,gsbi-v1.0.0"; 315 cell-index = <5>; 316 reg = <0x16400000 0x100>; 317 clocks = <&gcc GSBI5_H_CLK>; 318 clock-names = "iface"; 319 #address-cells = <1>; 320 #size-cells = <1>; 321 ranges; 322 323 syscon-tcsr = <&tcsr>; 324 325 status = "disabled"; 326 327 gsbi5_serial: serial@16440000 { 328 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 329 reg = <0x16440000 0x1000>, 330 <0x16400000 0x1000>; 331 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 333 clock-names = "core", "iface"; 334 status = "disabled"; 335 }; 336 }; 337 338 gsbi8: gsbi@1a000000 { 339 compatible = "qcom,gsbi-v1.0.0"; 340 cell-index = <8>; 341 reg = <0x1a000000 0x100>; 342 clocks = <&gcc GSBI8_H_CLK>; 343 clock-names = "iface"; 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges; 347 348 syscon-tcsr = <&tcsr>; 349 350 status = "disabled"; 351 352 gsbi8_serial: serial@1a040000 { 353 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 354 reg = <0x1a040000 0x1000>, 355 <0x1a000000 0x1000>; 356 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&gcc GSBI8_UART_CLK>, 358 <&gcc GSBI8_H_CLK>; 359 clock-names = "core", 360 "iface"; 361 362 status = "disabled"; 363 }; 364 }; 365 366 ssbi: ssbi@500000 { 367 compatible = "qcom,ssbi"; 368 reg = <0x500000 0x1000>; 369 qcom,controller-type = "pmic-arbiter"; 370 }; 371 372 rng@1a500000 { 373 compatible = "qcom,prng"; 374 reg = <0x1a500000 0x200>; 375 clocks = <&gcc PRNG_CLK>; 376 clock-names = "core"; 377 }; 378 379 sdcc3: mmc@12180000 { 380 compatible = "arm,pl18x", "arm,primecell"; 381 arm,primecell-periphid = <0x00051180>; 382 status = "disabled"; 383 reg = <0x12180000 0x2000>; 384 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 386 clock-names = "mclk", "apb_pclk"; 387 bus-width = <4>; 388 cap-sd-highspeed; 389 cap-mmc-highspeed; 390 max-frequency = <192000000>; 391 no-1-8-v; 392 vmmc-supply = <&vsdcc_fixed>; 393 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 394 dma-names = "tx", "rx"; 395 }; 396 397 sdcc3bam: dma-controller@12182000 { 398 compatible = "qcom,bam-v1.3.0"; 399 reg = <0x12182000 0x4000>; 400 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&gcc SDC3_H_CLK>; 402 clock-names = "bam_clk"; 403 #dma-cells = <1>; 404 qcom,ee = <0>; 405 }; 406 407 sdcc1: mmc@12400000 { 408 status = "disabled"; 409 compatible = "arm,pl18x", "arm,primecell"; 410 arm,primecell-periphid = <0x00051180>; 411 reg = <0x12400000 0x2000>; 412 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 414 clock-names = "mclk", "apb_pclk"; 415 bus-width = <8>; 416 max-frequency = <96000000>; 417 non-removable; 418 cap-sd-highspeed; 419 cap-mmc-highspeed; 420 vmmc-supply = <&vsdcc_fixed>; 421 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 422 dma-names = "tx", "rx"; 423 }; 424 425 sdcc1bam: dma-controller@12402000 { 426 compatible = "qcom,bam-v1.3.0"; 427 reg = <0x12402000 0x4000>; 428 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&gcc SDC1_H_CLK>; 430 clock-names = "bam_clk"; 431 #dma-cells = <1>; 432 qcom,ee = <0>; 433 }; 434 435 tcsr: syscon@1a400000 { 436 compatible = "qcom,tcsr-msm8960", "syscon"; 437 reg = <0x1a400000 0x100>; 438 }; 439 440 gsbi1: gsbi@16000000 { 441 compatible = "qcom,gsbi-v1.0.0"; 442 cell-index = <1>; 443 reg = <0x16000000 0x100>; 444 clocks = <&gcc GSBI1_H_CLK>; 445 clock-names = "iface"; 446 #address-cells = <1>; 447 #size-cells = <1>; 448 ranges; 449 450 status = "disabled"; 451 452 gsbi1_spi: spi@16080000 { 453 compatible = "qcom,spi-qup-v1.1.1"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 reg = <0x16080000 0x1000>; 457 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 458 cs-gpios = <&msmgpio 8 0>; 459 460 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 461 clock-names = "core", "iface"; 462 status = "disabled"; 463 }; 464 }; 465 466 usb1: usb@12500000 { 467 compatible = "qcom,ci-hdrc"; 468 reg = <0x12500000 0x200>, 469 <0x12500200 0x200>; 470 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 472 clock-names = "core", "iface"; 473 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 474 assigned-clock-rates = <60000000>; 475 resets = <&gcc USB_HS1_RESET>; 476 reset-names = "core"; 477 phy_type = "ulpi"; 478 ahb-burst-config = <0>; 479 phys = <&usb_hs1_phy>; 480 phy-names = "usb-phy"; 481 #reset-cells = <1>; 482 status = "disabled"; 483 484 ulpi { 485 usb_hs1_phy: phy { 486 compatible = "qcom,usb-hs-phy-msm8960", 487 "qcom,usb-hs-phy"; 488 clocks = <&sleep_clk>, <&cxo_board>; 489 clock-names = "sleep", "ref"; 490 resets = <&usb1 0>; 491 reset-names = "por"; 492 #phy-cells = <0>; 493 }; 494 }; 495 }; 496 497 gsbi3: gsbi@16200000 { 498 compatible = "qcom,gsbi-v1.0.0"; 499 reg = <0x16200000 0x100>; 500 ranges; 501 cell-index = <3>; 502 clocks = <&gcc GSBI3_H_CLK>; 503 clock-names = "iface"; 504 #address-cells = <1>; 505 #size-cells = <1>; 506 status = "disabled"; 507 508 gsbi3_i2c: i2c@16280000 { 509 compatible = "qcom,i2c-qup-v1.1.1"; 510 reg = <0x16280000 0x1000>; 511 pinctrl-0 = <&i2c3_default_state>; 512 pinctrl-1 = <&i2c3_sleep_state>; 513 pinctrl-names = "default", "sleep"; 514 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&gcc GSBI3_QUP_CLK>, 516 <&gcc GSBI3_H_CLK>; 517 clock-names = "core", "iface"; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 status = "disabled"; 521 }; 522 }; 523 }; 524}; 525#include "qcom-msm8960-pins.dtsi" 526